[AK4344] AK4344 100dB 96kHz 24-Bit Stereo 3.3V ΔΣ DAC AK4344 24 DAC ΔΣ 3.3V DR=100dB (SCF) AK4344 AK4344 24 MP3 16pin TSSOP STB, TV : 8kHz ∼ 96kHz 8 FIR SCF I/F : 24 (32kHz, 44.1kHz, 48kHz , 24/16 ) , I2S : 512/768/1024/1536fs for Half Speed (8kHz ∼ 24kHz) 256/384/512/768fs for Normal Speed (8kHz ∼ 48kHz) 128/192/256/384fs for Double Speed (48kHz ∼ 96kHz) µP : 4-wire/3-wire CMOS THD+N: -90dB(0dB) DR, S/N: 100dB DAC : 1Vrms (@VDD=3.3V) : 2.7 to 3.6V Ta = −20 ∼ 85°C : 16pin TSSOP MS0641-J-01 2010/09 -1- [AK4344] MCLK CSN CCLK CDTI µP Interface VDD De-emphasis Control CDTO SDTI1 LRCK BICK Audio Data Interface TEST1 PDN Clock Divider VSS VCOM 8X Interpolator ΔΣ Modulator SCF LPF LOUT 8X Interpolator ΔΣ Modulator SCF LPF ROUT TEST2 Figure 1. AK4344 (Mode= “0”) MCLK CSN CCLK CDTI SDTI2 SDTI1 LRCK µP Interface VDD De-emphasis Control Audio Data Interface BICK TEST1 PDN Clock Divider VSS VCOM 8X Interpolator ΔΣ Modulator SCF LPF LOUT 8X Interpolator ΔΣ Modulator SCF LPF ROUT TEST2 Figure 2. AK4344 (Mode= “1”) MS0641-J-01 2010/09 -2- [AK4344] ■ −20 ∼ +85°C AK4344 AK4344ET AKD4344 16pin TSSOP (0.65mm pitch) ■ MCLK 1 16 TEST2 BICK 2 15 CDTO/ SDTI2 SDTI1 3 14 VDD 13 VSS 12 VCOM AK4344 LRCK 4 PDN 5 CSN 6 11 LOUT CCLK 7 10 ROUT CDTI 8 9 TEST1 Top View MS0641-J-01 2010/09 -3- [AK4344] No. 1 2 3 4 Pin Name MCLK BICK SDTI1 LRCK I/O I I I I 5 PDN I 6 7 8 CSN CCLK CDTI I I I 9 TEST1 I 10 11 ROUT LOUT O O 12 VCOM O 13 14 VSS VDD CDTO SDTI2 O I TEST2 O 15 16 Function Master Clock Input Pin Audio Serial Data Clock Pin Audio Serial Data Input Pin1 Input Channel Clock Pin Full Power Down Mode Pin “L” : Power down, “H” : Power up Chip Select Pin 0 Control Data Clock Pin Control Data Input Pin TEST Pin This pin must be connected to VSS. Rch Analog Output Pin, The output is “Hi-Z” when PDN pin = “L”. Lch Analog Output Pin, The output is “Hi-Z” when PDN pin = “L”. Common Voltage Output Pin, 0.5 × VDD Normally connected to VSS with a 4.7μF (min. 1μF, max. 10μF) electrolytic Capacitor. The output is “L” when PDN pin = “L” Ground Pin Power Supply Pin, 2.7 ∼ 3.6V Control Data Output Pin in serial mode, The output is “Hi-Z” when PDN pin = “L”. Audio Serial Data Input Pin2 TEST Pin This pin must be OPEN. Note: MS0641-J-01 2010/09 -4- [AK4344] (VSS=0V; Note 1) Parameter Symbol Power Supply VDD Input Current, Any Pin Except Supplies IIN Digital Input Voltage (Note 2) VIND Ambient Temperature (Powered applied) Ta Storage Temperature Tstg Note 1. Note 2. MCLK, BICK, SDTI1, LRCK, PDN, CSN, CCLK, CDTI, SDTI2 min −0.3 −0.3 −20 −65 max 4.6 ±10 VDD+0.3 85 150 Units V mA V °C °C : (VSS=0V; Note 1) Parameter Power Supply Note 1. Symbol VDD min 2.7 typ 3.3 max 3.6 Units V : MS0641-J-01 2010/09 -5- [AK4344] (Ta=25°C; VDD=3.3V; VSS=0V; fs=44.1kHz, 96kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 20Hz ∼ 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units Dynamic Characteristics (GAIN bit= “1”) : Resolution 24 Bits 0dBFS THD+N fs=44.1kHz -90 -80 dB −60dBFS BW=20kHz −37 dB 0dBFS fs=96kHz -88 dB −60dBFS BW=40kHz −34 dB DR (−60dBFS with A-weighted) 92 100 dB S/N (A-weighted) 92 100 dB Interchannel Isolation 80 100 dB DC Accuracy: Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 100 ppm/°C Output Voltage: GAIN bit=“1” (Note 3) 2.60 2.8 3.00 Vpp Output Voltage: GAIN bit=“0” (Note 4) 2.05 2.2 2.35 Vpp Load Resistance (Note 5) 10 kΩ Load Capacitance 25 pF Power Supplies Power Supply Current Normal Operation (PDN pin = “H”, fs=44.1kHz) Normal Operation (PDN pin = “H”, fs=96kHz) Full Power-down mode (PDN pin = “L”) Note 3. (0dB) VDD Note 4. (0dB) VDD Note 5. AC Note 6. RSTN bit= “1”, PW bit= “1” Note 7. VDD VSS (Note 6) (Note 6) (Note 7) MS0641-J-01 7.0 12.8 8.5 50 10 Vout = 0.85 × VDD (typ). Vout = 0.67 × VDD (typ). mA mA μA 2010/09 -6- [AK4344] (Ta=25°C; VDD=2.7 ∼ 3.6V; fs=44.1kHz; DEM1 bit= “0”, DEM0 bit= “1”) Parameter Symbol min DAC Digital Filter: Passband (Note 8) ±0.05dB PB 0 −6.0dB Stopband (Note 8) SB 24.1 Passband Ripple PR Stopband Attenuation SA 54 Group Delay (Note 9) GD Digital Filter + SCF + CTF: FR Frequency Response 0 ∼ 20kHz 10) ∼ 40kHz (Note Note 8. fs ( ) Note 9. 16/24 typ max Units 22.05 20.0 - 24.0 - kHz kHz kHz dB dB 1/fs ±0.1 ±0.2 - dB dB ±0.01 Note 10. fs=96kHz. DC (Ta=25°C; VDD=2.7 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-80µA) Low-Level Output Voltage (Iout=80µA) Input Leakage Current Symbol VIH VIL VOH VOL Iin MS0641-J-01 min 70%VDD VDD-0.4 - typ - max 30%VDD 0.4 ± 10 Units V V V V µA 2010/09 -7- [AK4344] (Ta=25°C; VDD=2.7 ∼ 3.6V; CL = 20pF) Parameter Master Clock Frequency Half Speed Mode (512/768/1024/1536fs) Normal Speed Mode (256/384/512/768fs) Double Speed Mode (128/192/256/384fs) Duty Cycle LRCK Frequency Half Speed Mode (DFS1-0 = “10”) Normal Speed Mode (DFS1-0 = “00”) Double Speed Mode (DFS1-0 = “01”) Duty Cycle Audio Interface Timing BICK Period Half Speed Mode Normal Speed Mode Double Speed Mode BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge LRCK Edge to BICK “↑” SDTI Hold Time SDTI Setup Time Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” CDTO Delay CSN “↑” to CDTO Hi-Z Power-Down & Reset Timing PDN Pulse Width Note 11. LRCK Note 12. AK4344 PDN pin = “L” VCOM pin 4.7μF tPD min. 19ms VCOM pin DIF1-0 pin (Note 11) (Note 11) Symbol min fCLK fCLK fCLK dCLK typ max Units 4.096 2.048 6.144 40 36.864 36.864 36.864 60 MHz MHz MHz % fsh fsn fsd dCLK 8 8 48 45 24 48 96 55 kHz kHz kHz % tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fs 1/128fs 1/64fs 70 70 40 40 40 40 ns ns ns ns ns ns ns ns ns tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 80 80 40 40 150 150 50 ns ns ns ns ns ns ns ns ns ns 45 70 (Note 12) tPD BICK “↑” 4 (C) ms/μF tPD = 4 × C. 1μF ≤ C ≤ 10μF PDN pin MS0641-J-01 2010/09 -8- [AK4344] ■ 1/fCLK VIH MCLK VIL tCLKH tCLKL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tBCK VIH BICK VIL tBCKH tBCKL Figure 3. Clock Timing VIH LRCK VIL tBLR tLRB VIH BICK VIL tSDH tSDS VIH SDTI VIL Figure 4. Serial Interface Timing MS0641-J-01 2010/09 -9- [AK4344] VIH CSN VIL tCSS tCCK tCCKL tCCKH VIH CCLK VIL tCDH tCDS CDTI C1 C0 A4 R/W VIH VIL Hi-Z CDTO Figure 5. WRITE/READ Command Input Timing in 3-wire/4-wire serial mode tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 VIH D0 VIL Hi-Z CDTO Figure 6. WRITE Data Input Timing in 3-wire/4-wire serial mode VIH CSN VIL VIH CCLK VIL CDTI A1 VIH A0 VIL tDCD CDTO Hi-Z D7 D6 D5 50%VDD Figure 7. READ Data Output Timing 1 in 4-wire serial mode MS0641-J-01 2010/09 - 10 - [AK4344] tCSW VIH CSN VIL tCSH VIH CCLK VIL VIH CDTI VIL tCCZ CDTO D3 D2 D1 D0 Hi-Z 50%VDD Figure 8. READ Data Output Timing 2 in 4-wire serial mode tPD PDN VIL Figure 9. Power-Down & Reset Timing MS0641-J-01 2010/09 - 11 - [AK4344] ■ MCLK, LRCK, BICK (MCLK) (LRCK) MCLK MCLK LRCK Double speed Normal speed (Table 1) Auto MCLK MCLK MCLK, AK4344 ON Mode Normal Speed Double Speed Half Speed Auto DFS1 0 0 1 1 DFS0 fs 0 8 ∼ 48kHz 1 48 ∼ 96kHz 0 8 ∼ 24kHz 1 8 ∼ 96kHz Table 1. System Clock Example MCLK Frequency 512/768fs 128/192/256/384fs 1024/1536fs Sampling Speed Mode Normal Speed Double Speed Half Speed Table 2. Auto Mode ΔΣ DFS1-0 bit Half speed (DFS1 bit = DFS0 bit = “1”) (Table 2) VCOM MCLK, LRCK MCLK Frequency 256/384/512/768fs 128/192/256/384fs 512/768/1024/1536fs Table 2 Fs 8 ∼ 48kHz 48 ∼ 96kHz 8 ∼ 24kHz ■ 4 DIF1-0 bit 2’s BICK ≥ 48fs Mode 0 1 2 3 DIF1 0 0 1 1 DIF0 0 1 0 1 Table 3. (Table 3) BICK LSB “0” SDTI Format 16bit, LSB justified 24bit, LSB justified 24bit, MSB justified 16/24bit, I2S Compatible MS0641-J-01 MSB Mode 3 16 BICK = 32fs BICK ≥ 32fs ≥ 48fs ≥ 48fs ≥ 48fs or 32fs Figure Figure 10 Figure 11 Figure 12 Figure 13 2010/09 - 12 - [AK4344] LRCK 0 1 2 3 9 10 11 12 13 14 15 0 1 2 3 9 10 11 12 13 14 15 0 1 BICK(32fs) SDTI(i) 15 14 13 7 6 5 4 3 2 1 0 15 14 13 0 1 2 3 17 18 19 20 31 0 1 2 3 7 6 5 4 3 2 1 0 15 17 18 19 20 31 0 1 BICK(64fs) SDTI(i) Don't Care 15 14 13 12 1 0 Don't Care 15 14 13 12 2 1 0 SDTI-15:MSB, 0:LSB Lch Data Rch Data Figure 10. Mode 0 Timing LRCK 0 1 2 8 9 24 31 0 1 2 8 9 24 31 0 1 BICK(64fs) SDTI(i) Don't Care 23 1 0 8 Don't Care 8 23 1 0 23:MSB, 0:LSB Lch Data Rch Data Figure 11. Mode 1 Timing LRCK 0 1 2 20 21 22 23 24 31 0 1 2 20 21 22 23 24 31 0 1 BICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23 23:MSB, 0:LSB Lch Data Rch Data Figure 12. Mode 2 Timing LRCK 0 1 2 3 21 22 23 24 25 0 1 2 21 22 23 24 25 0 1 BICK(64fs) SDTI(i) 23 22 4 3 2 1 0 Don't Care 23 22 4 3 2 1 0 Don't Care 23:MSB, 0:LSB Lch Data Rch Data Figure 13. Mode 3 Timing MS0641-J-01 2010/09 - 13 - [AK4344] ■ AK4344 IIR ) Speed Mode 3 (32kHz, 44.1kHz, 48kHz) DEM1-0 bit Double Speed Mode (50/15μs Quad OFF DEM1 DEM0 Mode 0 0 1 1 0 1 0 1 44.1kHz OFF 48kHz 32kHz Table 4. (default) (Normal Speed Mode) ■ AK4344 PDN pin L PDN (1) Internal State Normal Operation Power-down D/A In (Digital) “0” data GD (2) GD (4) D/A Out (Analog) Clock In External MUTE (2) (4) (3) (5) Don’t care MCLK, BICK, LRCK (6) Mute ON Notes: (1) 19ms PDN pin “L” (VCOM pin VSS 4.7μF (2) (3) Hi-Z (4) PDN (“↑ ↓”) 3~4 LRCK (5) (6) Normal Operation ) (GD) 0 (PDN pin=“L”) (MCLK, BICK, LRCK) (4) Figure 14. / MS0641-J-01 2010/09 - 14 - [AK4344] ■ (1) RSTN bit RSTN bit “0” VCOM AK4344 DZFL/DZFR pin “H” Figure 15 RSTN bit RSTN bit 3~4/fs (6) 2~3/fs (6) Internal RSTN bit Internal State Normal Operation Normal Operation Digital Block P D/A In (Digital) d “0” data (1) GD GD (3) D/A Out (Analog) (2) (3) (1) (4) Clock In Don’t care MCLK,LRCK,BICK Notes: (1) (2) (3) RSTN (4) (5) RSTN bit (GD) VCOM ( (VDD/2) ) (RSTN bit = “0”) LSI 2 ~ 3/fs 0 (MCLK, BICK, LRCK) RSTN bit Figure 15. 3 ~ 4/fs 1 MS0641-J-01 2010/09 - 15 - [AK4344] (2) MCLK (PDN pin = “H”) MCLK VCOM AK4344 (1) PDN pin Internal State Power-down D/A In (Digital) Power-down Normal Operation (2) GD (4) Hi-Z VCOM (2) (4) (4) Clock In (5) MCLK Stop MCLK, BICK, LRCK External MUTE (6) Notes: (1) Normal Operation (3) GD D/A Out (Analog) Reset 19ms (6) PDN pin “L” (6) (VCOM pin VSS 4.7μF ) (2) (3) (GD) 0 (4) PDN pin (5) (6) ( (MCLK (4) ) 0 MCLK ) / MCLK 3 4LRCK (BICK, LRCK) Figure 16. 2 MS0641-J-01 2010/09 - 16 - [AK4344] ■ μP AK4344 4 1. 4 μP I/F mode (MODE bit = “0”) 3 μP I/F mode (MODE bit = “1”) μP I/F mode (MODE bit = “0”, default) 4 I/F pin(CSN,CCLK,CDTI,CDTO) I/F Chip address (2bits, C1/0; 01 ), Read/Write (1bit), Register address (MSB first, 5bits) Control data (MSB first, 8bits) CCLK CCLK 16 CCLK 16 CSN H CSN CDTO Hi Z CCLK 5MHz (max) PDN pin= L CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 WRITE Hi-Z CDTO CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 READ Hi-Z CDTO D7 D6 D5 D4 D3 D2 D1 D0 Hi-Z C1-C0: Chip Address: (Fixed to “01”) R/W: READ/WRITE (0:READ, 1:WRITE) A4-A0: Register Address D7-D0: Control Data Figure 17. 4 *AK4344 (PDN pin =“L”) I/F MCLK MS0641-J-01 2010/09 - 17 - [AK4344] 2. 3 μP I/F mode (MODE bit = “1”) 3 (2bits, C1/0; “01” (MSB first, 8bits) I/F pin (CSN,CCLK,CDTI) ), Read/Write (1bit, “1” , CCLK CCLK 16 CCLK 5MHz (max) I/F Chip address ), Register address (MSB first, 5bits) Control data CCLK 16 CSN PDN pin = “L” H RSTN bit CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1-C0: R/W: A4-A0: D7-D0: Chip Address (Fixed to “01”) READ/WRITE (Fixed to “1”, Write only) Register Address Control Data Figure 18. 3 *AK4344 3 *AK4344 I/F Chip address C1/0 MCLK (PDN pin = “L”) R/W 011 ■ DAC AK4344 4 μP I/F mode (MODE bit = “0”) DAC MODE 0 1 1 3 μP I/F mode (MODE bit = “1”) SDTI1 SDTI2 μP / IF 4-wire 3-wire 3-wire SEL x 0 1 3 DAC input SDTI1 SDTI1 SDTI2 (x: Don’t care) Table 5. DAC MS0641-J-01 2010/09 - 18 - [AK4344] ■ Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 1 0 0 0 DIF1 DIF0 PW RSTN 01H 02H Control 2 Control 3 0 0 1 0 0 0 DFS1 INVL DFS0 INVR DEM1 MODE DEM0 0 GAIN SEL Notes: 05H→1FH PDN pin “L” RSTN bit = “0” PW bit, RSTN bit “0” “1” “0” “0” “1” ■ Addr 00H Register Name Control 1 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 DIF1 DIF0 PW RSTN 1 1 1 1 R/W Default R/W 1 0 0 0 RSTN: 0: Reset. 1: Normal Operation MCLK DFS RSTN bit PW: 0: Power down. 1: Normal Operation DIF1-0: (Table 3) Initial: “11”, Mode 3 MS0641-J-01 2010/09 - 19 - [AK4344] Addr 01H Register Name Control 2 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 DFS1 DFS0 DEM1 DEM0 GAIN 1 0 1 1 R/W R/W Default 0 DEM1-0: 1 0 1 (Table 4) Initial: “01”, OFF DFS1-0: 00: Normal speed 01: Double speed 10: Half speed 11: Auto (default) Normal/ Double/ Half Speed Mode GAIN: 0: Vout = 0.67 × VDD (typ) at Full-scale voltage(0dB). 1: Vout = 0.85 × VDD (typ) at Full-scale voltage(0dB). Register Name 02H Control 3 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 INVL INVR MODE 0 SEL 0 0 0 0 R/W R/W Default 0 0 0 0 INVR: Rch 0: Normal Output 1: Inverted Output INVL: Lch 0: Normal Output 1: Inverted Output MODE: 0: 4 1: 3 SEL: DAC 0: SDTI1 input 1: SDTI2 input 4 uP I/F mode (MODE bit = “0”) MS0641-J-01 2010/09 - 20 - [AK4344] Figure 19 Figure 20 (AKD4344) Master Clock 1 MCLK TEST2 16 64fs 2 BICK CDTO 15 24bit Audio Data 3 SDTI VDD 14 fs Reset & Power down Micro Controller Digital Ground 0.1u + Analog Supply 2.7 to 3.6V 10u 4 LRCK VSS 13 5 PDN VCOM 12 6 CSN LOUT 11 Lch Out 7 CCLK ROUT 10 Rch Out 8 CDTI TEST1 9 AK4344 4.7u + Analog Ground Figure 19. Typical Connection Diagram (Mode bit = “0”, 4 ) 24bit Audio Data2 Master Clock 1 MCLK TEST2 16 64fs 2 BICK SDTI2 15 3 SDTI VDD 14 24bit Audio Data1 fs Reset & Power down Micro Controller Digital Ground 0.1u 4 LRCK 5 + Analog Supply 2.7 to 3.6V 10u VSS 13 PDN VCOM 12 6 CSN LOUT 11 Lch Out 7 CCLK ROUT 10 Rch Out 8 CDTI TEST1 9 AK4344 4.7u + Analog Ground Figure 20. Typical Connection Diagram (Mode bit = “1”, 3 MS0641-J-01 ) 2010/09 - 21 - [AK4344] 1. VDD VSS PC 2. VDD VSS VCOM 4.7μF 0.1μF VSS VSS1 VCOM pin 3. VCOM (0.5 VDD) ) (SCF) 2 s compliment (2 ) 7FFFFFH(@24bit) 000000H(@24bit) VCOM ( (CTF) 800000H(@24bit) (0.5 x VDD) LSI VCOM mV 2.8Vpp (1Vrms) DC LFP Figure 21 AK4344 10u 220 Analog Out LOUT / ROUT 2.8Vpp (1Vrms) 22k 1nF fc=723.4kHz, g=-0.013dB at 40kHz st Figure 21. External 1 order LPF Circuit Example MS0641-J-01 2010/09 - 22 - [AK4344] 16pin TSSOP (Unit: mm) 1.1 (max) *5.0±0.1 16 9 8 1 0.13 6.4±0.2 *4.4±0.1 A 0.65 0.22±0.1 M 0.17±0.05 Detail A 0.5±0.2 0.1±0.1 Seating Plane 0.10 NOTE: Dimension "*" does not include mold flash. 0-10° ■ : : : ( ) MS0641-J-01 2010/09 - 23 - [AK4344] AKM 4344ET XXYYY 1) 2) 3) 4) Date (YY/MM/DD) 09/05/19 10/09/28 Revision 00 01 Reason Pin #1 indication Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code Marketing Code : 4344ET Asahi Kasei Logo Page Contents 23 MS0641-J-01 2010/09 - 24 - [AK4344] z z z z z z MS0641-J-01 2010/09 - 25 -