[AK1590]
AK1590
1GHz Delta-Sigma Fractional-N Frequency Synthesizer
1. Overview
AK1590 is a Delta-Sigma Fractional-N PLL (Phase Locked Loop) frequency synthesizer with a frequency switching
function, covering a wide range of frequencies from 60 to 1000MHz. This product consists of an 18-bit Delta-Sigma
modulator, a low-noise phase frequency comparator, a highly accurate charge pump, a reference divider and dual-module
prescaler (P/P+1) and frequency offset adjustable circuits.
2. Features
Operating frequency:
60 to 1000MHz
Programmable charge pump current:
In a normal operating scheme, the charge pump current can be set
in 8 steps, in the range from 20 to 168μA.
In a Fast Lockup scheme, the charge pump current can be set in
8 steps, in the range from 0.8 to 2.3mA.
Supply Voltage:
2.7 to 5.5 V (PVDD pin)
Separate power supply for the charge pump:
PVDD to 5.5V (CPVDD pin)
On-chip power-saving features
Frequency offset adjustable function:
No glitch operation for AFC(Automatic Frequency Control) and
DFM(Digital Frequency Modulation)
General-purpose output:
Two general-purpose output ports to control peripheral parts
Low phase noise:
-201dBc/Hz
Low consumption current:
2.5mA typ
Package:
24pin QFN (0.5mm pitch, 4mm4mm0.7mm)
Operating temperature:
-40 to +85°C
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Table of Contents
1.
Overview ___________________________________________________________________________ 1
2.
Features ___________________________________________________________________________ 1
3.
Block Diagram ______________________________________________________________________ 3
4.
Pin Functional Description ____________________________________________________________ 4
5.
Absolute Maximum Ratings ___________________________________________________________ 6
6.
Recommended Operating Range _______________________________________________________ 6
7.
Electrical Characteristics ______________________________________________________________ 7
8.
Block Functional Descriptions ________________________________________________________ 11
9.
Register Map _______________________________________________________________________ 19
10.
Register Functional Description _______________________________________________________ 20
11.
IC Interface Schematic _______________________________________________________________ 27
12.
Recommended Connection Schematic for Off-Chip Components ___________________________ 29
13.
Power-up Sequence _________________________________________________________________ 31
14.
Typical Evaluation Board Schematic ___________________________________________________ 32
15.
Block Diagram by Power Supply_______________________________________________________ 33
16.
Outer Dimensions___________________________________________________________________ 34
17.
Marking ___________________________________________________________________________ 35
In this specification, the following notations are used for specific signal and register names:
[Name] : Pin name
<Name> : Register group name (Address name)
{Name} : Register bit name
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CPVSS
CPVDD
PVDD
PVSS
VREF
DVSS
3. Block Diagram
LDO
BIAS
R COUNTER
8bit
REFIN
CHARGE PUMP 1
CP
PHASE
FREQENCY
DETECTOR
CLK
CHARGE PUMP 2
(For Fast Lock Up)
REGISTER
24bit
DATA
LE
NUM
+
FAST
COUNTER
13bit
OFFSET
N DIVIDER
ΔΣ
18bit
SUM
CPZ
LOCK DETECT
SWIN
PULSE
SWALLOW
COUNTER
INT
GPO2
GPO1
PDN2
PDN1
-
TEST3
RFINN
LD
PRESCALER
4/5, 8/9,16/17
TEST2
+
TEST1
RFINP
Fig. 1 Block Diagram
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4. Pin Functional Description
Table 1 Pin Function
No.
Name
I/O
1
CPVDD
P
Power supply for charge pump
2
TEST3
DI
Test pin 3. This pin must be connected to ground.
3
TEST1
DI
Test pin 1. This pin must be connected to ground.
4
LE
DI
Load enable
Schmidt trigger input
5
DATA
DI
Serial data input
Schmidt trigger input
6
CLK
DI
Serial clock
Schmidt trigger input
7
LD
DO
Lock detect
8
PDN2
DI
Power down pin for PLL
Schmidt trigger input
9
PDN1
DI
Power down signal for LDO
Schmidt trigger input
10
REFIN
AI
Reference input
11
TEST2
DI
Test pin 2. This pin must be connected to ground.
12
GPO1
DO
General-purpose output pin 1
Low
13
GPO2
DO
General-purpose output pin 2
Low
14
DVSS
G
15
VREF
AIO
16
RFINN
AI
Prescaler input
17
RFINP
AI
Prescaler input
18
PVDD
P
Power supply for peripherals
19
BIAS
AIO
20
PVSS
G
21
CP
AO
Charge pump output
22
CPZ
AIO
Connect to the loop filter capacitor
Note 1, Note 2
23
SWIN
AI
Connect to resistance pin for Fast Lockup
Note 1, Note 2
24
CPVSS
G
Ground pin for charge pump
Note 1)
Note 2)
Pin Functions
Power down
Remarks
Internal pull-down,
Schmidt trigger input
Internal pull-down,
Schmidt trigger input
Low
Internal pull-down,
Schmidt trigger input
Digital ground pin
Connect to LDO reference voltage capacitor
Low
Resistance pin for setting charge pump output
current
Ground pin for peripherals
Hi-Z
For detailed functional descriptions, see the section “Charge Pump and Loop Filter” in “8. Block Functional
Description” below.
The input voltage from [CPZ] pin is used in the internal circuit. [CPZ] pin must not be open even when the Fast
Lockup feature is unused. For the output destination from [CPZ] pin, see “Fig.5 Loop Filter Schematic”.
[SWIN] pin could be open when the Fast Lockup feature is not used.
The state of loop filter switch is ON when “[PDN1]=Low, [PDN2]=Low” or “[PDN1]=High, [PDN2]=Low”.
Note 3)
Power down means the state where [PDN1]=[PDN2]=Low after power on.
AI: Analog input pin
AO: Analog output pin
AIO: Analog I/O pin
DO: Digital output pin
P: Power supply pin
G: Ground pin
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CPVSS
SWIN
CPZ
CP
PVSS
BIAS
[AK1590]
24
23
22
21
20
19
CPVDD
1
18 PVDD
TEST3
2
17 RFINP
TEST1
3
LE
4
DATA
5
14 DVSS
CLK
6
13 GPO2
16 RFINN
TOP
10
11
12
TEST2
GPO1
9
15 VREF
REFIN
8
PDN1
LD
7
PDN2
VIEW
Fig. 2 Package Pin Layout
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5. Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Unit
VDD1
-0.3
6.5
V
Note 1, Note 2
VDD2
-0.3
6.5
V
Note 1, Note 3
VSS1
0
0
V
Voltage ground level, Note 4
VSS2
0
0
V
Voltage ground level, Note 5
VSS3
0
0
V
Voltage ground level, Note 6
VAIN1
VSS1-0.3
VDD1+0.3
V
Note 1, Note 7, Note 10
VAIN2
VSS2-0.3
VDD2+0.3
V
Note 1, Note 8, Note 10
VDIN
VSS3-0.3
VDD1+0.3
V
Note 1, Note 9, Note 10
Input Current
IIN
-10
10
mA
Storage Temperature
Tstg
-55
125
°C
Supply Voltage
Ground Level
Analog Input Voltage
Digital Input Voltage
Note 1)
0V reference for all voltages.
Note 2)
Applied to [PVDD] pin.
Note 3)
Applied to [CPVDD] pin
Note 4)
Applied to [PVSS] pin.
Remarks
Note 5) Applied to [CPVSS] pin.
Note 6)
Applied to [DVSS] pin.
Note 7)
Applied to [REFIN], [RFINN] and [RFINP] pins.
Note 8)
Applied to [CPZ] and [SWIN] pins.
Note 9)
Applied to [CLK], [DATA], [LE], [PDN1] and [PDN2] pins.
Note 10) Maximum must not be over 6.5V.
Exceeding these maximum ratings may result in damage to AK1590. Normal operation is not guaranteed at these
extremes.
6. Recommended Operating Range
Table 3 Recommended Operating Range
Parameter
Operating Temperature
Supply Voltage
Symbol
Min.
Ta
-40
VDD1
2.7
VDD2
VDD1
Typ.
Max.
Unit
Remarks
85
C
3.3
5.5
V
Applied to [PVDD] pin
5.0
5.5
V
Applied to [CPVDD] pin
VDD1 and VDD2 can be driven individually within the recommended operating range.
The specifications are applicable within the recommended operating range (supply voltage / operating temperature).
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7. Electrical Characteristics
1. Digital DC Characteristics
Table 4 Digital DC Characteristics
Parameter
Symbol
Conditions
Min.
High level input voltage
Vih
Low level input voltage
Vil
High level input current
Iih
Vih = VDD1 = 5.5V
Low level input current
Iil
Vil = 0V, VDD1 = 5.5V
Max.
Voh
Ioh = -500A
Low level output voltage
Vol
Iol = 500A
0.2VDD1
V
Note 1
-1
1
A
Note 1
-1
1
A
Note 1
V
Note 2
V
Note 2
0.4
Applied to [CLK], [DATA], [LE], [PDN1] and [PDN2] pins.
Note 2)
Applied to [LD], [GPO1] and [GPO2] pins.
7
Remarks
Note 1
VDD1-0.4
Note 1)
Unit
V
0.8VDD1
High level output voltage
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2. Serial Interface Timing
<Write-In Timing>
Tlesu
Tle
Tcsu
LE
(Input)
Tch
Tcl
CLK
(Input)
Tsu
DATA
(Input)
D19
Thd
D0
D18
A3
A2
A1
A0
D19
Fig. 3 Serial Interface Timing Chart
Table 5 Serial Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
Unit
Clock L level hold time
Tcl
40
ns
Clock H level hold time
Tch
40
ns
Clock setup time
Tcsu
20
ns
Data setup time
Tsu
20
ns
Data hold time
Thd
20
ns
LE Setup Time
Tlesu
20
ns
LE Pulse Width
Tle
40
ns
Remarks
Note 1) While [LE] pin is setting at “Low”, 24 iteration clocks have to be set with [CLK] pin. If 25 or more clocks are set,
the last 24 clocks synchronized data are valid.
Note 2)
OFFSET register must be written at the lower speed than calculated frequency by
“1/3.5RF Frequency/(INT+7)”. If the writing speed is faster than this, the setting is invalid.
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3. Analog Circuit Characteristics
The resistance of 27kΩ is connected to [BIAS] pin, VDD1 = 2.7V to 5.5V, VDD2 = VDD1 to 5.5V, –40°C ≤ Ta ≤ 85°C
Parameter
Min.
Typ.
Max.
Unit
Remarks
RF Characteristics
Input Sensitivity
Input Frequency
-10
+5
dBm
60
500
MHz
Prescaler 4/5
60
1000
MHz
Prescaler 8/9,16/17
REFIN Characteristics
Input Sensitivity
0.4
2
Vpp
Input Frequency
5
40
MHz
125
MHz
Prescaler
Maximum Allowable Prescaler Output
Frequency
Phase Detector
Phase Detector Frequency
5
MHz
Charge Pump
Charge Pump 1 Maximum Current
168.9
A
Charge Pump 1 Minimum Current
21.1
A
Charge Pump 2 Maximum Current
2.32
mA
Charge Pump 2 Minimum Current
0.84
mA
1
nA
0.6 ≤ Vcpo ≤ VDD2-0.7
Icp TRI-STATE Leak Current
Mismatch between Source and Sink Currents
(Note 1)
10
%
Vcpo = VDD2/2, Ta = 25°C
Icp vs. Vcpo (Note 2)
15
%
0.5 ≤ Vcpo ≤ VDD2-0.5, Ta = 25°C
50
s
Regulator
VREF Rise Time
Current Consumption
IDD1
10
A
3.6
mA
IDD2
2.4
IDD3
0.17
mA
IDD4
0.5
mA
Power Down mode
[PDN1]=“Low”, [PDN2]=”Low"
[PDN1]=”High”, [PDN2]=”High”
IDD for [PVDD]
[PDN1]=”High”, [PDN2]=”High”
IDD for [CPVDD] (Note 3)
Power Save mode
[PDN1]=“High”, [PDN2]=”Low"
Note 1)
Mismatch between Source and Sink Currents: [(|Isink|-|Isource|)/{(|Isink|+|Isource|)/2}] × 100 [%]
Note 2)
See “Fig. 4 Charge Pump Characteristics - Voltage vs. Current”: Icp vs. Vcpo:
[{1/2×(|I1|-|I2|)}/{1/2×(|I1|+|I2|)}]×100 [%]
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Note 3)
IDD3 is the current that consumes constantly at [CPVDD]. This does not include the operation current in Fast
Lockup mode.
Note 4) When both [PDN1] and [PDN2] are ”High”, the total current consumption is equivalent to “IDD2+IDD3”.
Note 5)
In the shipment test, the exposed pad on the center of the back of package is connected to ground.
Resistance Connected to BIAS Pin for Setting Charge Pump Output Current
Parameter
BIAS resistance
Min.
Typ.
Max.
Unit
22
27
33
kΩ
Remarks
Icp
I1
I2
I2
I1
Isink
Isource
0.5
VDD2/2
VDD2 - 0.5
Vcpo
Fig. 4 Charge Pump Characteristics - Voltage vs. Current
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8. Block Functional Descriptions
1. Frequency Setup
AK1590 is a Fractional-N type synthesizer that takes 2
18
as the denominator, which calculates the integer and numerator
to be set using the following formulas:
18
Frequency setting = FPFD × (Integer + Numerator / 2 )
Integer = ROUND (Target Frequency / FPFD)
18
Numerator = ROUND {(Target Frequency – Integer × FPFD) / (FPFD / 2 )}
Note)
ROUND: Rounded off to the nearest integer
FPFD : Phase Frequency Detector comparative Frequency (= [REFIN] input frequency / R divider ratio)
Calculation examples
Example 1)
The numerator is positive; when the target frequency is 950.0375MHz and FPFD is 1MHz.
Integer = 950.0375MHz / 1MHz = 950.0375
It is rounded off to 950 (decimal) = 3B6 (hexadecimal) = 0011 1011 0110 (binary)
18
Numerator = (950.0375MHz - 950 × 1MHz) / (1MHz / 2 ) = 9830.4
It is rounded off to 9830 (decimal) = 2666 (hexadecimal) = 10 0110 0110 0110 (binary)
18
Frequency setting =1MHz × (950 + 9830 / 2 ) = 950.0374985MHz
(In this case the frequency error is 1.5Hz.)
Example 2)
The numerator is negative; when the target frequency is 950.550MHz and FPFD is 1MHz.
Integer = 950.550MHz / 1MHz = 950.550
It is rounded off to 951 (decimal) = 3B7 (hexadecimal) = 0011 1011 0111 (binary)
18
Numerator = (950.550MHz - 951 × 1MHz) / (1MHz / 2 ) = -117964.8
It is rounded off to -117965 (decimal), which is reduced from 2
18
to be converted into
binary for 2's complementary expression.
18
2 - 117965 (decimal) = 144179 (decimal) = 23333 (hexadecimal) = 10 0011 0011 0011
0011 (binary)
18
Frequency setting =1MHz × (951 + (-117965/2 )) = 950.5499992MHz
(In this case the frequency error is 0.8Hz.)
Calculation of 2’s complement representation
1)
Positive number:
Binary expression (Unmanipulated)
exp. 100 (decimal)
64 (hexadecimal) = 110 0100 (binary)
2)
Negative number:
2
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2 minus this number in binary expression
exp. –100 (decimal)
- 100 = 262044 (decimal) = 3FF9C (hexadecimal) = 11 1111 1111 1001 1100 (binary)
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2. Charge Pump and Loop Filter
AK1590 has two charge pumps; Charge Pump 1 for normal operation and Charge Pump 2 for Fast Lockup mode.
The internal timer is used to switch these two charge pumps to achieve a Fast Lock PLL.
The loop filter is external and connected to [CP], [SWIN] and [CPZ] pins. [CPZ] pin should be connected to R2 and C2 ,
which are intermediate nodes, even if the Fast Lockup is not used. Therefore, R2 must be connected to [CP] pin, while C2
must be connected to the ground.
R2 and R2’ are connected in parallel with internal switch in Fast Lockup. These R2 and R2’ parallel resistance value is
required for calculating loop bandwidth and phase margin in Fast Lockup operation.
Phase Detector
Loop Filter
up
R3
CP
VCO
C1
down
R2'
R2
C3
Timer
SWIN
C2
CPZ
Fig. 5 Loop Filter Schematic
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3. Fast Lockup Mode
Setting D[16] = {FASTEN} in <Address4> to “1” enables the Fast Lockup mode for AK1590.
Changing a frequency setting (The frequency changes at the rising edge of [LE], when <Address1> and <Address2> are
accessed.) or [PDN2] pin is turned from ”Low” to ”High” with {FASTEN}=1 enables the Fast Lockup mode. The loop filter
switch turns ON during the timer period specified by the counter value in D[12:0] = {FAST[12:0]} in <Address4>, and the
charge pump for the Fast Lockup mode (Charge Pump 2) is enabled. After the timer period elapsed, the loop filter switch
turns OFF. The charge pump for normal operation (Charge Pump 1) is enabled. D[12:0] ={ FAST[12:0]} in <Address4> is
used to set the timer period for this mode.
The following formula is used to calculate the time period:
Phase detector frequency cycle × counter value set in {FAST[12:0]}
The charge pump current can be adjusted with the register setting in 8 steps in normal operation (Charge Pump 1) and 8
steps in the Fast Lockup operation (Charge Pump 2).
The charge pump current for normal operation (Charge Pump 1) is determined by the setting in {CP1[2:0]}, which is a 3-bit
address of D[17:15] in <Address2>, and a value of the resistance connected to [BIAS] pin. The following formulas show
the relationship between the resistance value, the register setting and the current.
Charge Pump 1 minimum current (CP1_min) = 0.57 / Resistance connected to [BIAS] pin
Charge Pump 1 current = CP1_min × ({CP1[2:0]} + 1)
The charge pump current for the Fast Lockup mode operation (Charge Pump 2 current) is determined by the setting in
{CP2[2:0]}, which is a 3-bit address of D[15:13] in <Address4>, and a value of the resistance connected to [BIAS] pin. The
following formulas show the relationship between the resistance value, the register setting and the current.
Charge Pump 2 minimum current (CP2_min) = 5.7 / Resistance connected to [BIAS] pin
Charge Pump 2 current = CP2_min × ({CP2[2:0]} + 4)
The allowed range for the resistance (connected to [BIAS] pin) is from 22 to 33kΩ for both normal and Fast Lockup mode
operations. For details of current settings, see ”10. Register Functional Description”.
Fast Lockup time specified
by the timer
Operation
Normal
Fast Lockup Mode
Normal
Charge Pump 1
Charge Pump 2
Charge Pump 1
OFF
ON
OFF
mode
Charge pump
Loop filter switch
The frequency changes or [PDN2] pin is set from ”Low” to ”High”
during D[16] = {FSTEN} in < Address4 > is set to”1”.
Fig. 6 Timing Chart for Fast Lockup Mode
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4. Lock Detect (LD) Signal
In AK1590, “lock detect” output can be selected by D[11] = {LD} in <Address3>. When D[11] is set to “1", the phase
detector output provides a phase detection status as an analog level (comparison result). This is called “Analog Lock
Detect”.
When D[11] is set to “0”, the lock detect signal outputs according to the on-chip logic. This is called “Digital Lock Detect”.
4.1 Analog Lock Detect
In analog lock detect, the phase detector output comes from [LD] pin.
Reference clock
PFD clock
VCO divide clock
Phase detector output
LD output
Fig. 7 Analog Lock Detect Operation
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4.2 Digital Lock Detect
In digital lock detect, [LD] pin outputs ”Low” when the frequency is set. The output of [LD] pin turns from “Low” to “High”
(which means “locked state”) when a phase error smaller than T is detected for 63 times consecutively. If the phase error
that is larger than T is detected for 63 times consecutively during [LD] pin outputs “High”, the output of [LD] pin turns to
“Low”(which means “unlocked state”).
The accuracy of the phase detect is set by {LDCKSEL[1:0]}.
{LDCKSEL[1:0]} is set to “00”: T = REFIN cycle
(This is not available for the reference dividing ratio ≤ 3.)
{LDCKSEL[1:0]} is set to “01”: T = REFIN cycle × 2 (This is not available for the reference dividing ratio ≤ 5.)
{LDCKSEL[1:0]} is set to “10”: T = REFIN cycle × 3 (This is not available for the reference dividing ratio ≤ 6.)
Since AK1590 is a Delta-Sigma Fractional-N type, a phase error up to 7 times larger than the VCO period frequency may
occur in the phase detector. Therefore {LDCKSEL[1:0]} setting should be large enough to cover the amplitude of the
Delta-Sigma Fractional frequency. However, if the VCO frequency does not satisfy either of the following formula, the
digital lock detect is not available. In such case, the analog lock detect should be used.
{DITH} = D[14] in <Address3> is set to “1” (DITH ON):
VCO frequency > [REFIN] pin input frequency / [{LDCKSEL[1:0]} + 1] × 7
{DITH} = D[14] in <Address3> is set to “0” (DITH OFF):
VCO frequency > [REFIN] pin input frequency / [{LDCKSEL[1:0]} + 1] × 4
Example 1)
When [REFIN] input frequency = 33.6MHz, {DITH} = 1, {LDCKSEL[1:0]} = ”10”;
33.6MHz / (2+1) × 7 = 78.4MHz
As a result, the digital lock detect is not available if the VCO frequency is equivalent to or smaller than
78.4MHz.
Example 2)
When [REFIN] input frequency = 33.6MHz, {DITH} = 0, {LDCKSEL[1:0]} = “01”;
33.6MHz / (1+1) × 4 = 67.2MHz
As a result, the digital lock detect is not available if the VCO frequency is equivalent to or smaller than
67.2MHz.
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Setup example
{DITH} = D[14] in <Address3> is set to “1” (DITH ON):
Digital Lock Detect Available
Digital Lock Detect Unavailable
180MHz
70MHz
12.8MHz
32MHz
{LDCKSEL[1:0]}
“00”
“10”
Calculation
180MHz > 12.8/(0+1) × 7 = 89.6MHz
70MHz < 32/(2+1) × 7 = 74.67MHz
VCO frequency
[REFIN] input
frequency
{DITH} = D[14] in <Address3> is set to “0” (DITH OFF):
Digital Lock Detect Available
Digital Lock Detect Unavailable
180MHz
60MHz
12.8MHz
32MHz
{LDCKSEL[1:0]}
“00”
“01”
Calculation
180MHz > 12.8/(0+1) × 4 = 51.2MHz
60MHz < 32/(1+1) × 4 = 64MHz
VCO frequency
[REFIN] input
frequency
Case: {LDCKSEL} = “00”
Ｔ
Reference clock
PFD clock
VCO divide clock
Phase detector output
Lock detect result
Invalid
Valid
Valid
Valid
Invalid
Invalid
Valid
Fig. 8 Digital Lock Detect Operation
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Unlocked ([LD]=”Low”)
Flag = 0
No
Phase Error < T
Yes
Flag = Flag+1
No
Flag > 63
Yes
Locked ([LD]=”High”)
Fig. 9 Transition Flow Chart: Unlocked State to Locked State
Locked ([LD]=”High”)
Address2 write
Flag = 0
No
Phase Error > T
Yes
Flag = Flag+1
No
Flag > 63
Yes
Unlocked ([LD]=”Low”)
Fig. 10 Transition Flow Chart: Locked State to Unlocked State
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5. Reference Input
The reference input can be set with a dividing number in the range of 4 to 255 using {R[7:0]}, which is a 8-bit address in
<Address3>. A dividing number from 0 to 3 cannot be set.
6. Prescaler and Swallow Counter
The dual modulus prescaler (P/P+1) and the swallow counter are used to provide a large dividing ratio.
The prescaler is set by {PRE[1:0]}, which is a 2-bit address in <Address3>.
When {PRE[1:0]} =”00”, P = 4 is selected and then an integer from 89 to 8191 can be set.
When {PRE[1:0]} =”01”, P = 8 is selected and then an integer from 201 to 16383 can be set.
When {PRE[1:0]} =”10” or “11”, P = 16 is selected and then an integer from 521 to 32767 can be set.
For details of how to calculate an integer, see the section “Frequency Setup” in “8. Block Functional Description”.
7. Operation Mode
AK1590 can be operated in Power Down or Power Save mode as necessary by using the external control pins [PDN1]
and [PDN2].
Power On
See “13. Power-up Sequence”.
Normal Operation
Pin name
Mode
PDN1
PDN2
“Low”
“Low”
Power Down mode
“Low”
“High”
Prohibited
“High”
“Low”
Power Save mode
“High”
“High”
Normal Operation mode
Note 1)
(Note 1 and Note 2)
Registers setting can be acceptable after 50s from [PDN1] is set to “High”. The charge pump is in
Hi-Z state during this period.
Note 2)
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[AK1590]
9. Register Map
Name
Data
Address
Num
0
0
0
1
Int
0
0
1
0
0
0
1
1
Cp_fast
0
1
0
0
GPO
0
1
0
1
Offset
0
1
1
0
Div
D19 to D0
Name
D19 D18 D17 D16 D15 D14
D13
D12
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Address
Num
0
0
NUM
[17]
NUM
[16]
NUM
[15]
NUM
[14]
NUM
[13]
NUM
[12]
NUM
[11]
NUM
[10]
NUM
[9]
NUM
[8]
NUM
[7]
NUM
[6]
NUM
[5]
NUM
[4]
NUM
[3]
NUM
[2]
NUM
[1]
NUM
[0]
0x01
Int
0
0
CP1
[2]
CP1
[1]
CP1
[0]
INT
[14]
INT
[13]
INT
[12]
INT
[11]
INT
[10]
INT
[9]
INT
[8]
INT
[7]
INT
[6]
INT
[5]
INT
[4]
INT
[3]
INT
[2]
INT
[1]
INT
[0]
0x02
DITH
LDCK
SEL[1]
LDCK
SEL[0]
LD
CP
POLA
PRE
[1]
PRE
[0]
R
[7]
R
[6]
R
[5]
R
[4]
R
[3]
R
[2]
R
[1]
R
[0]
0x03
CP2
[1]
CP2
[0]
FAST
[12]
FAST
[11]
FAST
[10]
FAST
[9]
FAST
[8]
FAST
[7]
FAST
[6]
FAST
[5]
FAST
[4]
FAST
[3]
FAST
[2]
FAST
[1]
FAST
[0]
0x04
0
GPO
2
GPO
1
0x05
OFST OFST OFST OFST OFST OFST OFST OFST OFST OFST OFST OFST
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
0x06
Div
Cp_fast
0
0
0
0
CP
HiZ
0
0
0
FAST
EN
CP2
[2]
GPO
0
0
Offset
0
0
Note 1)
0
0
0
0
OFST OFST OFST OFST
[17]
[16]
[15]
[14]
0
0
OFST
[13]
OFST
[12]
0
0
0
0
0
0
0
0
0
Writing into address 0x01 is enabled when writing into address 0x02 is performed. Be sure to write into address
0x01 first and then address 0x02.
Note 2)
The initial register values are not defined just after [PDN1] releases ([PDN1] set to “High”). Therefore, even
after [PDN1] is set to “High”, each bit value remains undefined. In order to set all register values, it is required to
write the data in all addresses of the register.
MS1478-E-02
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[AK1590]
10. Register Functional Description
< Address 1: Num >
D19
D18
D[17:0]
Address
0
0
NUM[17:0]
0001
Note) Writing into address 0x01 is enabled when writing into address 0x02 is performed.
NUM[17:0] : Set the numerator in 2’s complementary representation.
< Address 2: Int >
D19
D18
D[17:15]
D[14:0]
Address
0
0
CP1[2:0]
INT[14:0]
0010
CP1[2:0]: Set the current value for the charge pump in normal operation (Charge Pump 1).
Charge Pump 1 current is determined by the following formula:
CP1_min = 0.57 / Resistance connected to [BIAS] pin
Charge Pump 1 current = CP1_min × ({CP1[2:0]} + 1)
D[17:15]
Charge Pump 1 current [A]
22kΩ
27kΩ
33kΩ
000
25.9
21.1
17.3
001
51.8
42.2
34.5
010
77.7
63.3
51.8
011
103.6
84.4
69.1
100
129.5
100.6
86.4
101
155.5
126.7
103.6
110
181.4
147.8
120.9
111
207.3
168.9
138.2
INT[14:0] : Set the integer.
When {PRE[1:0]} =”00”, P = 4 is selected and then an integer from 89 to 8191 can be set.
When {PRE[1:0]} =”01”, P = 8 is selected and then an integer from 201 to 16383 can be
set.
When {PRE[1:0]} =”10” or “11”, P = 16 is selected and then an integer from 521 to 32767
can be set.
MS1478-E-02
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[AK1590]
< Address 3: Div >
D19
D18
D17
D16
D15
D14
D[13:12]
D11
D10
D[9:8]
D[7:0]
Addres
0
0
0
0
CPHIZ
DITH
LDCKSEL[1:0]
LD
CPPOLA
PRE[1:0]
R[7:0]
s
0011
CPHIZ: Select normal or TRI-STATE for the CP1/CP2 output.
D15
Function
Remarks
0
Charge pumps are activated
Use this setting for normal operation
1
TRI-STATE
Note 1)
Note 1) The charge pump output is put in Hi-Z state.
DITH: Select dithering ON or OFF for a delta-sigma circuit.
D14
Function
Remarks
0
DITH OFF
Low Noise mode
1
DITH ON
Low Spurious mode
It is used to control the turning On or Off for dithering to cancel cyclical noise.
When OFFSET register is used, set DITH=0(OFF).
LDCKSEL[1:0] : Set phase error values for lock detect.
D13
D12
Function
Remarks
0
0
1 cycle of the REFIN clock
0
1
2 cycles of the REFIN clock
1
0
3 cycles of the REFIN clock
1
1
Prohibited
For detailed functional descriptions, see the section “Lock Detect (LD) Signal” in “8. Block Functional
Description”.
LD: Select analog or digital for the lock detect.
D11
Function
0
Digital Lock Detect
1
Analog Lock Detect
Remarks
For detailed functional descriptions, see the section “Lock Detect (LD) Signal” in “8. Block Functional
Description”.
CPPOLA: Select positive or negative output polarity for Charge Pump 1 and Charge Pump 2.
D10
MS1478-E-02
Function
0
Positive
1
Negative
Remarks
21
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[AK1590]
High
VCO frequency
Positive
Negative
Low
Low
High
Charge pump output voltage
Fig. 11 Charge Pump slope Polarity
PRE[1:0] : Select a dividing ratio for the prescaler.
D9
D8
Function
0
0
P=4
0
1
P=8
1
0
P=16
1
1
P=16
Remarks
R[7:0]: Set a dividing ratio for the reference clock.
This can be set in the range from 4 (4 divisions) to 255 (255 divisions). 0 to 3 cannot be set.
D7
D6
D5
D4
D3
D2
D1
D0
Function
Remarks
0
0
0
0
0
0
0
0
0
Prohibited
0
0
0
0
0
0
0
1
1
Prohibited
0
0
0
0
0
0
1
0
2
Prohibited
0
0
0
0
0
0
1
1
3
Prohibited
DATA
MS1478-E-02
1
1
1
1
1
1
0
1
253
1
1
1
1
1
1
1
0
254
1
1
1
1
1
1
1
1
255
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[AK1590]
< Address 4: Cp_fast >
D19
D18
D17
D16
D[15:13]
D[12:0]
Addres
0
0
0
FASTEN
CP2[2:0]
FAST[12:0]
s
0100
FASTEN: Enable or disables the Fast Lockup mode.
D16
Function
Remarks
0
The switchover settings specified in CP2[2:0] and FAST[12:0] are disabled.
1
The switchover settings specified in CP2[2:0] and FAST[12:0] are enabled.
CP2[2:0]: Set the current value for the charge pump for the Fast Lockup mode
(Charge Pump 2).
Charge Pump 2 current is determined by the following formula:
CP2_min = 5.7 / Resistance connected to [BIAS] pin
Charge Pump 2 current = CP2_min × ({CP2[2:0]} + 4) [mA]
Charge Pump 2 current [mA]
D[15:13]
MS1478-E-02
22kΩ
27kΩ
33kΩ
000
1.04
0.84
0.69
001
1.30
1.06
0.86
010
1.55
1.27
1.04
011
1.81
1.48
1.21
100
2.07
1.69
1.38
101
2.33
1.90
1.55
110
2.59
2.11
1.73
111
2.85
2.32
1.90
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[AK1590]
FAST[12:0] : Set the FAST counter value.
A decimal number from 1 to 8191 can be set. This counter value is used to set the time period during
which the charge pump for the Fast Lockup mode is ON.
The charge pump for the Fast Lockup mode is turned OFF after the time period calculated by
“this count value × the reference clock cycle”. 0 cannot be set.
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
Remarks
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Prohibited
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
2
DATA
MS1478-E-02
1
1
1
1
1
1
1
1
1
1
1
0
1
8189
1
1
1
1
1
1
1
1
1
1
1
1
0
8190
1
1
1
1
1
1
1
1
1
1
1
1
1
8191
24
2015/6
[AK1590]
< Address 5: GPO >
D[19:2]
D1
D0
Address
0
GPO2
GPO1
0101
GPO2: Set the state of [GPO2] pin
This value controls the General-Purpose Output pin GPO2.
The voltage applied to PVDD pin determines the “High” output level.
D1
Function
Remarks
0
“Low” output from the GPO2 pin
1
“High” output from the GPO2 pin
GPO1: Set the state of [GPO1] pin
This value controls the General-Purpose Output pin GPO1.
The voltage applied to the PVDD pin determines the “High” output level.
D0
Function
Remarks
0
“Low” output from the GPO1 pin
1
“High” output from the GPO1 pin
< Address 6: Offset >
D19
D18
D[17:0]
Address
0
0
OFST[17:0]
0110
OFST[17:0] : Set the adjustable frequency offset in 2’s complementary representation.
This register designates offset from carrier frequency.
After this register is accessed, {NUM[17:0]} is recalculated and {NUM[17:0]}+{OFST[17:0]} are used in
delta-sigma and N-divider as the numerator. When this register is not used, this register must be
written 00000 (hexadecimal).
When this register is used continuously as below,
{OFST}(0) {OFST}(1) … {OFST}(k-1) {OFST}(k) {OFST}(k+1) …
{NUM} and {OFST} can be set in the below range.
-131072 ≤ |{NUM}+{OFST}| ≤ 131071 (decimal)
|{OFST}(k)- {OFST}(k-1)| ≤ 2000 (decimal)
When this register is used in out of this range, the circuit of delta-sigma modulator may cause
unexpected glitches in VCO control voltage.
When OFFSET register is used, set DITH=0(OFF).
MS1478-E-02
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[AK1590]
OFFSET register must be written at the lower speed than calculated frequency by
“1/3.5RF Frequency/(INT+7)”. If the writing speed is faster than this, the setting is invalid.
Setting examples
Example 1)
The frequency offset is positive; when the frequency offset is 100Hz and FPFD is 1MHz.
18
Frequency offset = 100Hz / (1MHz/2 ) = 26.2
It is round off to 26 (decimal) = 1A (hexadecimal) = 11010 (binary)
Example 2)
The frequency offset is negative; when the frequency offset is -100Hz and FPFD is 1MHz.
18
Frequency offset = -100Hz / (1MHz/2 ) = -26.2
It is round off to -26 (decimal), which is reduced from 2
18
to be converted into binary for 2’s
complementary expression.
2
Example 3)
18
– 26 = 262118 (decimal) = 3FFE6 (hexadecimal) = 11 1111 1111 1110 0110 (binary)
Calculation example : |{NUM}+{OFST}|
When the frequency offset is 1500Hz, FPFD is 4.8MHz, and VCO frequency is 467.52MHz.
Integer = 467.52MHz / 4.8MHz = 97.4
It is rounded off to 97 (decimal) = 61 (hexadecimal) = 110 0001 (binary)
18
Numerator = (467.52MHz - 97 × 4.8MHz) / (4.8MHz / 2 ) = 104857.6
It is rounded off to 104858 (decimal) = 1999A (hexadecimal) = 1 1001 1001 1010 (binary)
18
Frequency offset = 1500Hz / (4.8MHz/2 ) = 81.92
It is round off to 82 (decimal) = 52 (hexadecimal) = 101 0010 (binary)
In this case, {NUM}+{OFST} = 104858+82=104940 (decimal)
Example 4)
Calculation example : |{OFST}(k)- {OFST}(k-1)|
When FPFD is 1MHz. The frequency offset is set to 2000Hz at the 1st time. Then the frequency offset
is set to -2000Hz at the 2nd time.
18
Frequency offset(1st time) = 2000Hz / (1MHz/2 ) = 524.288
It is round off to 524 (decimal) = 20C (hexadecimal) = 10 0000 1100 (binary)
18
Frequency offset(2nd time) = -2000Hz / (1MHz/2 ) = -524.288
It is round off to -524 (decimal), which is reduced from 2
18
to be converted into binary for
2’s complementary expression.
2
18
– 524 = 261620 (decimal) = 3FDF4 (hexadecimal) = 11 1111 1101 1111 0100 (binary)
In this case, |{OFST}(k)- {OFST}(k-1)| = -524 – 524 = -1048 (decimal)
MS1478-E-02
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[AK1590]
11. IC Interface Schematic
No.
Name
I/O
R0(Ω)
4
LE
I
300
5
DATA
I
300
6
CLK
I
300
8
PDN2
I
300
9
PDN1
I
300
2
TEST3
I
300
3
TEST1
I
300
11
TEST2
I
300
Function
Cur(A)
Digital input pins
R0
Digital input pins Pull-Down
R0
100k
7
LD
O
12
GPO1
O
13
GPO2
O
10
REFIN
I
Digital output pin
300
Analog input pin
R0
15
VREF
IO
300
19
BIAS
IO
300
22
CPZ
IO
300
MS1478-E-02
Analog I/O pin
R0
27
2015/6
[AK1590]
No.
Name
I/O
23
SWIN
I
Analog input pin
21
CP
O
Analog output pin
16
RFINN
I
40k
20
17
RFINP
I
40k
20
R0(Ω)
Function
Cur(A)
Analog input pin (RF signal input)
R0
MS1478-E-02
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[AK1590]
12. Recommended Connection Schematic for Off-Chip Components
1. PVDD, CPVDD
LSI
PVDD
0.01F
100pF
10F
CPVDD
0.01F
100pF
10F
2. VREF
LSI
VREF
220nF±10%
VREF2
3. TEST [1,2,3]
LSI
TEST [1,2,3]
MS1478-E-02
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[AK1590]
4. REFIN
LSI
REFIN
100pF±10%
5. RFINP, RFINN
LSI
VCO Output
RFINP
51Ω
100pF±10%
RFINN
100pF±10%
6. BIAS
LSI
BIAS
22kΩ~33kΩ
MS1478-E-02
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[AK1590]
13. Power-up Sequence
PDN1
50s
The register can be written
ON
On-chip LDO
OFF
Internal register values are set
Write to the register
PDN2
CP
Hi-Z
Output
Fig. 12 Recommended Power-up Sequence
Note 1)
The initial register values are not defined. Therefore, even after [PDN1] is set to “High”, each bit
value remains undefined. In order to set all register values, it is required to write the data in all
addresses of the register.
Note 2)
It is prohibited to do power up and [PDN2] release at the same time. It is mandatory to power up first,
then set [PDN2] to “High”. If they are set simultaneously, initial operation might be unstable.
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[AK1590]
14. Typical Evaluation Board Schematic
RFOUT
AK1590
Loop Filter
100pF
REFIN
CP
18
100pF
R3
VCO
C1
R2'
R2
C3
18
18
VREF
220nF
SWIN
C2
CPZ
BIAS
27k
100pF
RFINP
51
RFINN
100pF
Fig. 13 Typical Evaluation Board Schematic
The input voltage from [CPZ] pin is used in the internal circuit. [CPZ] pin must not be open even when the Fast Lockup
feature is unused. For the output destination from [CPZ] pin, see “Fig.5 Loop Filter Schematic”. [SWIN] pin could be open
when the Fast Lockup feature is not used.
R2 and R2’ are connected in parallel with internal switch in Fast Lockup. These R2 and R2’ parallel resistance value is
required for calculating loop bandwidth and phase margin in Fast Lockup. The on-resistance value of the internal switch is
150Ω for reference.
It is recommended to connect the exposed pad (the center of the back of the package) to ground, although it will not make
any impact on the electrical characteristics even if the pad is open. Moreover, all test pins should be connected to ground.
MS1478-E-02
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[AK1590]
CPVSS
CPVDD
PVDD
PVSS
VREF
DVSS
15. Block Diagram by Power Supply
LDO
BIAS
R COUNTER
8bit
REFIN
CHARGE PUMP 1
CP
PHASE
FREQENCY
DETECTOR
CLK
CHARGE PUMP 2
(For Fast Lock Up)
REGISTER
24bit
DATA
LE
+
NUM
CPZ
FAST
COUNTER
13bit
OFFSET
N DIVIDER
ΔΣ
18bit
LOCK DETECT
SWIN
PULSE
SWALLOW
COUNTER
SUM
INT
GPO2
GPO1
CPVDD
PDN2
PVDD
PDN1
-
TEST3
RFINN
LD
PRESCALER
4/5, 8/9,16/17
TEST2
+
TEST1
RFINP
Fig. 14 Block Diagram by Power Supply
MS1478-E-02
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[AK1590]
16. Outer Dimensions
4.00±0.07
2.40
18
12
19
7
24
B
1
6
C0.30
2.00
0.05 M S
0.12~0.18
0.17~0.27
0.70
0.00~0.05
0.05 S
0.05MAX
Part A
A B
0.22±0.05
0.75MAX
S
0.5
0.40±0.07
2.40
A
2.00
4.00±0.07
13
Detailed chart in part A
Fig. 15 Outer Dimensions
Note) It is recommended to connect the exposed pad (the center of the back of the package) to ground, although
it will not make any impact on the electrical characteristics eve if the pad is open.
MS1478-E-02
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[AK1590]
17. Marking
(a) Style
:
QFN
(b) Number of pins
:
24
(c) 1 pin marking:
:
○
(d) Product number
:
1590
(e) Date code
:
YWWL (4 digits)
Y:
Lower 1 digit of calendar year (Year 2012 → 2, 2013 → 3 ...)
WW:
Week
L:
Lot identification, given to each product lot which is made in a week
LOT ID is given in alphabetical order (A, B, C…).
1590(d)
YWWL (e)
(c)
Fig. 16 Marking
MS1478-E-02
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2015/6
[AK1590]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy
or completeness of the information contained in this document nor grants any license to any intellectual
property rights or any other rights of AKM or any third party with respect to the information in this document.
You are fully responsible for use of such information contained in this document in your product design or
applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD
PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR
APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life,
bodily injury, serious property damage or serious public impact, including but not limited to, equipment used
in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for
automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control
combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and
equipment used in finance-related fields. Do not use Product for the above use unless specifically agreed by
AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or
corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in
this document for any military purposes, including without limitation, for the design, development, use,
stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products
(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not
be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with
applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or
extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
MS1478-E-02
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2015/6
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IDD:2.2mA
AK1543
400MHz~1.3GHz Low Power Fractional-N Synthesizer
IDD:5.1mA
AK1544
400MHz~1.3GHz Low Power Integer-N Synthesizer
IDD:2.8mA
AK1590
60MHz~1GHz Fractional-N Synthesizer
IDD:2.5mA
AK1545
0.5GHz~3.5GHz Integer-N Synthesizer
16-TSSOP
AK1546
0.5GHz~3GHz Low Phase Noise Integer-N Synthesizer
Normalized C/N:-226dBc/Hz
AK1547
0.5GHz~4GHz Integer-N Synthesizer
5V Supply
AK1548
1GHz~8GHz Low Phase Noise Integer-N Synthesizer
Normalized C/N:-226dBc/Hz
100~300MHz Analog Signal Control IF VGA w/ RSSI
Dynamic Range:30dB
IFVGA
AK1291
integrated VCO
AK1572
690MHz~4GHz Down Conversion Mixer with Frac.-N PLL and VCO
IIP3:24dBm,
-111dBc/Hz@100kHz
AK1575
690MHz~4GHz Up Conversion Mixer with Frac.-N PLL and VCO
IIP3:24dBm,
-111dBc/Hz@100kHz
IF Reciever (2nd Mixer + IF BPF + FM Detector)
AK2364
Built-in programmable AGC+BPF, FM detector IC
IFBPF:10kHz ~ 4.5kHz
AK2365A
Built-in programmable AGC+BPF, IFIC
IFBPF:7.5kHz ~ 2kHz
Analog BB for PMR/LMR
AK2345C
AK2360/
AK2360A
CTCSS Filter, Encoder, Decoder
24-VSOP
Inverted frequency(3.376kHz/3.020kHz) scrambler
8-SON
AK2363
MSK Modem/DTMF Receiver
24-QFN
AK2346B
0.3-2.55/3.0kHz Analog audio filter,
Emphasis, Compandor, scrambler, MSK Modem
24-VSOP
AK2346A
24-QFN
0.3-2.55/3.0kHz Analog audio filter
Emphasis, Compandor, scrambler, CTCSS filter
24-VSOP
AK2330
8-bit 8ch Electronic Volume
VREF can be selected for each
channel
AK2331
8-bit 4ch Electronic Volume
VREF can be selected for each
channel
AK2347B
Function IC
Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without
notice. When you consider any use or application of AKM product stipulated in this document, please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
2015/6