High Speed Digital Design & Verification Seminar Key challenges in the design and analysis of high speed digital links Chip-to-chip Interconnect Goes Serial, Gets Fast and needs to co-exist A look at Apple Macbook pro Increased Density High-speed everywhere Pressure to Reduce cost USB 3.0 HDMI DVI DP PCIe SATA DDR3 4.8 Gb/s 5 Gb/s 8 Gb/s 8.6 Gb/s 5 Gb/s 3 Gb/s 0.8-2.133 Gb/s Signal Integrity Engineering Challenges Now: Multi-gigabit/s Digital World Hits Microwave Effect “Wall” No time for reflections to die down between pulses Need classic microwave techniques to prevent eye closure and BER Chip #1 Interconnect impedance=Zo/(Fr ), standardize on ~50 Output impedance Input impedance ~50 ~50 Page 3 Chip #2 Four Signal Integrity problems and their causes 1. Poor signal quality of one net: reflections and distortions from impedance discontinuities in the signal or return path 2. Crosstalk between multiple nets: mutual C and mutual L coupling Aggressor Victim 3. Rail collapse (Ground Bounce) in the power distribution system: voltage drops across impedance in the power/ground network 4. Jitter from causes listed above and variety of other sources including clock distribution, data dependent effects, and EMI “Ground” A Typical Design Driver Trace PCB Trace Vias Connectors Die Package Card Receiver Backplane Die Package Card What RF Engineers Know: • • • • Everything in the circuit has RF performance Transition = Impedance Change/Discontinuity Need to measure and characterize all components No amount of signal conditioning can overcome a poor interconnect Impedance problems are everywhere Connectors Backplanes PC Boards IC Packages Cables High-Speed PCB Challenges 1. Parasitic capacitance in through hole 2. Localized crosstalk 3. Localized changes in conductor width 4. Localized changes in conductor spacing 5. Reflections due to via stub 6. Non-uniform dielectric 7. Dielectric constant variation 8. Surface treatment thickness non-uniformity 9. Localized changes in foil thickness Impact of Bandwidth on FR4 FR4 is common, low cost and easy to manufacture BUT it has problems: • Reflections at high speeds • Dispersion • Insertion Loss • Frequency Response • Jitter • Closed eyes 3.125 Gb/s 6.25 Gb/s 12.5 Gb/s Typical High Speed Digital PHY Time or Frequency domain? Digital engineer toolbox • Time domain • Oscilloscopes/TDR RF/uW engineer toolbox • Frequency domain • Network Analyzers High speed digital challenges summary Design Analysis/measurement Very high signal rates • • • • • Signals must be differential Crosstalk & Coupling Controlling impedance FR4 Bandwidth limitations Connectors, Via transitions etc. • • Noise & Jitter Probing a key issue • Loading • Probe location Microwave effects • Simulation is essential • Interconnect modeling • Power/GND plane resonances • Characterize I/O buffers Need models and accuracy “Know-how” • • Time or frequency domain? Need high quality probes and fixtures • Measurement requirements get tighter • • Standards evolve rapidly Leveraging existing designs gets harder Agilent Workflow for HSD/SI • Channel Analysis & Optimization in Time and Freq. Domains • Fast, Robust & Accurate Convolution Algorithms. • Impedance Profile Analysis TDR/TDT • Fixturing Deembedding • Impedance Optimization to Minimize Reflections • HighZ Probes • Effective PCB PreLayout Design • Accurate S-parameters Embedding/DeEmbedding • Full range of EM extraction tool • Crosstalk’s impact on Eye Diagram • Power Delivery Network impedance extraction • Jitter Breakdown TJ/RJ/DJ/BUJ/PJ/ISI • Near field and current visualization at physical level • Integration of Deemphasis and Equalization algorithms • Libraries for HSD PHY Compliance • Receiver emulation Equalization, CDR • RootCause Analysis of EyeMask Collapse • Jitter sources Analysis through Jitter FFT and Breakdown. • Agilent member of Body standards: PCI Sig, USB Org, SATA IO, HDMI, Displayport, Thunderbolt… • First Silicon ready TX/RX Compliance • Accurate RX Jitter Tolerance Caracterisation • Complete Protocol Validation • Custom Compliance Test through User Defined App. EEsof High Speed Digital Design Flow Maintaining Signal Integrity from Concept to Implementation Chip Design IC Model Generation (SystemVue) High Speed Digital Design: Package and PCB Pre-Layout Pre-Layout Post-Layout Post-Layout w/Channel Sim Design & Analysis w/Transient Verify & Refine Access Critical Nets & PDNs EM Models to Verify & Refine ADS Constraint Mgmt. Layout Design Rules to Constraint Editor Constraint-Based Board Tool Layout Methodology Validation & Refinement T&M Equipment •Analysis •Debug •Compliance Physical Design •Design & Simulation •Analysis & Optimization •Verification