TI SN65HVD3088ED

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DGK
D
P
SLLS562C − MARCH 2003 − REVISED − JUNE 2004
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FEATURES
DESCRIPTION
D Available in Small MSOP-8 Package
D Meets or Exceeds the Requirements of the
These devices are half-duplex transceivers designed for
RS-485 data bus networks. Powered by a 5-V supply, they
are fully compliant with TIA/EIA-485A standard. With
controlled transition times, these devices are suitable for
transmitting data over long twisted-pair cables.
SN65HVD3082E and SN75HVD3082E devices are
optimized for signaling rates up to 200 kbps.
SN65HVD3085E is suitable for data transmission up to 1
Mbps, whereas SN65HVD3088E is suitable for
applications requiring signaling rates up to 20 Mbps.
These devices are designed to operate with very low
supply current, typically 0.3 mA, exclusive of the load.
When in the inactive shutdown mode, the supply current
drops to a few nanoamps, making these devices ideal for
power-sensitive applications.
TIA/EIA−485A Standard
D Low Quiescent Power
− 0.3 mA Active Mode
− 1 nA Shutdown Mode
D
D
D
D
1/8 Unit Load—Up to 256 Nodes on a Bus
Bus-Pin ESD Protection Up to 15 kV
Industry-Standard SN75176 Footprint
Failsafe Receiver
(Bus Open, Bus Shorted, Bus Idle)
The wide common-mode range and high ESD protection
levels of these devices make them suitable for demanding
applications such as energy meter networks, electrical
inverters, status/command signals across telecom racks,
cabled chassis interconnects, and industrial automation
networks where noise tolerance is essential. These
devices match the industry-standard footprint of SN75176.
Power-on reset circuits keep the outputs in a highimpedance state until the supply voltage has stabilized. A
thermal shutdown function protects the device from
damage due to system fault conditions. The
SN75HVD3082E is characterized for operation from 0°C
to 70°C and SN65HVD308xE are characterized for
operation from −40°C to 85°C air temperature.
APPLICATIONS
D
D
D
D
D
D
D
Energy Meter Networks
Motor Control
Power Inverters
Industrial Automation
Building Automation Networks
Battery-Powered Applications
Telecommunications Equipment
ORDERING INFORMATION
PACKAGE TYPE
D(1)
TA
SIGNALING RATE
(Mbps)
0°C to 70°C
0.2
SN75HVD3082EP
Marked as 75HVD3082
SN75HVD3082ED
Marked as VN3082
SN75HVD3082EDGK
Marked as NWM
0.2
SN65HVD3082EP
Marked as 65HVD3082
SN65HVD3082ED
Marked as VP3082
SN65HVD3082EDGK
Marked as NWN
1
SN65HVD3085ED
Marked as VP3085
SN65HVD3085EDGK
Marked as NWK
20
SN65HVD3088ED
Marked as VP3088
SN65HVD3088EDGK
Marked as NWH
−40°C to 85°C
P
DGK(2)
(1) The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD3082EDR).
(2) The DGK package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD3082EDGKR).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright  2004, Texas Instruments Incorporated
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SLLS562C − MARCH 2003 − REVISED − JUNE 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) (2)
UNITS
Supply voltage range, VCC
−0.5 V to 7 V
Voltage range at A or B
−9 V to 14 V
Voltage range at any logic pin
−0.3 V to VCC + 0.3 V
Receiver output current
−24 mA to 24 mA
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 13)
−50 V to 50 V
Junction temperature, TJ
170°C
Continuous total power dissipation
Refer to Package Dissipation Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
PACKAGE
JEDEC BOARD MODEL
D
Low k(1)
High k(2)
P
Low k(1)
Low k(1)
DGK
High k(2)
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
507 mW
DERATING FACTOR(3)
ABOVE TA = 25°C
4.82 mW/°C
289 mW
217 mW
824 mW
7.85 mW/°C
471 mW
353 mW
686 mW
6.53 mW/°C
392 mW
294 mW
394 mW
3.76 mW/°C
255 mW
169 mW
583 mW
5.55 mW/°C
333 mW
250 mW
TA <25°C
POWER RATING
(1) In accordance with the low-k thermal metric definitions of EIA/JESD51-3
(2) In accordance with the high-k thermal metric definitions of EIA/JESDS1-7
(3) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
2
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SLLS562C − MARCH 2003 − REVISED − JUNE 2004
RECOMMENDED OPERATING CONDITIONS(1)
MIN
Supply voltage, VCC
4.5
Input voltage at any bus terminal (separately or common mode), VI
TYP
MAX
UNIT
5.5
V
−7
12
V
High-level input voltage (D, DE, or RE inputs), VIH
2
V
Low-level input voltage (D, DE, or RE inputs), VIL
0
VCC
0.8
−12
12
V
−60
60
−8
8
Differential input voltage, VID
Driver
Output current, IO
Receiver
Differential load resistance, RL
54
Signaling rate, 1/tUI
0.2
SN65HVD3085E
1
SN65HVD3088E
20
SN65HVD3082E, SN65HVD3085E, SN65HVD3088E
Operating free−air temperature, TA
mA
Ω
60
SN65HVD3082E, SN75HVD3082E
V
−40
85
0
70
SN75HVD3082E
Junction temperature, TJ(2)
−40
130
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
(2) See thermal characteristics table for information on maintenance of this specification for the DGK package.
Mbps
°C
°C
SUPPLY CURRENT
over recommended operating conditions unless otherwise noted
PARAMETER
ICC
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
Driver and receiver enabled
D at VCC or open,
DE at VCC, RE at 0 V, No load
425
900
µA
Driver enabled, receiver disabled
D at VCC or open,
DE at VCC, RE at VCC, No load
330
600
µA
Receiver enabled, driver disabled
D at VCC or open,
DE at 0 V, RE at 0 V, No load
300
600
µA
0.001
2
µA
MIN TYP(1)
MAX
Driver and receiver disabled
D at VCC or open,
(1) All typical values are at 25°C and with a 5-V supply.
DE at 0 V, RE at VCC
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER
Human body model
Human body model(2)
TEST CONDITIONS
Bus terminals and GND
All pins
Charged-device-model(3)
All pins
(1) All typical values at 25°C
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.
UNIT
±15
kV
±4
kV
±1
kV
3
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SLLS562C − MARCH 2003 − REVISED − JUNE 2004
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
IO = 0, No load
RL = 54 Ω, See Figure 1
MIN
TYP(1)
3
4.3
1.5
2.3
MAX
VOD
Differential output voltage
∆VOD
VOC(SS)
Change in magnitude of differential output voltage
∆VOC(SS)
VOC(PP)
Change in steady-state common-mode output voltage
IOZ
II
High-impedance output current
See receiver input currents
Input current
D, DE
−100
100
−7 V ≤ VO ≤ 12 V, See Figure 7
−250
250
RL = 100 Ω
VTEST = −7 V to 12 V, See Figure 2
See Figure 1 and Figure 2
Steady-state common-mode output voltage
See Figure 3
V
2
1.5
−0.2
0
0.2
1
2.6
3
−0.1
0
0.1
See Figure 3
IOS
Short-circuit output current
(1) All typical values are at 25°C and with a 5V-supply.
UNIT
500
V
V
mV
µA
A
mA
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
tPLH
tPHL
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
tr
tf
Differential output signal rise time
Differential output signal fall time
tsk(p)
tPZH
tPZL
tPHZ
tPLZ
tPZH(SHDN)
tPZL(SHDN)
4
Pulse skew ( |tPHL - tPLH| )
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-impedance-to-low−level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output
Propagation delay time, shutdown-to-high-level output
Propagation delay time, shutdown-to-low-level output
TEST CONDITIONS
MIN
TYP
MAX
RL = 54 Ω,
CL = 50 pF,
See Figure 4
HVD3082E
700
1300
HVD3085E
150
500
HVD3088E
12
20
RL = 54 Ω,
CL = 50 pF,
See Figure 4
HVD3082E
900
1500
HVD3085E
200
300
HVD3088E
7
15
RL = 54 Ω,
CL = 50 pF,
See Figure 4
HVD3082E
20
200
HVD3085E
5
50
HVD3088E
1.4
5
RL = 110 Ω,,
RE at 0 V,
See Figure 5
and Figure 6
HVD3082E
2500
7000
HVD3085E
1000
2500
HVD3088E
13
30
RL = 110 Ω,,
RE at 0 V,
See Figure 5
and Figure 6
HVD3082E
80
200
HVD3085E
60
100
500
HVD3088E
12
30
RL = 110 Ω, RE HVD3082E
HVD3085E
at VCC,
See Figure 5
HVD3088E
3500
7000
2500
4500
1600
2600
UNIT
ns
ns
ns
ns
ns
ns
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SLLS562C − MARCH 2003 − REVISED − JUNE 2004
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
VIT+
VIT−
Positive-going input threshold voltage
Vhys
VOH
Hysteresis voltage (VIT+ − VIT−)
VOL
IOZ
Low-level output voltage
Negative-going input threshold voltage
High-level output voltage
High-impedance-state output current
TEST CONDITIONS
IO = −8 mA
IO = 8 mA
Bus input current
IIH
IIL
High-level input current (RE)
Low-level input current (RE)
Cdiff
Differential input capacitance
(1) All typical values are at 25°C and with a 5-V supply.
TYP(1)
MAX
−85
−200
VID = 200 mV, IOH = −8 mA, See Figure 8
VID = −200 mV, IOH = 8 mA, See Figure 8
−10
VIL = 0.8 V
VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
mV
mV
30
mV
4.6
V
0.15
0.4
−1
VIH = −7 V, VCC = 0
VIH = 2 V
UNIT
−115
4
VO = 0 to VCC, RE= VCC
VIH = 12 V, VCC = 5 V
VIH = 12 V, VCC = 0
VIH = −7 V, VCC = 5 V
II
MIN
V
µA
1
0.04
0.1
0.06
0.125
mA
−0.1
−0.04
−0.05
−0.03
−60
−30
µA
−60
−30
µA
7
pF
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
tPLH
TEST CONDITIONS
HVD3082E
HVD3085E
Propagation delay time, low-to-high-level output
MIN
TYP
75
HVD3088E
tPHL
tsk(p)
Propagation delay time, high-to-low-level output
RL = 54 Ω,
CL = 15 pF,
See Figure 9
HVD3082E
HVD3085E
79
Output signal rise time
tPZH
Output enable time to high level
Output signal fall time
VID = −1.5 V to 1.5 V,
CL = 15 pF, See Figure 9
HVD3082E
HVD3085E
4
tPHZ
Output enable time to low level
Output enable time from high level
CL = 15 pF,
DE at 3 V,
See Figure 10
and Figure 11
HVD3082E
HVD3085E
Output enable time from low level
HVD3082E
HVD3085E
CL = 15 pF, DE at 0 V,
See Figure 12
ns
3
ns
3
ns
5
50
ns
30
10
50
ns
30
5
50
ns
30
8
HVD3088E
tPZH(SHDN) Propagation delay time, shutdown-to-high-level output
tPZL(SHDN) Propagation delay time, shutdown-to-low-level output
30
1.8
HVD3088E
tPLZ
ns
1.5
HVD3088E
HVD3082E
HVD3085E
200
10
HVD3088E
tPZL
ns
100
HVD3088E
tr
tf
200
UNIT
100
HVD3088E
HVD3082E
HVD3085E
Pulse skew ( |tPHL − tPLH| )
MAX
50
ns
30
1600
3500
ns
1700
3500
ns
5
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SLLS562C − MARCH 2003 − REVISED − JUNE 2004
PARAMETER MEASUREMENT INFORMATION
NOTE:Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise and
fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. ZO = 50 Ω (unless otherwise specified).
A IOA
II
0 V or 3 V
27 Ω
VOD
D
50 pF
27 Ω
B IOB
VOC
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 Ω
IOA
VOD
0 V or 3 V
60 Ω
375 Ω
IOB
VTEST = −7 V to 12 V
VTEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
27 Ω
A
VA
D
Signal
Generator
50 Ω
B
27 Ω
≈3.25 V
VB
50 pF
≈1.75 V
∆VOC(SS)
VOC(PP)
VOC
VOC
Figure 3. Driver VOC Test Circuit and Waveforms
3V
INPUT
RL = 54 Ω
Signal
Generator
VOD
1.5 V
10%
VOD(L)
0V
OUTPUT
tr
Figure 4. Driver Switching Test Circuit and Waveforms
6
90%
0V
tPHL
VOD(H)
tPLH
CL = 50 pF
50 Ω
1.5 V
tf
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SLLS562C − MARCH 2003 − REVISED − JUNE 2004
A
S1
D
0 V or 3 V
3 V if Testing A Output
0 V if Testing B Output
DE
Signal
Generator
3V
Output
B
1.5 V
DE
CL = 50 pF
RL = 110 Ω
1.5 V
0.5 V
tPZH
0V
VOH
Output
50 Ω
2.5 V
VOff 0
tPHZ
Figure 5. Driver Enable/Disable Test Circuit and Waveforms, High Output
5V
A
D
0 V or 3 V
0 V if Testing A Output
3 V if Testing B Output
DE
Signal
Generator
RL = 110 Ω
S1
3V
Output
B
1.5 V
DE
1.5 V
0V
CL = 50 pF
tPZL
tPLZ
Output
50 Ω
5V
2.5 V
VOL
0.5 V
Figure 6. Driver Enable/Disable Test Circuit and Waveforms, Low Output
IOS
IO
VO
VID
Voltage
Source
VO
Figure 7. Driver Short-Circuit Test
Signal
Generator
Figure 8. Receiver Parameter Definitions
50 Ω
Input B
VID
A
B
Signal
Generator
50 Ω
R
CL = 15 pF
IO
VO
1.5 V
50%
Input A
tPLH
Output
90%
1.5 V
tr
0V
tPHL
VOH
10% V
OL
tf
Figure 9. Receiver Switching Test Circuit and Waveforms
7
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SLLS562C − MARCH 2003 − REVISED − JUNE 2004
VCC
VCC
D
DE
A
54 Ω
B
3V
1 kΩ
R
0V
1.5 V
0V
CL = 15 pF
RE
Signal
Generator
RE
tPZH
tPHZ
50 Ω
1.5 V
R
VOH
VOH −0.5 V
GND
Figure 10. Receiver Enable/Disable Test Circuit and Waveforms, Data Output High
0V
VCC
D
DE
A
54 Ω
B
3V
1 kΩ
R
RE
5V
1.5 V
0V
CL = 15 pF
RE
tPZL
Signal
Generator
tPLZ
VCC
50 Ω
R
1.5 V
VOL +0.5 V
VOL
Figure 11. Receiver Enable/Disable Test Circuit and Waveforms, Data Output Low
VCC
Switch Down for V(A) = 1.5 V,
Switch Up for V(A) = −1.5 V
A
1.5 V or
−1.5 V
R
B
3V
1 kΩ
CL = 15 pF
RE
Signal
Generator
50 Ω
RE
1.5 V
0V
tPZH(SHDN)
tPZL(SHDN)
5V
R
VOH
1.5 V
0V
Figure 12. Receiver Enable From Shutdown Test Circuit and Waveforms
8
VOL
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VTEST
100 Ω
0V
Pulse Generator,
15 µs Duration,
1% Duty Cycle
15 µs
1.5 ms
−VTEST
Figure 13. Test Circuit and Waveforms, Transient Over-Voltage Test
DEVICE INFORMATION
PIN ASSIGNMENTS
LOGIC DIAGRAM (POSITIVE LOGIC)
D, P OR DGK PACKAGE
(TOP VIEW)
D
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
4
3
DE
2
RE
6
R 1
7
A
B
FUNCTION TABLE
DRIVER
RECEIVER
OUTPUTS
INPUT
D
ENABLE
DE
A
DIFFERENTIAL INPUTS
VID = VA – VB
ENABLE
RE
OUTPUT
R
H
H
H
L
L
H
L
VID ≤ −0.2 V
−0.2 V < VID < −0.01 V
L
L
H
L
X
L
Z
?
Z
−0.01 V ≤ VID
L
H
Open
H
H
X
Open
Z
L
X
H
Z
Z
Open circuit
L
H
Short circuit
L
H
X
Open
Z
B
NOTE: H= high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
9
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Input
DE Input
VCC
Input
200 kΩ
500 VCC
Input
9V
500 200 kΩ
9V
A Input
B Input
VCC
16 V
VCC
16 V
36 kΩ
180 k Ω
36 kΩ
180 kΩ
Input
Input
16 V
36 kΩ
16 V
36 kΩ
A and B Outputs
R Outputs
VCC
VCC
16 V
5Ω
Output
16 V
10
Output
9V
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DGK Package
THERMAL CHARACTERISTICS
PARAMETER
ΘJA
Junction-to-ambient thermal resistance(1)
ΘJB
ΘJC
Junction-to-board thermal resistance
P(AVG)
Average power dissipation
P(AVG)
Average power dissipation
P(AVG)
Average power dissipation
TA
Ambient air temperature
TEST CONDITIONS
Low-k(2) board, no air flow
High-k(3) board, no air flow
MIN
TYP
MAX
266
°C/W
180
High-k(3) board, no air flow
108
Junction-to-case thermal resistance
°C/W
66
RL = 54 Ω, Input to D is a 200 kbps
50% duty cycle square wave
Vcc at 5.5 V, TJ = 130°C
RL = 54 Ω, Input to D is a 1 Mbps
50% duty cycle square wave
Vcc at 5.5 V, TJ = 130°C
RL = 54 Ω, Input to D is a 20 Mbps
50% duty cycle square wave
Vcc at 5.5 V, TJ = 130°C
UNIT
HVD3082E
203
mW
HVD3085E
205
mW
HVD3088E
276
mW
High k board model
−40
93
Low k board model
−40
75
°C
TSD
Thermal shut-down junction temperature
165
°C
(1) See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.
(2) JESD51-3 Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
(3) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
11
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SLLS562C − MARCH 2003 − REVISED − JUNE 2004
TYPICAL CHARACTERISTICS
SN65HVD3082E
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
RMS SUPPLY CURRENT
vs
SIGNALING RATE
80
10
No Load,
VCC = 5 V
TA = 25°C
50% Square wave input
I CC − Supply Current − mA
I I − Input Bias Current − µ A
60
40
VCC = 0 V
20
VCC = 5 V
0
−20
Driver and Receiver
1
Receiver Only
−40
−60
−8
−6
−4
−2 0
2
4
6
VI − Bus Input Voltage − V
8
10
0.1
12
1
10
Signaling Rate − kbps
Figure 14
Figure 15
SN65HVD3085E
SN65HVD3088E
RMS SUPPLY CURRENT
vs
SIGNALING RATE
RMS SUPPLY CURRENT
vs
SIGNALING RATE
100
100
No Load,
VCC = 5 V
TA = 25°C
50% Square wave input
I CC − Supply Current − mA
I CC − Supply Current − mA
100
10
Driver and Receiver
1
No Load,
VCC = 5 V
TA = 25°C
50% Square wave input
10
Driver and Receiver
1
Receiver Only
Receiver Only
0.1
1
10
100
Signaling Rate − kbps
Figure 16
12
1000
0.1
0.001
0.010
0.100
1
Signaling Rate − Mbps
Figure 17
10
100
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TYPICAL CHARACTERISTICS
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
RECEIVER OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
5
5
VOD − Differential Output Voltage − V
4.5
4
4.5
RL = 120Ω
VO − Receiver Output Voltage − V
TA = 25°C
VCC = 5 V
3.5
3
RL = 60Ω
2.5
2
1.5
1
4
TA = 25°C
VCC = 5 V
VIC = 0.75 V
3.5
3
2.5
2
1.5
1
0.5
0.5
0
0
10
20
30
40
IO − Differential Output Current − mA
Figure 18
50
0
−200 −180 −160 −140 −120 −100 −80 −60 −40 −20
VID − Differential Input Voltage − V
0
Figure 19
13
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SLLS562C − MARCH 2003 − REVISED − JUNE 2004
APPLICATION INFORMATION
RT
RT
NOTE: The line should be terminated at both ends with its characteristic impedance (RT = ZO).
Stub lengths off the main line should be kept as short as possible.
Figure 20. Typical Application Circuit
POWER USAGE IN AN RS-485 TRANSCEIVER
Power consumption is a concern in many applications. Power supply current is delivered to the bus load as well as to the
transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must drive consists of all of the
receiving nodes, plus the termination resistors at each end of the bus.
The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-A standard
defines a unit load as allowing up to 1 mA. With up to 32 unit loads allowed on the bus, the total current supplied to all
receivers can be as high as 32 mA. The HVD308xE is rated as a 1/8 unit load device. As shown in Figure 14, the bus input
current is less than 1/8 mA, allowing up to 256 nodes on a single bus.
The current in the termination resistors depends on the differential bus voltage. The standard requires active drivers to
produce at least 1.5 V of differential signal. For a bus terminated with one standard 120-Ω resistor at each end, this sums
to 25 mA differential output current whenever the bus is active. Typically the HVD308xE can drive more than 25 mA to a
60 Ω load, resulting in a differential output voltage higher than the minimum required by the standard. (See Figure 16.)
Overall, the total load current can be 60 mA to a loaded RS-485 bus. This is in addition to the current required by the
transceiver itself; the HVD308xE circuitry requires only about 0.4 mA with both driver and receiver enabled, and only
0.3 mA with either the driver enabled or with the receiver enabled. In low-power shutdown mode, neither the driver nor
receiver is active, and the supply current is very low.
Supply current increases with signaling rate primarily due to the totum pole outputs of the driver (see Figure 15). When
these outputs change state, there is a moment when both the high-side and low-side output transistors are conducting and
this creates a short spike in the supply current. As the frequency of state changes increases, more power is used.
LOW-POWER SHUTDOWN MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the enable inputs
are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against inadvertently entering
shutdown mode during driver/receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the
device is assured to be in shutdown mode. In this low-power shutdown mode, most internal circuitry is powered down, and
the supply current is typically 1 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active.
If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after the enable
times given by tPZH(SHDN) and tPZL(SHDN) in the driver switching characteristics. If the D input is open when the driver is
enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature.
If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the bus inputs
(A and B) after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the receiver switching characteristics. If there is no
valid state on the bus the receiver responds as described in the failsafe operation section.
If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus
inputs (A and B) and the driver output is driven according to the D input. Note that the state of the active driver affects the
inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver outputs are valid.
14
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SLLS562C − MARCH 2003 − REVISED − JUNE 2004
THERMAL CHARACTERISTICS OF IC PACKAGES
ΘJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature
divided by the operating power
ΘJA is NOT a constant and is a strong function of
D
D
D
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
ΘJA can be used to compare the thermal performance of packages if the specific test conditions are defined and used.
Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal
characteristics of holding fixtures. ΘJA is often misused when it is used to calculate junction temperatures for other
installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal
performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in−use
condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%
to 50% difference in ΘJA can be measured between these two test cards
ΘJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow
from die, through the mold compound into the copper block.
ΘJC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict
junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and
junction temperatures are backed out. It can be used with ΘJB in 1-dimensional thermal simulation of a package system.
ΘJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. ΘJB is
only defined for the high-k test card.
ΘJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance
(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system
(see Figure 21).
Ambient Node
CA Calculated
Surface Node
JC Calculated/Measured
Junction
JB Calculated/Measured
PC Board
Figure 21. Thermal Resistance
15
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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