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IRFR/U5505
l
l
l
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Ultra Low On-Resistance
P-Channel
Surface Mount (IRFR5505)
Straight Lead (IRFU5505)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
D
VDSS = -55V
RDS(on) = 0.11Ω
G
ID = -18A
S
I-P a k
TO -2 5 1 A A
D -P a k
T O -2 52 A A
Description
The D-Pak is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ -10V
Continuous Drain Current, VGS @ -10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
-18
-11
-64
57
0.45
± 20
150
-9.6
5.7
-5.0
-55 to + 150
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
2014-8-15
Junction-to-Case
Junction-to-Ambient (PCB mount)**
Junction-to-Ambient
1
Typ.
Max.
Units
–––
–––
–––
2.2
50
110
°C/W
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IRFR/U5505
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Q gs
Q gd
t d(on)
tr
t d(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
-55
–––
–––
-2.0
4.2
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
-0.049
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
12
28
20
16
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
–––
–––
–––
650
270
120
V(BR)DSS
∆V(BR)DSS/∆TJ
I GSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = -250µA
––– V/°C Reference to 25°C, ID = -1mA
0.11
Ω
VGS = -10V, ID = -9.6A „
-4.0
V
VDS = VGS, I D = -250µA
–––
S
VDS = -25V, I D = -9.6A
-25
VDS = -55V, VGS = 0V
µA
-250
VDS = -44V, VGS = 0V, TJ = 150°C
-100
V GS = 20V
nA
100
VGS = -20V
32
ID = -9.6A
7.1
nC VDS = -44V
15
VGS = -10V, See Fig. 6 and 13 „
–––
VDD = -28V
–––
I D = -9.6A
ns
–––
RG = 2.6Ω
–––
RD = 2.8Ω, See Fig. 10 „
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact…
–––
VGS = 0V
–––
pF
VDS = -25V
–––
ƒ = 1.0MHz, See Fig. 5
D
S
Source-Drain Ratings and Characteristics
IS
ISM
VSD
t rr
Q rr
t on
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
‚ Starting TJ = 25°C, L = 3.2mH
RG = 25Ω, IAS = -9.6A. (See Figure 12)
ƒ ISD ≤ -9.6A, di/dt ≤ 290A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
2014-8-15
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– -18
showing the
A
G
integral reverse
––– ––– -64
p-n junction diode.
S
––– ––– -1.6
V
TJ = 25°C, IS = -9.6A, VGS = 0V „
––– 51
77
ns
TJ = 25°C, IF = -9.6A
––– 110 160
nC
di/dt = 100A/µs „
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
…This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact
2
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IRFR/U5505
-I D , Drain-to-Source Current (A)
TOP
BOTTOM
100
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
TOP
-I D , Drain-to-Source Current (A)
100
10
-4.5V
1
BOTTOM
10
-4.5V 20µs PULSE WIDTH
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
TJ = 150 °C
1
0.1
100
1
10
100
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
2.0
R DS(on) , Drain-to-Source On Resistance
(Normalized)
-VDS , Drain-to-Source Voltage (V)
-I D , Drain-to-Source Current (A)
-VDS , Drain-to-Source Voltage (V)
TJ = 25 ° C
TJ = 150 ° C
10
1
V DS = -25V
20µs PULSE WIDTH
0.1
4
5
6
7
8
9
10
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = -10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( ° C)
-VGS , Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 3. Typical Transfer Characteristics
2014-8-15
ID = -16A
3
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IRFR/U5505
20
VGS
Ciss
Crss
Coss
C, Capacitance (pF)
1000
= 0V,
f = 1MHz
= Cgs + Cgd , Cds SHORTED
= Cgd
= Cds + Cgd
800
-VGS, Gate-to-Source Voltage (V)
1200
Ciss
600
Coss
400
Crss
200
0
1
10
ID = -9.6A
VDS = -44V
VDS = -28V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
0
-VDS, Drain-to-Source Voltage (V)
10
20
30
40
Q G, Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
1000
TJ = 150 ° C
-II D , Drain Current (A)
-ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY RDS(on)
10
100
TJ = 25 ° C
1
10us
100us
10
1ms
0.1
0.2
V GS = 0 V
0.6
1.0
1.4
1.8
2.2
-VSD,Source-to-Drain Voltage (V)
1
1
10ms
10
100
-VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
2014-8-15
TC = 25 °C
TJ = 150 °C
Single Pulse
Fig 8. Maximum Safe Operating Area
4
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IRFR/U5505
20
RD
VDS
VGS
I D , Drain Current (A)
16
D.U.T.
RG
+
12
VDD
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
8
Fig 10a. Switching Time Test Circuit
4
td(on)
tr
t d(off)
tf
VGS
10%
0
25
50
75
100
TC , Case Temperature
125
150
( ° C)
90%
VDS
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
2014-8-15
5
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IRFR/U5505
L
VDS
- V
V DD
+ DD
D .U .T
RG
IA S
- 20V
tp
EAS , Single Pulse Avalanche Energy (mJ)
350
A
D R IV E R
0 .0 1 Ω
15V
Fig 12a. Unclamped Inductive Test Circuit
I AS
ID
-4.3A
-6.1A
BOTTOM -9.6A
TOP
300
250
200
150
100
50
0
25
50
75
100
125
Starting T J, Junction Temperature
150
( °C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
tp
V(BR)DSS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
.2µF
.3µF
-10V
QGS
QGD
D.U.T.
+VDS
VGS
VG
-3mA
IG
Charge
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
2014-8-15
ID
Current Sampling Resistors
6
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IRFR/U5505
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
ƒ
+
‚
-
-
„
+

• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
RG
VGS
*
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ISD ]
*** V GS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For P-Channel HEXFETS
2014-8-15
7
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Package Outline
TO-252AA Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
-A1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
0.58 (.023)
0.46 (.018)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
1.02 (.040)
1.64 (.025)
1
2
10.42 (.410)
9.40 (.370)
LEA D AS SIG NME NT S
1 - G AT E
3
0.51 (.020)
MIN.
-B 1.52 (.060)
1.15 (.045)
4 - DRA IN
3X
2X
1.14 (.045)
0.76 (.030)
2 - DRA IN
3 - S OUR CE
0.89 (.035)
0.64 (.025)
0.25 ( .010)
0.58 (.023)
0.46 (.018)
M A M B
NOT ES:
2.28 (.090)
1 DIME NSIO NING & T OLE RANCING P ER A NSI Y 14.5M, 1982.
2 CO NTRO LLING DIMENS ION : INCH.
3 CO NFO RMS T O JEDE C O UTLINE TO -252AA .
4.57 (.180)
4 DIME NSIO NS S HO W N ARE BEF O RE SO LD ER DIP ,
SO LDER DIP MA X. +0.16 (.006).
Part Marking Information
TO-252AA (D-Pak)
E X A M P LE : T H IS IS A N IR F R 120
W IT H A S S E MB L Y
LOT C OD E 9U 1P
IN T E R N A T IO N A L
R E CT IF IE R
LO G O
A
IR F R
12 0
9U
A S S E MB L Y
L O T C OD E
2014-8-15
8
F IR S T P O R T ION
OF P A R T N U MB E R
1P
S E C O N D P O R T ION
OF PART NUMBER
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IRFR/U5505
Package Outline
TO-251AA Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
-A-
0.58 (.023)
0.46 (.018)
1.27 ( .050)
0.88 ( .035)
5.46 (.215)
5.21 (.205)
LEAD AS SIG NMENT S
4
1 - G AT E
2 - DRA IN
6.45 (.245)
5.68 (.224)
3 - S OURCE
4 - DRA IN
6.22 ( .245)
5.97 ( .235)
1.52 ( .060)
1.15 ( .045)
1
2
3
-B -
NOT ES :
1 DIME NSIO NING & T OLE RANCING P ER A NSI Y14.5M, 1982.
2.28 (.090)
1.91 (.075)
2 CO NTRO LLIN G DIMENS ION : INCH.
3 CO NFO RMS TO J EDE C O UT LINE TO -252AA .
9.65 (.380)
8.89 (.350)
4 DIME NSIO NS SHOW N A RE BEF O RE SO LDER DIP ,
SO LDER DIP MA X. +0.16 (.006).
3X
1.14 (.045)
0.76 (.030)
2.28 (.090)
3X
1.14 (.045)
0.89 (.035)
0.89 (.035)
0.64 (.025)
0.25 (.010)
M A M B
0.58 (.023)
0.46 (.018)
2X
Part Marking Information
TO-251AA (I-Pak)
E X A M P LE : TH IS IS A N IR F U1 20
W IT H A S S E M B LY
LO T C O D E 9U 1P
IN TE RN A T IO N A L
R E C T IF IE R
LO GO
IR F U
120
9U
A S S E M B LY
LO T C O D E
2014-8-15
9
F IR S T P O RT IO N
O F P A R T N UM B E R
1P
S E C O N D P O R T ION
OF PART NUMBER
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Tape & Reel Information
TO-252AA
TR
TRR
16 .3 ( .64 1 )
15 .7 ( .61 9 )
1 2 .1 ( .4 76 )
1 1 .9 ( .4 69 )
F E E D D IR E C TIO N
TRL
1 6 .3 ( .6 4 1 )
1 5 .7 ( .6 1 9 )
8 .1 ( .3 1 8 )
7 .9 ( .3 1 2 )
F E E D D IR E C TIO N
N O T ES :
1 . C O N T R O LL IN G D IM E N S IO N : M IL LIM E T E R .
2 . A L L D IM E N S IO N S A R E S H O W N IN M IL L IM E T E R S ( IN C H E S ).
3 . O U T L IN E C O N FO R M S TO E IA -48 1 & E IA -5 4 1 .
1 3 IN C H
16 m m
NO T ES :
1 . O U T L IN E C O N F O R M S T O E IA -4 8 1 .
2014-8-15
10
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