IRFZ48NS
IRFZ48NL
D 2 P ak
l
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T O -26 2
Advanced Process Technology
Surface Mount (IRFZ48NS)
Low-profile through-hole (IRFZ48NL)
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
Description
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-resistance
in any existing surface mount package. The D2Pak is
suitable for high current applications because of its low
internal connection resistance and can dissipate up to 2.0W
in a typical surface mount application.
The through-hole version (IRFZ48NL) is available for lowprofile applications.
Power MOSFET
D
VDSS = 55V
RDS(on) = 0.014Ω
G
ID = 64A
S
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TA = 25°C
PD @TC = 25°C
VGS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
64
45
210
3.8
130
0.83
± 20
32
13
5.0
-55 to + 175
Units
A
W
W
W/°C
V
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RqJC
RqJA
2014-8-10
Junction-to-Case
Junction-to-Ambient ( PCB Mounted,steady-state)**
1
Typ.
Max.
Units
–––
–––
1.15
40
°C/W
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IRFZ48NS/IRFZ48NL
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
LS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Min.
55
–––
–––
2.0
24
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Ciss
Coss
Crss
EAS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Single Pulse Avalanche Energy
–––
–––
–––
–––
V(BR)DSS
IDSS
IGSS
Drain-to-Source Leakage Current
Typ.
–––
0.058
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
12
78
34
50
7.5
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
14
mΩ VGS = 10V, ID = 32A
4.0
V
VDS = V GS, ID = 250µA
–––
S
VDS = 25V, ID = 32A
25
VDS = 55V, VGS = 0V
µA
250
VDS = 44V, VGS = 0V, TJ = 150°C
100
VGS = 20V
nA
-100
VGS = -20V
81
ID = 32A
19
nC VDS = 44V
30
VGS = 10V, See Fig. 6 and 13
–––
VDD = 28V
–––
ID = 32A
ns
–––
RG = 0.85Ω
–––
VGS = 10V, See Fig. 10
–––
nH Between lead,
and center of die contact
1970 –––
VGS = 0V
470 –––
VDS = 25V
120 –––
pF
ƒ = 1.0MHz, See Fig. 5
700
190 mJ IAS = 32A, L = 0.37mH
Source-Drain Ratings and Characteristics
IS
I SM
VSD
trr
Q rr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
64
––– –––
showing the
A
G
integral reverse
––– ––– 210
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 32A, VGS = 0V
––– 68 100
ns
TJ = 25°C, IF = 32A
––– 220 330
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting TJ = 25°C, L = 0.37mH
Pulse width ≤ 400µs; duty cycle ≤ 2%.
This is the destructive value not limited to the thermal limit.
This is the thermal limited value.
RG = 25Ω, IAS = 32A. (See Figure 12)
ISD ≤ 32A, di/dt ≤ 220A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
2014-8-10
2
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IRFZ48NS/IRFZ48NL
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
100
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
100
10
4.5V
20µs PULSE WIDTH
TJ = 25 °C
1
0.1
1
10
4.5V
10
1
0.1
100
Fig 1. Typical Output Characteristics
R DS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
2.5
TJ = 25 ° C
TJ = 175 ° C
10
V DS = 25V
20µs PULSE WIDTH
4
6
8
10
12
100
ID = 64A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
2014-8-10
10
Fig 2. Typical Output Characteristics
1000
1
1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
100
20µs PULSE WIDTH
TJ = 175 °C
Fig 4. Normalized On-Resistance
Vs. Temperature
3
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IRFZ48NS/IRFZ48NL
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
3000
C, Capacitance (pF)
2500
Ciss
2000
1500
1000
Coss
500
20
VGS , Gate-to-Source Voltage (V)
3500
ID = 32A
VDS = 44V
VDS = 27V
VDS = 11V
16
12
8
4
Crss
0
1
10
FOR TEST CIRCUIT
SEE FIGURE 13
0
100
0
20
VDS , Drain-to-Source Voltage (V)
40
60
80
QG , Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
100
TJ = 175 ° C
10
TJ = 25 ° C
1
0.1
0.2
V GS = 0 V
0.7
1.2
1.7
1msec
1
0.1
2.2
VSD ,Source-to-Drain Voltage (V)
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
1
10
100
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
2014-8-10
100µsec
10
4
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IRFZ48NS/IRFZ48NL
70
V DS
I D , Drain Current (A)
60
VGS
RD
D.U.T.
RG
50
+
-V DD
40
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
30
20
Fig 10a. Switching Time Test Circuit
VDS
10
90%
0
25
50
75
100
125
TC , Case Temperature
150
175
( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
P DM
0.10
0.1
0.05
0.02
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.01
0.00001
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
2014-8-10
5
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IRFZ48NS/IRFZ48NL
360
L
VDS
D R IV E R
D .U .T
RG
+
- VD D
IA S
20V
0.0 1 Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS
tp
A
EAS , Single Pulse Avalanche Energy (mJ)
15 V
TOP
300
BOTTOM
ID
13A
23A
32A
240
180
120
60
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature ( °C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
12V
QG
.2µF
.3µF
VGS
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
IG
Charge
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
2014-8-10
ID
Current Sampling Resistors
6
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IRFZ48NS/IRFZ48NL
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
RG
VGS
*
+
-
V DD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For N-channel HEXFET® power MOSFETs
2014-8-10
7
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IRFZ48NS/IRFZ48NL
D2Pak Package Outline
1 0.54 (.4 15)
1 0.29 (.4 05)
1.4 0 (.055 )
M AX.
-A-
1.3 2 (.05 2)
1.2 2 (.04 8)
2
1.7 8 (.07 0)
1.2 7 (.05 0)
1
1 0.16 (.4 00 )
RE F.
-B -
4.69 (.1 85)
4.20 (.1 65)
6.47 (.2 55 )
6.18 (.2 43 )
3
15 .4 9 (.6 10)
14 .7 3 (.5 80)
2.7 9 (.110 )
2.2 9 (.090 )
2.61 (.1 03 )
2.32 (.0 91 )
5 .28 (.20 8)
4 .78 (.18 8)
3X
1.40 (.0 55)
1.14 (.0 45)
5 .08 (.20 0)
0.5 5 (.022 )
0.4 6 (.018 )
0 .93 (.03 7 )
3X
0 .69 (.02 7 )
0 .25 (.01 0 )
M
8.8 9 (.3 50 )
R E F.
1.3 9 (.0 5 5)
1.1 4 (.0 4 5)
B A M
M IN IM U M R E CO M M E ND E D F O O TP R IN T
1 1.43 (.4 50 )
NO TE S:
1 D IM EN S IO N S A FTER SO L D ER D IP.
2 D IM EN S IO N IN G & TO LE RA N C IN G PE R A N S I Y1 4.5M , 198 2.
3 C O N TRO L LIN G D IM EN SIO N : IN C H .
4 H E ATSINK & L EA D D IM EN S IO N S D O N O T IN C LU D E B UR R S.
LE A D A SS IG N M E N TS
1 - G A TE
2 - D R AIN
3 - S O U RC E
8.89 (.3 50 )
17 .78 (.70 0)
3 .8 1 (.15 0)
2 .08 (.08 2)
2X
2.5 4 (.100 )
2X
Part Marking Information
D2Pak
IN TE R N A TIO N A L
R E C T IF IE R
LO G O
A
PART NUM BER
F530S
9 24 6
9B
1M
A S S E M B LY
LO T C O D E
2014-8-10
8
DATE CODE
(Y YW W )
YY = Y E A R
W W = W EEK
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IRFZ48NS/IRFZ48NL
Package Outline
TO-262 Outline
Part Marking Information
TO-262
2014-8-10
9
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IRFZ48NS/IRFZ48NL
Tape & Reel Information
D2Pak
TR R
1 .6 0 (.0 6 3 )
1 .5 0 (.0 5 9 )
1 .60 (.06 3)
1 .50 (.05 9)
4 .1 0 (.1 6 1 )
3 .9 0 (.1 5 3 )
F E E D D IRE CTIO N 1 .8 5 (.0 7 3 )
1 1 .6 0 (.4 5 7 )
1 1 .4 0 (.4 4 9 )
1 .6 5 (.0 6 5 )
0 .3 68 (.0 1 4 5 )
0 .3 42 (.0 1 3 5 )
1 5 .4 2 (.6 0 9 )
1 5 .2 2 (.6 0 1 )
2 4 .3 0 (.9 5 7 )
2 3 .9 0 (.9 4 1 )
TR L
1 .75 (.06 9 )
1 .25 (.04 9 )
10 .9 0 (.42 9)
10 .7 0 (.42 1)
4 .7 2 (.1 3 6)
4 .5 2 (.1 7 8)
16 .10 (.63 4 )
15 .90 (.62 6 )
F E E D D IRE C TIO N
13.50 (.532 )
12.80 (.504 )
2 7.4 0 (1.079)
2 3.9 0 (.9 41)
4
33 0.00
(1 4.1 73)
MA X.
60.00 (2.3 62)
MIN .
NO TES :
1. C O M F O R M S TO E IA -4 18.
2. C O N TR O LLIN G D IM E N S IO N : M ILL IM ET ER .
3. D IM E N S IO N ME A S U R E D @ H U B .
4. IN C LU D E S F LA N G E D IS TO R T IO N @ O U T E R E D G E .
2014-8-10
10
26 .40 (1.03 9)
24 .40 (.961 )
3
3 0.40 (1.1 97)
MAX.
4
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