IS61C5128AL/AS IS64C5128AL/AS

IS61C5128AL/AS
IS64C5128AL/AS
512K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
HIGH SPEED: (IS61/64C5128AL)
• High-speed access time: 10ns, 12 ns
• Low Active Power: 150 mW (typical)
• Low Standby Power: 10 mW (typical) CMOS standby
LOW POWER: (IS61/64C5128AS)
• High-speed access time: 25ns
• Low Active Power: 75 mW (typical)
• Low Standby Power: 1 mW (typical) CMOS standby
• TTL compatible interface levels
• Single 5V ± 10% power supply
• Fully static operation: no clock or refresh
required
• Available in 36-pin SOJ (400-mil), 32-pin
sTSOP-I, 32-pin SOP, 44-pin TSOP-II and 32-pin
TSOP-II packages
• Commercial, Industrial and Automotive temperature ranges available
• Lead-free available
DECEMBER 2013
DESCRIPTION
The ISSI IS61C5128AL/AS and IS64C5128AL/AS are high-
speed, 4,194,304-bit static RAMs organized as 524,288
words by 8 bits. They are fabricated using ISSI's highperformance CMOS technology.This highly reliable process
coupled with innovative circuit design techniques, yields
access times as fast as 12 ns with low power consumption.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced
down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61C5128AL/AS and IS64C5128AL/AS are packaged
in the JEDEC standard 36-pin SOJ (400-mil), 32-pin sTSOP-I,
32-pin SOP, 44-pin TSOP-II and 32-pin TSOP-II packages
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
CE
OE
CONTROL
CIRCUIT
WE
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com 1
Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
HIGH SPEED (IS61/64C5128AL) PIN CONFIGURATION
36-Pin SOJ (400-mil)
44-Pin TSOP (Type II)
A0
1
36
NC
A1
2
35
A18
A2
3
34
A17
A3
4
33
A16
A4
5
32
A15
CE
6
31
OE
I/O0
7
30
I/O7
I/O1
8
29
I/O6
VDD
9
28
GND
GND
10
27
VDD
I/O2
11
26
I/O5
I/O3
12
25
I/O4
WE
13
24
A14
A5
14
23
A13
A6
15
22
A12
A7
16
21
A11
A8
17
20
A10
A9
18
19
NC
NC
NC
A0
A1
A2
A3
A4
CE
I/O0
I/O1
VDD
GND
I/O2
I/O3
WE
A5
A6
A7
A8
A9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A18
A17
A16
A15
OE
I/O7
I/O6
GND
VDD
I/O5
I/O4
A14
A13
A12
A11
A10
NC
NC
NC
PIN DESCRIPTIONS
A0-A18 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7
Bidirectional Ports
VddPower
GND Ground
NC
No Connection
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
LOW POWER (IS61/64C5128AS) PIN CONFIGURATION
32-pin sTSOP (TYPE I)
A11
A9
A8
A13
WE
A18
A15
VDD
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-pin SOP
32-pin TSOP (TYPE II)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
A15
A18
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN DESCRIPTIONS
A0-A18 Address Inputs
CE Chip Enable 1 Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7Input/Output
VddPower
GNDGround
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Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
TRUTH TABLE
I/O PIN
Mode
WE
CE
OE I/O0-I/O7Vdd Current
Not Selected
X
H
X
High-Z
Isb1, Isb2
Output Disabled
H
L
H
High-Z
Icc1, Icc2
Read
H
L
L
DoutIcc1, Icc2
Write
L
L
X
DinIcc1, Icc2
ABSOLUTE MAXIMUM RATINGS(1)
SymbolParameter
Vterm
Terminal Voltage with Respect to GND
Tstg
Storage Temperature
Pt
Power Dissipation
Iout
DC Output Current (LOW)
Value
–0.5 to +7.0
–65 to +150
1.5
20
Unit
V
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
SymbolParameter
Cin
Input Capacitance
Cout
Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.Unit
5
pF
7
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
SymbolParameter
Test Conditions
Min.
Max.
Unit
Output HIGH Voltage
Vdd = Min., Ioh = –4.0 mA
2.4
—
V
Voh
Vol
Output LOW Voltage
Vdd = Min., Iol = 8.0 mA
—
0.4
V
Vih
Input HIGH Voltage
2.2
Vdd + 0.5
V
(1)
Vil
Input LOW Voltage
–0.3
0.8
V
Ili
Input Leakage
GND ≤ Vin ≤ Vdd
Com.–1
1 µA
Ind. –2
2
Auto. –5
5
Ilo
Output Leakage
GND ≤ Vout ≤ Vdd
Com.–1
1 µA
Outputs Disabled
Ind.
–2
2
Auto. –5
5
Note:
4
1. Vil = –3.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
OPERATING RANGE: high speed option (IS61/64C5128AL)
Range
Commercial
Industrial
Automotive
Ambient Temperature
Vdd
0°C to +70°C
5V ± 10%
-40°C to +85°C
5V ± 10%
-40°C to +125°C
5V ± 10%
Speed (ns)
10
10
12
OPERATING RANGe: low power option (IS61/64C5128AS)
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
Vdd
5V ± 10%
5V ± 10%
5V ± 10%
Speed (ns)
25
25
25
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Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
HIGH SPEED OPTION (IS61/64C5128AL)
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
Icc1
Vdd Operating
Vdd = Vdd max., CE = Vil
Com.
Supply Current
Iout = 0 mA, f = 0
Ind.
Auto.
Icc2
Vdd Dynamic Operating
Vdd = Vdd max., CE = Vil
Com.
Supply Current
Iout = 0 mA, f = fmax
Ind.
Auto. typ.(2)
Isb1
TTL Standby Current
Vdd = Vdd max., Com.
(TTL Inputs)
Vin = Vih or Vil
Ind.
CE ≥ Vih, f = 0
Auto.
CMOS Standby
Vdd = Vdd max., Com.
Isb2
Current (CMOS Inputs)
CE ≤ Vdd – 0.2V,
Ind.
Vin ≥ Vdd – 0.2V, or
Auto.
Vin ≤ 0.2V, f = 0
typ.(2)
-10 ns -12 ns
Min. Max.
Min. Max.
Unit
—
45
— 45
mA
—
50 —50
—
55
— 55
—
50
— 45
mA
—
55 —
50
—
70
—
60
30
25
—
15
—15
mA
—
20
—20
—
30
—
30
—
—
—
8
12
20
2
—8
—12
—20
mA
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 5V, Ta = 25% and not 100% tested.
LOW POWER OPTION (IS61/64C5128AS)
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25 ns
SymbolParameter
Test Conditions
Min. Max.
Unit
Icc
Average operating
CE = Vil, Vdd = Max.
Com.
—
10
mA
Current
I OUT= 0 mA, f= 0
Ind.
—15
Auto.
—20
Icc1
Vdd Dynamic Operating Vdd = Max., CE = Vil
Com.
—
25
mA
Supply Current
Iout = 0 mA, f = fmax
Ind.
—30
Auto.
—40
typ.(2)
15
Isb1
TTL Standby Current Vdd = Max., Com.
—
1
mA
(TTL Inputs)
Vin = Vih or Vil, CE ≥ Vih,
Ind.—
1.5
f = 0
Auto.
—
2
Isb2
CMOS Standby
Vdd = Max., Com.
—
0.8mA
Current (CMOS Inputs) CE ≥ Vdd – 0.2V, Ind.—
0.9
Vin ≥ Vdd – 0.2V,
Auto.
—2
or Vin ≤ Vss + 0.2V, f = 0
typ.
0.2
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 5V, Ta = 25% and not 100% tested.
6
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Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
trc
taa
toha
tace
tdoe
thzoe(2)
tlzoe(2)
thzce(2)
tlzce(2)
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to High-Z Output
OE to Low-Z Output
CE to High-Z Output
CE to Low-Z Output
-10 -12-25
Min.Max.
Min. Max.
Min. Max.
10 —
12
—
25
—
— 10
—
12
—
25
3
—
3
—
3
—
— 10
—
12
—
25
—
5
—
6
—
15
0
5
0
6
0
8
0
—
0
—
2
—
0
5
0
6
0
8
2
—
2
—
2
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to
3.0V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480 Ω
480 Ω
5V
5V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
255 Ω
5 pF
Including
jig and
scope
Figure 1
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Rev. C
12/18/2013
255 Ω
Figure 2
7
IS61C5128AL/AS
IS64C5128AL/AS
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
t RC
ADDRESS
t AA
t OHA
DOUT
t OHA
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
t RC
ADDRESS
t AA
t OHA
OE
t HZOE
t DOE
t LZOE
CE
t LZCS
DOUT
t ACS
HIGH-Z
t HZCS
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = Vil.
3. Address is valid prior to or coincident with CE LOW transitions.
8
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Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
SymbolParameter
twc
Write Cycle Time
tsce
CE to Write End
taw
Address Setup Time to Write End
tha
Address Hold from Write End
tsa
Address Setup Time
tpwe1 WE Pulse Width (OE =High)
tpwe2 WE Pulse Width (OE=Low)
tsd
Data Setup to Write End
thd
Data Hold from Write End
(2)
thzwe WE LOW to High-Z Output
tlzwe(2) WE HIGH to Low-Z Output
-10-12 -25
Min.Max.
Min.Max.
Min.Max.
10
—
12
—
25
—
7
—
9
—
18
—
7
—
9
—
18
—
Unit
ns
ns
ns
0
0
7
7
6
0
—
—
—
—
—
—
0
0
9
9
6
0
—
—
—
—
—
—
0
0
15
15
15
0
—
—
—
—
—
—
ns
ns
ns
ns
ns
­ns
—
3
6
—
—
3
6
—
—
5
15
—
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW, and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
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Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCS
t HA
CE
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ Vih.
10
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Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
DOUT
t HZWE
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
CE_WR2.eps
WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
DOUT
DATA UNDEFINED
t HZWE
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ Vih.
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Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
DATA RETENTION SWITCHING CHARACTERISTICS (HIGH SPEED) (IS61/64C5128AL)
Symbol Parameter
Test Condition
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 2.9V, CE ≥ Vdd – 0.2V
Com.
Vin ≥ Vdd – 0.2V, or Vin ≤ Vss + 0.2VInd.
Auto.
typ. (1)
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note:
Min. Max.Unit
2.9
5.5
V
—
8
mA
— 10
— 15
1
0
—
ns
trc —ns
1. Typical Values are measured at Vdd = 5V, Ta = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
4.5V
Data Retention Mode
tRDR
VDD
VDR
CE
GND
12
CE ≥ VDD - 0.2V
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Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
DATA RETENTION SWITCHING CHARACTERISTICS (LOW POWER) (IS61/64C5128AS)
Symbol Parameter
Test Condition
Vdr
Vdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 2.9V, CE ≥ Vdd – 0.2V
Com.
Vin ≥ Vdd – 0.2V, or Vin ≤ Vss + 0.2VInd.
Auto.
typ. (1)
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note:
Min.
Max.Unit
2.9
5.5
V
—
0.8 mA
— 0.9
— 2
0.2
0
—
ns
trc —ns
1. Typical Values are measured at Vdd = 5V, Ta = 25oC and not 100% tested.
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
4.5V
Data Retention Mode
tRDR
VDD
VDR
CE
GND
CE ≥ VDD - 0.2V
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Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
HIGH SPEED (IS61/64C5128Al)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
10
Order Part No.
IS61C5128AL-10KI
IS61C5128AL-10KLI
IS61C5128AL-10TI
IS61C5128AL-10TLI
Package
400-mil Plastic SOJ 400-mil Plastic SOJ, Lead-free
44-pin TSOP-II
44-pin TSOP-II, Lead-free
Automotive Range: –40°C to +125°C
Speed (ns)
12
Order Part No.
IS64C5128AL-12KA3
IS64C5128AL-12CTA3
IS64C5128AL-12CTLA3
Package
400-mil Plastic SOJ
44-pin TSOP-II, Copper Leadframe 44-pin TSOP-II, Lead-free, Copper Leadframe
LOW POWER (IS61/64C5128AS)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
25
14
Order Part No.
IS61C5128AS-25QI
IS61C5128AS-25QLI
IS61C5128AS-25HI
IS61C5128AS-25HLI
IS61C5128AS-25TI
IS61C5128AS-25TLI
Package
450-mil Plastic SOP 450-mil Plastic SOP, Lead-free
32-pin STSOP-I
32-pin STSOP-I, Lead-free 32-pin TSOP-II
32-pin TSOP-II, Lead-free
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Rev. C
12/18/2013
IS61C5128AL/AS
IS64C5128AL/AS
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Rev. C
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IS61C5128AL/AS
16
IS64C5128AL/AS
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Rev. C
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IS64C5128AL/AS
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Rev. C
12/18/2013
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18
4. Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.
5. Reference document : JEDEC SPEC MS-027.
3. Dimension b2 does not include dambar protrusion/intrusion.
2. Dimension D and E1 do not include mold protrusion .
1. Controlling dimension : mm
NOTE :
12/20/2007
IS61C5128AL/AS
IS64C5128AL/AS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
12/18/2013
Rev. C
12/18/2013
Θ
Package Outline
06/04/2008
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
Θ
IS61C5128AL/AS
IS64C5128AL/AS
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