IS61WV25616ALL/BLL

IS61WV25616ALL/ALS
IS61WV25616BLL/BLS
IS64WV25616BLL/BLS
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM
NOVEMBER 2012
FEATURES
HIGH SPEED: (IS61/64WV25616ALL/BLL)
• High-speed access time: 8, 10, 20 ns
• Low Active Power: 85 mW (typical)
• Low Standby Power: 7 mW (typical)
CMOS standby
LOW POWER: (IS61/64WV25616ALS/BLS)
• High-speed access time: 25, 35, 45 ns
• Low Active Power: 35 mW (typical)
• Low Standby Power: 0.6 mW (typical)
CMOS standby
• Single power supply
— Vdd 1.65V to 2.2V (IS61WV25616Axx)
— Vdd 2.4V to 3.6V (IS61/64WV25616Bxx)
• Fully static operation: no clock or refresh required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperature support
• Lead-free available
DESCRIPTION
The ISSI IS61WV25616Axx/Bxx and IS64WV25616Bxx
are high-speed, 4,194,304-bit static RAMs organized as
262,144 words by 16 bits. It is fabricated using ISSI's highperformance CMOS technology.This highly reliable process
coupled with innovative circuit design techniques, yields
high-performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61WV25616Axx/Bxx and IS64WV25616Bxx are packaged in the JEDEC standard 44-pin 400mil SOJ,
44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VDD
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com1
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
I/O PIN
WE CE
OE
LBUB
I/O0-I/O7 I/O8-I/O15Vdd Current
XHXXX
High-Z
High-Z
Isb1, Isb2
H
L
H
X
X
High-Z
High-Z
Icc
X L X H H
High-Z
High-Z
HLLLH
DoutHigh-Z
Icc
HLLHL
High-Z
Dout
H
L
L
L
LDoutDout
L L X L H
DinHigh-Z
Icc
L L X H L
High-Z
Din
L
L
X
L
LDinDin
PIN CONFIGURATIONS
44-Pin TSOP (Type II) and SOJ
A0
A1
A2
A3
A4
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
WE
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
PIN DESCRIPTIONS
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
A0-A17
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
VddPower
GNDGround
*SOJ package under evaluation.
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
PIN CONFIGURATIONS
44-Pin LQFP
48-Pin mini BGA (6mm x 8mm)
2
3
4
5
6
A
LB
OE
A0
A1
A2
N/C
B
I/O8
UB
A3
A4
CE
I/O0
C
I/O9
I/O10
A5
A6
I/O1
I/O2
D
GND
I/O11
A17
A7
I/O3
VDD
E
VDD
I/O12
NC
A16
I/O4
GND
F
I/O14
I/O13
A14
A15
I/O5
I/O6
G
I/O15
NC
A12
A13
WE
I/O7
H
NC
A8
A9
A10
A11
NC
A17
A16
A15
A14
A13
A12
A11
A10
OE
UB
LB
1
44 43 42 41 40 39 38 37 36 35 34
33
1
32
2
31
3
30
4
29
5
TOP VIEW
28
6
27
7
26
8
25
9
24
10
23
11
12 13 14 15 16 17 18 19 20 21 22
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
*LQFP package under evaluation.
PIN DESCRIPTIONS
A0-A17
Address Inputs
I/O0-I/O15
Data Inputs/Outputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
LB
Lower-byte Control (I/O0-I/O7)
UB
Upper-byte Control (I/O8-I/O15)
NC
No Connection
VddPower
GNDGround
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
3
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 3.3V + 5%
SymbolParameter
Test Conditions
Voh
Output HIGH Voltage
Vdd = Min., Ioh = –4.0 mA
Vol
Output LOW Voltage
Vdd = Min., Iol = 8.0 mA
Vih
Input HIGH Voltage
Vil
Input LOW Voltage(1)
Ili
Input Leakage
GND ≤ Vin ≤ Vdd
Ilo
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.
Max.
Unit
2.4
—
V
—
0.4
V
2
Vdd + 0.3
V
–0.3
0.8
V
–11µA
–1
1
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 2.4V-3.6V
Symbol
Voh
Vol
Vih
Vil
Ili
Ilo
Parameter
Test Conditions
Output HIGH Voltage
Vdd = Min., Ioh = –1.0 mA
Output LOW Voltage
Vdd = Min., Iol = 1.0 mA
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
GND ≤ Vin ≤ Vdd
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
Min.Max.Unit
1.8
—
V
—
0.4
V
2.0
Vdd + 0.3
V
–0.3
0.8
V
–11µA
–1
1
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Vdd = 1.65V-2.2V
Symbol
Voh
Vol
Vih
Vil(1)
Ili
Ilo
Parameter
Test Conditions
Vdd Min.Max.Unit
Output HIGH Voltage
Ioh = -0.1 mA
1.65-2.2V
1.4
—
V
Output LOW Voltage
Iol = 0.1 mA
1.65-2.2V
—
0.2
V
Input HIGH Voltage
1.65-2.2V
1.4
Vdd + 0.2
V
Input LOW Voltage
1.65-2.2V–0.2 0.4 V
Input Leakage
GND ≤ Vin ≤ Vdd
–11µA
Output Leakage
GND ≤ Vout ≤ Vdd, Outputs Disabled
–1
1
µA
Note:
1. Vil (min.) = –0.3V DC; Vil (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
Vih (max.) = Vdd + 0.3V DC; Vih (max.) = Vdd + 2.0V AC (pulse width < 10 ns). Not 100% tested.
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
AC TEST CONDITIONS
Parameter
UnitUnit
(2.4V-3.6V)
(3.3V + 10%)
Input Pulse Level
0V to 3V
0V to 3V
Input Rise and Fall Times
1V/ ns
1V/ ns
Input and Output Timing
1.5V
1.5V
and Reference Level (VRef)
Output Load
See Figures 1 and 2
See Figures 1 and 2
Unit
(1.65V-2.2V)
0V to 1.8V
1V/ ns
0.9V
See Figures 1 and 2
AC TEST LOADS
319 Ω
ZO = 50Ω
3.3V
50Ω
1.5V
OUTPUT
30 pF
Including
jig and
scope
Figure 1.
OUTPUT
5 pF
Including
jig and
scope
353 Ω
Figure 2.
Integrated Silicon Solution, Inc. — www.issi.com5
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
ABSOLUTE MAXIMUM RATINGS(1)
SymbolParameter
Vterm
Terminal Voltage with Respect to GND
Vdd
Vdd Relates to GND
Tstg
Storage Temperature
Pt
Power Dissipation
Value
–0.5 to Vdd + 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1,2)
SymbolParameter
Cin
Input Capacitance
CI/O
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.Unit
6
pF
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
6
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
HIGH SPEED (IS61WV25616ALL/BLL)
OPERATING RANGE (Vdd) (IS61WV25616ALL)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Vdd
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Speed
20ns
20ns
20ns
OPERATING RANGE (Vdd) (IS61WV25616BLL)(1)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd (8 ns)1
3.3V + 5%
3.3V + 5%
Vdd (10 ns)1
2.4V-3.6V
2.4V-3.6V
Note:
1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range
of 3.3V + 5%, the device meets 8ns.
OPERATING RANGE (Vdd) (IS64WV25616BLL)
Range
Ambient Temperature
Automotive
–40°C to +125°C
Vdd (10 ns)
2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8
SymbolParameter
Test Conditions Min. Max.
Icc
Vdd Dynamic Operating Vdd = Max., Com.
—
50
Supply Current
Iout = 0 mA, f = fmax
Ind. — 55
Auto. — —
typ.(2)
Icc1
Operating
Vdd = Max., Com.
—
35
Supply Current
Iout = 0 mA, f = 0
Ind. — 40
Auto. — —
Isb1
TTL Standby Current
Vdd = Max., Com.
—
10
(TTL Inputs)
Vin = Vih or Vil
Ind. — 15
CE ≥ Vih, f = 0
Auto.
—
—
Isb2
CMOS Standby
Vdd = Max., Com.
—
8
Current (CMOS Inputs) CE ≥ Vdd – 0.2V,
Ind.
—
9
Vin ≥ Vdd – 0.2V, or Auto. — —
Vin ≤ 0.2V, f = 0
typ.(2)
-10
Min.Max.
—
40
—45
—65
25
—
35
—40
—60
—
10
—15
—
30
—
8
—
9
—20
2
-20
Min.Max. Unit
—
35
mA
—40
—60
—
30
mA
—40
—60
—10 mA
—15
—
30
—
8
mA
—
9
—
20
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
7
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
LOW POWER (IS61WV25616ALS/BLS)
OPERATING RANGE (Vdd) (IS61WV25616ALS)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Automotive
–40°C to +125°C
Vdd
1.65V-2.2V
1.65V-2.2V
1.65V-2.2V
Speed
45ns
45ns
45ns
OPERATING RANGE (Vdd) (IS61WV25616BLS)
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
Vdd (25 ns)
2.4V-3.6V
2.4V-3.6V
OPERATING RANGE (Vdd) (IS64WV25616BLS)
Range
Ambient Temperature
Automotive
–40°C to +125°C
Vdd (35 ns)
2.4V-3.6V
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-25
-35
SymbolParameter
Test Conditions Min.Max. Min.Max.
Icc
Vdd Dynamic Operating
Vdd = Max., Com. —20 —20
Supply Current
Iout = 0 mA, f = fmax
Ind. —25 —25
Auto. —50 —50
typ.(2)
11
Icc1
Operating
Vdd = Max., Com. —10 —10
Supply Current
Iout = 0 mA, f = 0
Ind. —12 —12
Auto. —20 —20
Isb1
TTL Standby Current
Vdd = Max., Com.
—
5
—5
(TTL Inputs)
Vin = Vih or Vil
Ind.
—
7
—
7
CE ≥ Vih, f = 0
Auto.
—
10
—
10
Isb2
CMOS Standby
Vdd = Max., Com.
—
1
—
1
Current (CMOS Inputs)
CE ≥ Vdd – 0.2V,
Ind.
—
2
—
2
Vin ≥ Vdd – 0.2V, or Auto. —10 —
10
Vin ≤ 0.2V, f = 0
typ.(2)
0.2
-45
Min.Max. Unit
—15 mA
—20
—40
—10 mA
—12
—20
—5 mA
—
7
—
10
—
1mA
—
2
—
10
Note:
1. At f = fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at Vdd = 3.0V, Ta = 25oC and not 100% tested.
8
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8
Symbol
Parameter Min. Max.
trc
Read Cycle Time
8
—
taa
Address Access Time
—
8
toha
Output Hold Time
2.0
—
tace
CE Access Time
—
8
tdoe
OE Access Time
—
4.5
thzoe(2)
OE to High-Z Output
—
3
tlzoe(2)
OE to Low-Z Output
0
—
thzce(2
CE to High-Z Output
0
3
tlzce(2)
CE to Low-Z Output
3
—
tba
LB, UB Access Time
—
5.5
thzb(2)
LB, UB to High-Z Output
0
3
(2)
tlzb LB, UB to Low-Z Output
0
—
tpu
Power Up Time
0
—
tpd
Power Down Time
—
8
-10
Min. Max. Unit
10 —
ns
— 10
ns
2.0 —
ns
— 10
ns
— 4.5 ns
—
4
ns
0
—
ns
0
4
ns
3
—
ns
— 6.5 ns
0
3
ns
0
—
ns
0
—
ns
— 10
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage.
Integrated Silicon Solution, Inc. — www.issi.com9
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
trc
taa
toha
tace
tdoe
thzoe(2)
tlzoe(2)
thzce(2
tlzce(2)
-20 ns -25 ns -35 ns
Parameter Min.Max.
Min.Max.
Min.Max.
Read Cycle Time
20 —
25 —
35 —
Address Access Time — 20
— 25
— 35
Output Hold Time
2.5 —
4 —
4 —
CE Access Time
— 20
— 25
— 35
OE Access Time
— 8
— 12
— 15
OE to High-Z Output 0 8
0 8
0 10
OE to Low-Z Output 0—
0—
0—
CE to High-Z Output 0 8
0 8
0 10
CE to Low-Z Output 3 —
10 —
10 —
tba
thzb
tlzb
LB, UB Access Time — 8
LB, UB to High-Z Output 0 8
LB, UB to Low-Z Output 0—
— 25
0 8
0—
— 35
0 10
0—
-45ns
Min.Max.
45 —
— 45
7 —
— 45
— 20
0 15
0—
0 15
15 —
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
— 45
0 15
0—
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to
Vdd-0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = Vil, UB or LB = Vil)
t RC
ADDRESS
t OHA
DOUT
t AA
t OHA
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
tLZOE
CE
tACE
tLZCE
tHZCE
LB, UB
DOUT
VDD
Supply
Current
HIGH-Z
tBA
tLZB
tHZB
tRC
DATA VALID
tPU
50%
tPD
50%
ICC
ISB
UB_CEDR2.eps
Notes:
1.WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = Vil.
3. Address is valid prior to or coincident with CE LOW transition.
Integrated Silicon Solution, Inc. — www.issi.com11
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8-10
Symbol Parameter Min. Max. Min. Max. Unit
twc
Write Cycle Time
8
—
10
—
ns
tsce
CE to Write End
6.5
—
8
—
ns
taw
Address Setup Time 6.5
—
8
—
ns
to Write End
tha
Address Hold from Write End
0
—
0
—
ns
tsa
Address Setup Time
0
—
0
—
ns
tpwb
LB, UB Valid to End of Write
6.5
—
8
—
ns
tpwe1
WE Pulse Width
6.5
—
8
—
ns
tpwe2
WE Pulse Width (OE = LOW)
8.0
—
10
—
ns
tsd
Data Setup to Write End
5
—
6
—
ns
thd
Data Hold from Write End
0
—
0
—­ns
thzwe(2) WE LOW to High-Z Output
—
3.5 —
5
ns
(2)
tlzwe WE HIGH to Low-Z Output
2
—
2
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write. Shaded area product in development
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
twc
tsce
taw
tha
tsa
tpwb
tpwe1
tpwe2
tsd
thd
thzwe(3)
tlzwe(3)
-20 ns-25 ns-35 ns
-45ns
Parameter Min.Max.
Min.Max.
Min.Max.
Min.Max.
Write Cycle Time
20 —
25 —
35 —
45 —
CE to Write End
12 —
18 —
25 —
35 —
Address Setup Time 12 —
15 —
25 —
35 —
to Write End
Address Hold from Write End 0 —
0 —
0 —
0 —
Address Setup Time
0 —
0 —
0 —
0 —
LB, UB Valid to End of Write
12 —
18 —
30 —
35 —
WE Pulse Width (OE = HIGH) 12 —
18 —
30 —
35 —
WE Pulse Width (OE = LOW) 17 —
20 —
30 —
35 —
Data Setup to Write End
9 —
12 —
15 —
20 —
Data Hold from Write End
0 —
0 —­0 —­0 —
WE LOW to High-Z Output
— 9
— 12
— 20
— 20
WE HIGH to Low-Z Output 3 —
5 —
5 —
5 —
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to Vdd0.3V and output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
13
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 )
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t PBW
UB, LB
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
UB_CEWR1.eps
Notes:
1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least
one of the LB and UB inputs being in the LOW state.
2. WRITE = (CE) [ (LB) = (UB) ] (WE).
WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
UB_CEWR2.eps
14
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
AC WAVEFORMS
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
t PBW
UB, LB
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
UB_CEWR3.eps
WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
t WC
ADDRESS
t WC
ADDRESS 1
ADDRESS 2
OE
t SA
CE
LOW
t HA
t SA
WE
UB, LB
t HA
t PBW
t PBW
WORD 1
WORD 2
t HZWE
DOUT
t LZWE
HIGH-Z
DATA UNDEFINED
t HD
t SD
DIN
DATAIN
VALID
t HD
t SD
DATAIN
VALID
UB_CEWR4.eps
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in
valid states to initiate a Write, but any can be deasserted to terminate the Write. The t sa, t ha, t sd, and t hd timing is referenced
to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
Integrated Silicon Solution, Inc. — www.issi.com15
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
HIGH SPEED (IS61WV25616ALL/BLL)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol Parameter
Test Condition
VdrVdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 2.0V, CE ≥ Vdd – 0.2V
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested.
Options
Min.
Typ.(1) Max.Unit
2.0
—
3.6
V
Com.
—
2
8
mA
Ind.
—
—
9
Auto.
15
0
—
—
ns
trc — —ns
o
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol Parameter
Test Condition
VdrVdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 1.2V, CE ≥ Vdd – 0.2V
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested.
Options
Com.
Ind.
Min.
Typ.(1) Max.Unit
1.2
—
3.6
V
—
5
10
mA
—
—
15
0
—
—
ns
trc — —ns
o
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CE
GND
16
CE ≥ VDD - 0.2V
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
LOW POWER (IS61WV25616ALS/BLS)
DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V)
Symbol Parameter
Test Condition
VdrVdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 2.0V, CE ≥ Vdd – 0.2V
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = 3.0V, Ta = 25 C and not 100% tested.
Options
Min.
Typ.(1) Max.Unit
2.0
—
3.6
V
Com.
—
0.2
1
mA
Ind.
—
—
2
Auto.
10
0
—
—
ns
trc — —ns
o
DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V)
Symbol Parameter
Test Condition
VdrVdd for Data Retention
See Data Retention Waveform
Idr
Data Retention Current
Vdd = 1.2V, CE ≥ Vdd – 0.2V
tsdr
Data Retention Setup Time See Data Retention Waveform
trdr
Recovery Time
See Data Retention Waveform
Note 1: Typical values are measured at Vdd = 1.8V, Ta = 25 C and not 100% tested.
Options
Com.
Ind.
Min.
Typ.(1) Max.Unit
1.2
—
3.6
V
—
0.2
1
mA
—
—
2
0
—
—
ns
trc — —ns
o
DATA RETENTION WAVEFORM (CE Controlled)
tSDR
Data Retention Mode
tRDR
VDD
VDR
CE
GND
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
CE ≥ VDD - 0.2V
17
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
ORDERING INFORMATION (HIGH SPEED)
Commercial Range: 0°C to +70°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
10 (81)
Order Part No.Package
IS61WV25616BLL-10TL TSOP (Type II), Lead-free
Note:
1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V to 3.6V.
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
10 (81)
Order Part No.
IS61WV25616BLL-10BI
IS61WV25616BLL-10BLI
IS61WV25616BLL-10TI
IS61WV25616BLL-10TLI
IS61WV25616BLL-10KLI
Package
48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free
TSOP (Type II)
TSOP (Type II), Lead-free
400-mil SOJ, Lead-free
Note:
1. Speed = 8ns for Vdd = 3.3V + 5%. Speed = 10ns for Vdd = 2.4V to 3.6V.
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed (ns)
20
Order Part No.
IS61WV25616ALL-20BI
IS61WV25616ALL-20TI
IS61WV25616ALL-20TLI
Package
48 mini BGA (6mm x 8mm) TSOP (Type II)
TSOP (Type II), Lead-free Automotive Range: -40°C to +125°C
Voltage Range: 2.4V to 3.6V
Speed (ns)
10
18
Order Part No.
IS64WV25616BLL-10BA3
IS64WV25616BLL-10BLA3
IS64WV25616BLL-10CTA3
IS64WV25616BLL-10CTLA3
Package
48 mini BGA (6mm x 8mm)
48 mini BGA (6mm x 8mm), Lead-free
TSOP (Type II), Copper Leadframe
TSOP (Type II), Lead-free, Copper Leadframe
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
ORDERING INFORMATION (LOW POWER)
Industrial Range: -40°C to +85°C
Voltage Range: 2.4V to 3.6V
peed (ns)
S
25
Order Part No.
Package
IS61WV25616BLS-25TLI TSOP (Type II), Lead-free
Industrial Range: -40°C to +85°C
Voltage Range: 1.65V to 2.2V
Speed (ns)
45
Order Part No.
Package
IS61WV25616ALS-45TLI TSOP (Type II), Lead-free
Integrated Silicon Solution, Inc. — www.issi.com19
Rev. H
11/14/2012
20
08/12/2008
Package Outline
1. CONTROLLING DIMENSION : MM .
2. Reference document : JEDEC MO-207
NOTE :
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012
Rev. H
11/14/2012
Package Outline
06/04/2008
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION.
2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION.
1. CONTROLLING DIMENSION : MM
NOTE :
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
Integrated Silicon Solution, Inc. — www.issi.com21
22
SEATING PLANE
4. Formed leads shall be planar with respect to one another within 0.1mm
at the seating plane after final test.
5. Reference document : JEDEC SPEC MS-027.
3. Dimension b2 does not include dambar protrusion/intrusion.
2. Dimension D and E1 do not include mold protrusion .
1. Controlling dimension : mm
NOTE :
12/21/2007
IS61WV25616ALL/ALS, IS61WV25616BLL/BLS,
IS64WV25616BLL/BLS
Integrated Silicon Solution, Inc. — www.issi.com
Rev. H
11/14/2012