IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM JULY 2010 DESCRIPTION The ISSI IS61WV25616Axx/Bxx and IS64WV25616Bxx FEATURES HIGH SPEED: (IS61/64WV25616ALL/BLL) • High-speed access time: 8, 10, 20 ns • Low Active Power: 85 mW (typical) • Low Standby Power: 7 mW (typical) CMOS standby are high-speed, 4,194,304-bit static RAMs organized as 262,144 words by 16 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. LOW POWER: (IS61/64WV25616ALS/BLS) • High-speed access time: 25, 35, 45 ns • Low Active Power: 35 mW (typical) • Low Standby Power: 0.6 mW (typical) CMOS standby • Single power supply — VDD 1.65V to 2.2V (IS61WV25616Axx) • • • • • When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. — VDD 2.4V to 3.6V (IS61/64WV25616Bxx) Fully static operation: no clock or refresh required Three state outputs Data control for upper and lower bytes Industrial and Automotive temperature support Lead-free available Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61WV25616Axx/Bxx and IS64WV25616Bxx are packaged in the JEDEC standard 44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A17 DECODER 256K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE CONTROL CIRCUIT UB LB Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 1 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS TRUTH TABLE I/O PIN I/O0-I/O7 I/O8-I/O15 WE CE OE LB UB Not Selected X H X X X High-Z High-Z ISB1, ISB2 Output Disabled H X L L H X X H X H High-Z High-Z High-Z High-Z ICC Read H H H L L L L L L L H L H L L DOUT High-Z DOUT High-Z DOUT DOUT I CC Write L L L L L L X X X L H L H L L DIN High-Z DIN High-Z DIN DIN I CC Mode PIN CONFIGURATIONS 44-Pin TSOP (Type II) and SOJ A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 VDD Current PIN DESCRIPTIONS 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VDD Power GND Ground *SOJ package under evaluation. 2 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS PIN CONFIGURATIONS 44-Pin LQFP 1 48-Pin mini BGA (6mm x 8mm) 2 3 4 5 6 A17 A16 A15 A14 A13 A12 A11 A10 OE UB LB 1 44 43 42 41 40 39 38 37 36 35 34 33 1 32 2 31 3 30 4 29 5 TOP VIEW 28 6 27 7 26 8 25 9 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22 I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A LB OE A0 A1 A2 N/C B I/O8 UB A3 A4 CE I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 D GND I/O11 A17 A7 I/O3 VDD E VDD I/O12 NC A16 I/O4 GND F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H NC A8 A9 A10 A11 NC 3 4 5 6 WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 2 7 *LQFP package under evaluation. 8 PIN DESCRIPTIONS A0-A17 Address Inputs I/O0-I/O15 Data Inputs/Outputs CE Chip Enable Input OE Output Enable Input WE Write Enable Input LB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No Connection VDD Power GND Ground 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 3 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 3.3V + 5% Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage VIL Input LOW Voltage(1) 2 VDD + 0.3 V –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Min. Max. Unit Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 2.4V-3.6V Symbol Parameter Test Conditions VOH Output HIGH Voltage VDD = Min., IOH = –1.0 mA 1.8 — V VOL Output LOW Voltage VDD = Min., IOL = 1.0 mA — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) VDD = 1.65V-2.2V Symbol Parameter Test Conditions VDD Min. Max. Unit VOH Output HIGH Voltage IOH = -0.1 mA 1.65-2.2V 1.4 — V VOL Output LOW Voltage IOL = 0.1 mA 1.65-2.2V — 0.2 V VIH VIL(1) Input HIGH Voltage 1.65-2.2V 1.4 VDD + 0.2 V Input LOW Voltage 1.65-2.2V –0.2 0.4 V ILI Input Leakage GND ≤ VIN ≤ VDD –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VDD, Outputs Disabled –1 1 µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested. VIH (max.) = VDD + 0.3V DC; VIH (max.) = VDD + 2.0V AC (pulse width < 10 ns). Not 100% tested. 4 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level (VRef) Output Load Unit (2.4V-3.6V) 0V to 3V 1V/ ns 1.5V Unit (3.3V + 10%) 0V to 3V 1V/ ns 1.5V Unit (1.65V-2.2V) 0V to 1.8V 1V/ ns 0.9V See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 2 1 2 3 AC TEST LOADS 4 319 Ω ZO = 50Ω 3.3V 50Ω 1.5V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1. 5 pF Including jig and scope 5 353 Ω 6 Figure 2. 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 5 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM VDD TSTG PT Parameter Terminal Voltage with Respect to GND VDD Relates to GND Storage Temperature Power Dissipation Value –0.5 to VDD + 0.5 –0.3 to 4.0 –65 to +150 1.0 Unit V V °C W Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance CI/O Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. 6 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS HIGH SPEED (IS61WV25616ALL/BLL) OPERATING RANGE (VDD) (IS61WV25616ALL) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C VDD 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V 1 Speed 20ns 20ns 20ns 2 OPERATING RANGE (VDD) (IS61WV25616BLL)(1) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C VDD (8 nS)1 3.3V + 5% 3.3V + 5% 3 VDD (10 nS)1 2.4V-3.6V 2.4V-3.6V 4 Note: 1. When operated in the range of 2.4V-3.6V, the device meets 10ns. When operated in the range of 3.3V + 5%, the device meets 8ns. 5 OPERATING RANGE (VDD) (IS64WV25616BLL) Range Automotive Ambient Temperature –40°C to +125°C VDD (10 nS) 2.4V-3.6V 6 POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter ICC ICC1 VDD Dynamic Operating Supply Current Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX Min. Max. Com. Ind. Auto. typ.(2) — — — 50 55 — 7 -10 Min. Max. — — — -20 Min. Max. Unit 40 45 65 — — — 35 40 60 mA 8 9 25 Operating Supply Current VDD = Max., IOUT = 0 mA, f = 0 Com. Ind. Auto. — — — 35 40 — — — — 35 40 60 — — — 30 40 60 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. Auto. — — — 10 15 — — — — 10 15 30 — — — 10 15 30 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Auto. typ.(2) — — — 8 9 — — — — 8 9 20 — — — 8 9 20 mA 10 11 2 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 12 7 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS LOW POWER (IS61WV25616ALS/BLS) OPERATING RANGE (VDD) (IS61WV25616ALS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C Automotive –40°C to +125°C VDD 1.65V-2.2V 1.65V-2.2V 1.65V-2.2V Speed 45ns 45ns 45ns OPERATING RANGE (VDD) (IS61WV25616BLS) Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C VDD (25 nS) 2.4V-3.6V 2.4V-3.6V OPERATING RANGE (VDD) (IS64WV25616BLS) Range Automotive Ambient Temperature –40°C to +125°C VDD (35 nS) 2.4V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC ICC1 VDD Dynamic Operating Supply Current -25 Min. Max. Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX Com. Ind. Auto. typ.(2) — — — -35 Min. Max. -45 Min. Max. Unit 20 25 50 — — — 20 25 50 — — — 15 20 40 mA 11 Operating Supply Current VDD = Max., IOUT = 0 mA, f = 0 Com. Ind. Auto. — — — 10 12 20 — — — 10 12 20 — — — 10 12 20 mA ISB1 TTL Standby Current (TTL Inputs) VDD = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. Auto. — — — 5 7 10 — — — 5 7 10 — — — 5 7 10 mA ISB2 CMOS Standby Current (CMOS Inputs) VDD = Max., CE ≥ VDD – 0.2V, VIN ≥ VDD – 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. Auto. typ.(2) — — — 1 2 10 — — — 1 2 10 — — — 1 2 10 mA 0.2 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested. 8 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 Symbol tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB(2) tLZB(2) tPU tPD Parameter -10 Min. Max. Min. Max. Read Cycle Time 8 — 10 — ns Address Access Time — 8 — 10 ns Output Hold Time 2.0 — 2.0 — ns CE Access Time — 8 — 10 ns OE Access Time — 4.5 — 4.5 ns OE to High-Z Output — 3 — 4 ns OE to Low-Z Output 0 — 0 — ns CE to High-Z Output 0 3 0 4 ns CE to Low-Z Output 3 — 3 — ns LB, UB Access Time — 5.5 — 6.5 ns LB, UB to High-Z Output 0 3 0 3 ns LB, UB to Low-Z Output 0 — 0 — ns Power Up Time 0 — 0 — ns Power Down Time — 8 — 10 ns 1 Unit 2 3 4 5 6 Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 9 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -20 ns Min. Max. -25 ns Min. Max. -35 ns Min. Max. -45ns Min. Max. Symbol Parameter Unit tRC Read Cycle Time 20 — 25 — 35 — 45 — ns tAA Address Access Time — 20 — 25 — 35 — 45 ns tOHA Output Hold Time 2.5 — 4 — 4 — 7 — ns tACE CE Access Time — 20 — 25 — 35 — 45 ns tDOE OE Access Time — 8 — 12 — 15 — 20 ns tHZOE(2) OE to High-Z Output 0 8 0 8 0 10 0 15 ns tLZOE(2) OE to Low-Z Output 0 — 0 — 0 — 0 — ns (2 tHZCE CE to High-Z Output 0 8 0 8 0 10 0 15 ns (2) tLZCE CE to Low-Z Output 3 — 10 — 10 — 15 — ns tBA LB, UB Access Time — 8 — 25 — 35 — 45 ns tHZB LB, UB to High-Z Output 0 8 0 8 0 10 0 15 ns tLZB LB, UB to Low-Z Output 0 — 0 — 0 — 0 — ns Notes: 1. Test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. 10 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS AC WAVEFORMS 1 READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) t RC 2 ADDRESS t AA t OHA t OHA DOUT 3 DATA VALID PREVIOUS DATA VALID READ1.eps 4 5 READ CYCLE NO. 2(1,3) tRC 6 ADDRESS tAA tOHA OE 7 tHZOE tDOE tLZOE CE tACE tHZCE tLZCE 8 LB, UB DOUT VDD Supply Current HIGH-Z tBA tLZB tHZB tRC DATA VALID tPU 50% tPD 9 ICC 50% ISB UB_CEDR2.eps 10 Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 11 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 Symbol Parameter -10 Min. Max. Min. Max. Unit tWC Write Cycle Time 8 — 10 — ns tSCE CE to Write End 6.5 — 8 — ns tAW Address Setup Time to Write End 6.5 — 8 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWB LB, UB Valid to End of Write 6.5 — 8 — ns tPWE1 WE Pulse Width 6.5 — 8 — ns tPWE2 WE Pulse Width (OE = LOW) 8.0 — 10 — ns tSD Data Setup to Write End 5 — 6 — ns tHD Data Hold from Write End 0 — 0 — ns tHZWE(2) WE LOW to High-Z Output — 3.5 — 5 ns tLZWE WE HIGH to Low-Z Output 2 — 2 — ns (2) Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) -20 ns Min. Max. -25 ns Min. Max. -35 ns Min. Max. -45ns Min. Max. Symbol Parameter tWC Write Cycle Time 20 — 25 — 35 — 45 — ns tSCE CE to Write End 12 — 18 — 25 — 35 — ns tAW Address Setup Time to Write End 12 — 15 — 25 — 35 — ns tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns tSA Address Setup Time 0 — 0 — 0 — 0 — ns tPWB LB, UB Valid to End of Write 12 — 18 — 30 — 35 — ns tPWE1 WE Pulse Width (OE = HIGH) 12 — 18 — 30 — 35 — ns tPWE2 WE Pulse Width (OE = LOW) 17 — 20 — 30 — 35 — ns tSD Data Setup to Write End 9 — 12 — 15 — 20 — ns tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns tHZWE(3) WE LOW to High-Z Output — 9 — 12 — 20 — 20 ns tLZWE WE HIGH to Low-Z Output 3 — 5 — 5 — 5 — ns (3) Unit 1 2 3 4 5 Notes: 1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to VDD-0.3V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 13 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 ) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE t AW t PWE1 t PWE2 WE t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN UB_CEWR1.eps Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID UB_CEWR2.eps 14 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS AC WAVEFORMS 1 WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1) t WC ADDRESS 2 VALID ADDRESS OE LOW CE LOW t HA 3 t AW t PWE2 WE t SA t PBW 4 UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD 5 DATAIN VALID DIN UB_CEWR3.eps 6 WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3) t WC ADDRESS 7 t WC ADDRESS 1 ADDRESS 2 8 OE t SA CE LOW t HA t SA WE UB, LB t PBW t PBW WORD 1 WORD 2 t HZWE DOUT 10 t LZWE HIGH-Z DATA UNDEFINED t HD t SD DIN 9 t HA DATAIN VALID t HD t SD 11 DATAIN VALID UB_CEWR4.eps Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function. Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 15 12 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS HIGH SPEED (IS61WV25616ALL/BLL) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) Min. Typ.(1) Max. Unit 2.0 — 3.6 V — — 2 — 8 9 15 mA See Data Retention Waveform 0 — — ns See Data Retention Waveform tRC — — ns Min. Typ.(1) Max. Unit 1.2 — 3.6 V — — 5 — 10 15 mA Symbol Parameter Test Condition Options VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V tSDR tRDR Data Retention Setup Time Recovery Time Com. Ind. Auto. Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested. O DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Symbol Parameter Test Condition Options VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 1.2V, CE ≥ VDD – 0.2V tSDR tRDR Data Retention Setup Time See Data Retention Waveform 0 — — ns Recovery Time See Data Retention Waveform tRC — — ns Com. Ind. Note 1: Typical values are measured at VDD = 1.8V, TA = 25 C and not 100% tested. O DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode tRDR VDD VDR CE GND 16 CE ≥ VDD - 0.2V Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS LOW POWER (IS61WV25616ALS/BLS) DATA RETENTION SWITCHING CHARACTERISTICS (2.4V-3.6V) 1 Min. Typ.(1) Max. Unit 2.0 — 3.6 V — — 0.2 — 1 2 10 mA See Data Retention Waveform 0 — — ns See Data Retention Waveform tRC — — ns Symbol Parameter Test Condition Options VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 2.0V, CE ≥ VDD – 0.2V tSDR tRDR Data Retention Setup Time Recovery Time Com. Ind. Auto. 2 3 Note 1: Typical values are measured at VDD = 3.0V, TA = 25 C and not 100% tested. O 4 DATA RETENTION SWITCHING CHARACTERISTICS (1.65V-2.2V) Min. Typ.(1) Max. Unit 1.2 — 3.6 V — — 0.2 — 1 2 mA See Data Retention Waveform 0 — — ns See Data Retention Waveform tRC — — ns Symbol Parameter Test Condition Options VDR VDD for Data Retention See Data Retention Waveform IDR Data Retention Current VDD = 1.2V, CE ≥ VDD – 0.2V tSDR tRDR Data Retention Setup Time Recovery Time Com. Ind. 5 6 : Typical values are measured at VDD = 1.8V, TA = 25 C and not 100% tested. O 7 8 DATA RETENTION WAVEFORM (CE Controlled) tSDR Data Retention Mode 9 tRDR VDD 10 VDR CE GND 11 CE ≥ VDD - 0.2V 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 17 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS ORDERING INFORMATION (HIGH SPEED) Commercial Range: 0°C to +70°C Voltage Range: 2.4V to 3.6V Speed (ns) 10 (81) Order Part No. Package IS61WV25616BLL-10TL TSOP (Type II), Lead-free Note: 1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.6V. Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 1 10 (8 ) Order Part No. Package IS61WV25616BLL-10BI IS61WV25616BLL-10BLI IS61WV25616BLL-10TI IS61WV25616BLL-10TLI 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II) TSOP (Type II), Lead-free Note: 1. Speed = 8ns for VDD = 3.3V + 5%. Speed = 10ns for VDD = 2.4V to 3.6V. Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V Speed (ns) 20 Order Part No. Package IS61WV25616ALL-20BI IS61WV25616ALL-20TI IS61WV25616ALL-20TLI 48 mini BGA (6mm x 8mm) TSOP (Type II) TSOP (Type II), Lead-free Automotive Range: -40°C to +125°C Voltage Range: 2.4V to 3.6V Speed (ns) 10 18 Order Part No. Package IS64WV25616BLL-10BA3 IS64WV25616BLL-10BLA3 IS64WV25616BLL-10CTA3 IS64WV25616BLL-10CTLA3 48 mini BGA (6mm x 8mm) 48 mini BGA (6mm x 8mm), Lead-free TSOP (Type II), Copper Leadframe TSOP (Type II), Lead-free, Copper Leadframe Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS ORDERING INFORMATION (LOW POWER) Industrial Range: -40°C to +85°C Voltage Range: 2.4V to 3.6V Speed (ns) 25 1 Order Part No. Package IS61WV25616BLS-25TLI TSOP (Type II), Lead-free 2 Industrial Range: -40°C to +85°C Voltage Range: 1.65V to 2.2V Speed (ns) 45 3 Order Part No. Package IS61WV25616ALS-45TLI TSOP (Type II), Lead-free 4 5 6 7 8 9 10 11 12 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 19 20 08/12/2008 Package Outline 1. CONTROLLING DIMENSION : MM . 2. Reference document : JEDEC MO-207 NOTE : IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 Integrated Silicon Solution, Inc. — www.issi.com Rev. G 07/15/2010 Package Outline 06/04/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : IS61WV25616ALL/ALS, IS61WV25616BLL/BLS, IS64WV25616BLL/BLS 1 2 3 4 5 6 7 8 9 10 11 12 21