a FEATURES 256 Switches in a 16 ⴛ 16 Array Wide Signal Range: to Supply Rails of 24 V or ⴞ12 V Low On-Resistance: 200 ⍀ Typ TTL/CMOS/Microprocessor-Compatible Control Lines Serial Input Simplifies Interface Serial Output Allows Cascading for More Channels Low Power Consumption: 2 mW Quiescent Compact 44-Lead PLCC 16 ⴛ 16 Crosspoint Switch Array AD75019 FUNCTIONAL BLOCK DIAGRAM ANALOG INPUTS/OUTPUTS X0 X15 SERIAL DATA IN VDD VSS VCC DGND +12V –12V +5V DGND Y0 LATCH ANALOG SWITCH ANALOG OUTPUTS/ INPUTS SHIFT REGISTER CELL #256 AD75019 BUSED CLOCK LINES SERIAL DATA TO NEXT STAGES 16 3 16 ARRAY OF SWITCHES, LATCHES, AND SHIFT REGISTER CELLS (ONLY TWO LOCATIONS ARE SHOWN FOR CLARITY) SERIAL DATA FROM PRIOR STAGES BUSED CLOCK LINES Y15 ANALOG SWITCH PARALLEL CLOCK SERIAL CLOCK PCLK PRODUCT DESCRIPTION The AD75019 contains 256 analog switches in a 16 × 16 array. Any of the X or Y pins may serve as an input or output. Any or all of the X terminals may be programmed to connect to any or all of the Y terminals. The switches can accommodate signals with amplitudes up to the supply rails and have a typical onresistance of 150 Ω. Data is loaded serially via the SIN input and clocked into an onboard 256-bit shift register via SCLK. When all the switch settings have been programmed, data is transferred into a set of 256 latches via PCLK. The serial shift register is dynamic, so there is a minimum clock rate of 20 kHz. The maximum clock rate of 5 MHz allows loading times as short as 52 µs. The switch control latches are static and will hold their data as long as power is applied. SHIFT REGISTER CELL #1 LATCH SCLK SOUT To extend the number of switches in the array, you may cascade multiple AD75019s. The SOUT output is the end of the shift register, and may be connected to the SIN input of the next AD75019. The AD75019 is fabricated in Analog Devices’ BiMOS II process. This epitaxial BiCMOS process features CMOS devices for low distortion switches and bipolar devices for ESD protection. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD75019–SPECIFICATIONS1(T = +25ⴗC, V A AD75019 MULTIPLEXER Input Signal Range Switch ON Resistance, V DD and VSS = ± 12 V, VSIGNAL = ± 12 V Switch ON Resistance, V DD and VSS = ± 5 V, VSIGNAL = ± 5 V Switch ON Resistance Matching 2, VSIGNAL = ± 12 V Leakage Current, VSIGNAL = ± 10 V Input/Output Capacitance Isolation Between Any Two Channels RS = 600 Ω, RL = 10 kΩ, VSIGNAL = 2 V p-p fSIGNAL = 1 kHz fSIGNAL = 20 kHz fSIGNAL = 1 MHz Total Harmonic Distortion RS = 600 Ω, RL = 10 kΩ, VSIGNAL = 2 V p-p Switch Frequency Response, –3 dB RS = 600 Ω, RL = 10 kΩ, VSIGNAL = 2 V p-p Propagation Delay DIGITAL INPUTS (SIN, SCLK, PCLK) Logic Levels (TTL Compatible) Input Voltage, Logic “1” Input Voltage, Logic “0” Input Current, VIH = 5.5 V Input Current, VIL = 0.8 V Input Capacitance DIGITAL OUTPUTS (SOUT) Logic Levels (TTL Compatible) Output Voltage, Logic “1” Output Voltage, Logic “0” Output Current, VOH = 2.8 V Output Current, V OL = 0.4 V POWER SUPPLY REQUIREMENTS Voltage Range, Total Analog Voltage Range, Positive Analog Voltage Range, Negative Analog Voltage Range, Digital Supply Current, SCLK = 5 MHz, VIL = 0.8 V, VIH = 2.4 V Supply Current, Quiescent, VIL = 0.8 V, VIH = 2.4 V TEMPERATURE RANGE Operating Storage DD and VSS = ⴞ12 V, VCC = +5 V unless otherwise noted) Symbol Min VIN RON RON ∆RON VSS – 0.5 Typ Max Units 150 300 20 2 VDD + 0.5 300 500 30 10 25 V Ω Ω Ω nA pF CIN 92 69 38 dB dB dB 0.01 % 8 MHz ns 5.5 0.8 ±1 ±1 10 V V µA µA pF 20 4 VIH VIL IIH IIL CIN 2.4 0 VOH VOL IOH IOL 2.8 VDD – VSS VDD – VDGND VSS – VDGND VCC – VDGND IDD, ISS ICC IDD, ISS ICC 9.0 (VCC – 0.5) –20.7 4.5 TMIN, TMAX –25 –65 V V mA mA 0.4 3.2 3.2 5 _ _ 25.2 25.2 0 5.5 ± 70 800 ⴞ400 100 V V V V mA µA µA µA +85 +150 °C °C NOTES 1 All minimum and maximum specifications are guaranteed, and specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. 2 Switch resistance matching is measured with zero volts at each analog input and refers to the difference between the maximum and minimum values. Specifications subject to change without notice. –2– SOUT DGND 4 2 1 44 43 42 41 40 3 NC PCLK 5 VCC VDD SCLK 6 PIN 1 IDENTIFIER Y15 7 Y14 8 39 NC 38 Y7 Y13 9 37 Y6 Y12 10 Y11 11 36 Y5 Y10 12 Y9 13 AD75019 35 Y4 TOP VIEW (Not to Scale) 34 Y3 33 Y2 Y8 14 32 Y1 X0 15 31 Y0 X1 16 X2 17 30 X15 29 X14 X13 X11 X12 X10 X9 18 19 20 21 22 23 24 25 26 27 28 X7 X8 Description Analog Input (or Output) Analog Input (or Output) Analog Input (or Output) Analog Input (or Output) Analog Input (or Output) Analog Input (or Output) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) No Internal Connection No Internal Connection Positive Analog Power Supply Digital Power Supply Digital Ground Serial Data Output: Positive True VSS SIN Name X8 X9 X10 X11 X12 X13 X14 X15 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 NC NC VDD VCC DGND SOUT X6 Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 NC Description Parallel Clock Input Serial Clock Input Serial Data Input Negative Analog Power Supply No Internal Connection No Internal Connection Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Output (or Input) Analog Input (or Output) Analog Input (or Output) Analog Input (or Output) Analog Input (or Output) Analog Input (or Output) Analog Input (or Output) Analog Input (or Output) Analog Input (or Output) X4 X5 Name PCLK SCLK SIN VSS NC NC Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 X0 X1 X2 X3 X4 X5 X6 X7 X3 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 NC PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS NC = NO CONNECT REV. C AD75019 TIMING CHARACTERISTICS1 (T = T A MIN to TMAX, rated power supplies unless otherwise noted) Parameter Symbol Value Units Condition Data Setup Time SCLK Pulsewidth Data Hold Time SCLK Pulse Separation SCLK to PCLK Delay SCLK to PCLK Delay and Release PCLK Pulsewidth Propagation Delay, PCLK to Switches On or Off Data Load Time SCLK Frequency SCLK, PCLK Rise and Fall Times t1 t2 t3 t4 t5 (t5 + t6) t6 _ _ _ _ 20 100 40 100 65 5 65 70 52 20 1 ns ns ns ns ns ms ns ns µs kHz µs min min min min min max min max SCLK = 5 MHz min max NOTES 1 Timing measurement reference level is 1.5 V. Specifications subject to change without notice. TIMING DIAGRAM LOAD DATA INTO SERIAL REGISTER DURING RISING EDGE t4 1 SCLK t2 0 t1 1 = CLOSE SIN 0 = OPEN t3 Y15–X15 Y15–X14 Y0–X0 t5 1 PCLK t6 TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL 0 OPERATION TRUTH TABLE Control Lines PCLK SCLK SIN SOUT Operation/Comment 1 1 0 1 X Datai X Datai-256 0 X X X No operation. The data on the SIN line is loaded into the serial register; data clocked into the serial register 256 clocks ago appears at the SOUT output. Data in the serial shift register transfers into the parallel latches which control the switch array. APPLICATIONS INFORMATION Loading Data Data to control the switches is clocked serially into a 256-bit shift register and then transferred in parallel to 256 bits of memory. The rising edge of SCLK, the serial clock input, loads data into the shift register. The first bit loaded via SIN, the serial data input, controls the switch at the intersection of row Y15 and column X15. The next bits control the remaining columns (down to X0) of row Y15, and are followed by the bits for row Y14, and so on down to the data for the switch at the intersection of row Y0 and column X0. The shift register is dynamic, so there is a minimum clock rate, specified as 20 kHz. After the shift register is filled with the new 256 bits of control data, PCLK is activated (pulsed low) to transfer the data to the parallel latches. Since the shift register is dynamic, there is a maximum time delay specified before the data is lost: PCLK must be activated and brought back high within 5 ms after filling the shift register. The switch control latches are static and will hold their data as long as power is applied. Power Supply Sequencing and Bypassing All junction-isolated parts operating on multiple power supplies require proper attention to supply sequencing. Because BiMOS II is a junction-isolated process, parasitic diodes exist between VDD and VCC, and between VSS and DGND. As a result, VDD must always be greater than (VCC – 0.5 V), and VSS must always be less than (DGND + 0.5 V). If you can’t ensure that system power supplies will sequence to meet these conditions, external Schottky (e.g., 1N5818) or silicon (e.g., 1N4001) diodes may be used. To protect the positive side, the anode would connect to VCC (Pin 42) and the cathode to VDD (Pin 41). For the negative side, connect the anode to VSS (Pin 4) and the cathode to DGND (Pin 43). Each of the three power supply pins [VDD (Pin 41), VCC (Pin 42) and VSS (Pin 4)] should be bypassed to DGND (Pin 43) through a 0.1 µF ceramic capacitor located close to the package pins. Transistor Count AD75019 contains 5,472 transistors. This number may be used To extend the number of switches in the array, you may cascade for calculating projected reliability. multiple AD75019s. The SOUT output is the end of the shift register, and may be directly connected to the SIN input of the next AD75019. REV. C –3– AD75019 ABSOLUTE MAXIMUM RATINGS* Max Units –0.5 –25.2 –0.5 –0.5 –0.5 –0.3 +25.2 +0.5 +7.0 +25.2 +25.2 VCC + 0.5 1.0 +70 +150 +300 V V V V V V W °C °C °C 0 –65 Conditions C1502c–0–8/99 VDD to DGND VSS to DGND VCC to DGND VDD to VSS VCC to VSS Digital Inputs to DGND Power Dissipation Operating Temperature Range Storage Temperature Lead Temperature Min TA ⱕ 75°C Soldering, 10 sec *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION WARNING! ESD (electrostatic discharge) sensitive device. The digital control inputs are Zener protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. ESD SENSITIVE DEVICE ORDERING GUIDE Model Temperature Range Package Option* AD75019JP 0°C to +70°C P-44A *P = Plastic Leaded Chip Carrier (PLCC) Package. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Leaded Chip Carrier (P-44A) 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 6 7 PIN 1 IDENTIFIER 0.025 (0.63) 0.015 (0.38) 40 39 0.050 (1.27) BSC 17 BOTTOM VIEW (PINS UP) 0.040 (1.01) 0.025 (0.64) 0.656 (16.66) SQ 0.650 (16.51) 0.695 (17.65) SQ 0.685 (17.40) PIN 1 IDENTIFIER 0.032 (0.81) 0.026 (0.66) 29 28 18 0.020 (0.50) R 0.63 (16.00) 0.59 (14.99) 0.021 (0.53) 0.013 (0.33) TOP VIEW (PINS DOWN) 0.020 (0.50) R PRINTED IN U.S.A. 0.048 (1.21) 0.042 (1.07) 0.110 (2.79) 0.085 (2.16) –4– REV. C