RENESAS M62281FP

M62281P/FP
General Purpose Current Mode PWM Control IC
REJ03D0840-0201
Rev.2.01
Nov 14, 2007
Description
M62281P/FP is designed as a high speed current mode PWM control IC.
This small 10 pin package contains many functions and protection circuits allowing simpler peripheral circuit and
compact set design.
This IC can operate high speed switching (700 kHz Max.) with high speed current sense comparator and current
limiting circuit.
Features
• 700 kHz applicable to MOS-FET
 Output current Io(peak) = ±1 A
 Totempole output
• CURRENT SENSE terminal separate from CLM terminal makes SMPS strong in noise.
• High speed pulse-by-pulse current limiting
• Timer type latch protection circuit with OVP (external reset is possible)
• Soft start operation is possible (with dead time control)
• Built-in OP Amp for feedback control (photo coupler can be driven)
• Small start-up current 180 µA
• Start-up voltage 12.5 V, Stop voltage 8.3 V
Application
Switching Regulator
DC/DC converter
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 1 of 12
M62281P/FP
Block Diagram
VCC
CLM
UVLO
CLM
comp.
CT
(OVP)
Timer
latch
CLM
Latch
0.2 V
COLLECT Note
R
CS
comp.
EA IN
S
VOUT
S
PWM
Latch
−
R
+
EMIT Note
GND
2.5 V
OSC.
EA
SOFT
CURRENT
OUT (Duty set-up) SENSE
CF
Note: GND terminal is connected to emitter terminal as M62281FP in IC inside.
And VCC terminal is connected to collector terminal as M62281FP in IC inside.
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 2 of 12
M62281P/FP
Pin Arrangement
M62281FP
VOUT
1
10
VCC
GND
2
9
EA IN
CLM
3
8
EA OUT
CURRENT
SENSE
4
7
CT
CF
5
6
SOFT
(Top view)
Outline: PRSP0010DB-A (10P2N-A)
M62281P
VOUT
1
14
COLLECT
EMIT
2
13
VCC
GND
3
12
EA IN
CLM
4
11
EA OUT
CURRENT
SENSE
5
10
CT
CF
6
9
SOFT
N.C
7
8
N.C
(Top view)
Outline: PRDP0014AA-A (14P4)
Absolute Maximum Ratings
(Ta = 25°C, unless otherwise noted)
Item
Ratings
Unit
VCC
IOUT
36
150
V
mA
CT terminal supply voltage
VCT
1.0
36
A
V
EA IN terminal supply voltage
CLM terminal supply voltage
VEA IN
VCLM
10
−0.3 to +4.0
V
V
CURRENT SENSE terminal supply voltage
Power dissipation
VCS
Pd
−0.3 to +5.8
1500
V
mW
Kθ
440
12
mW/°C
°C
°C
Supply voltage
Output terminal current
Thermal derating
Symbol
Operating temperature
Topr
3.52
−20 to +85
Storage temperature
Tstg
−40 to +150
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 3 of 12
Condition
Continuous
Peak
P
Ta ≥ 25°C
FP
P
FP
M62281P/FP
Electrical Characteristics
(Ta = 25°C, VCC = 14 V, unless otherwise noted)
Block
Item
Max.
Unit
All
device
Supply voltage range
Operation start-up voltage
VCC
VCC(START)
VCC(STOP)
11.5

12.5
35
13.5
V
V
Operation stop voltage
Start-up and stop Voltage
difference
VCC(STOP)
∆VCC
7.6
3.5
8.3
4.2
9.0
5.1
V
V
Stand-by current
ICCL
90
180
270
µA
CT
Error
Amp
Current
sense
CLM
SOFT
OSC
Symbol
Limits
Typ.
Min.
Test Conditions
VCC = VCC(START) −
0.5 V
Operating current
ICCO
7.5
13
19
mA
Timer latch circuit current
ICCOFF
0.9
0.8
2.0
1.8
3.0
2.7
mA
mA
CT term. “H” threshold
voltage
CT term. “L” threshold
voltage
VTHCTH
3.5
4.0
4.5
V
VTHCTL
0.4
0.7
1.0
V
CT term. discharge
current
CT term. charge current
ICTDCHG
70
110
165
µA
In normal operation
ICTCHG
−33
−14
−5
µA
In CLM actuating
Reference voltage
Input bias current
VB
IB
2.4
−300
2.5
−100
2.6
0
V
nA
Open loop gain
Unity gain bandwidth
AV
fT


70
1


dB
MHz
Output source current
Output voltage (High)
IOS
VOm+
−460
5.3
−370
5.8
−240
6.25
µA
V
Output voltage (Low)
CS term. input voltage
gain
VOm−
AVCS
0

0.2
3.0
0.35

V
V/V
Input bias current
CS term. delay time
IB
TPDCS
−5

−1
150


µA
ns
CLM term. threshold
voltage
CLM term. output current
VTHCLM
180
200
220
mV
IOUTCLM
VCC = 14 V
VCC = VCC(STOP) +
0.2 V
VEAIN = 0 V
Delay time to output
−270
−200
−140
µA
VCLM = 0 V
CLM term. delay time
Input voltage range at 0%
duty
TPDCLM
VSOFT (0%)

0
100


1.0
ns
V
Delay time to output
Soft term. voltage
range to set 0% duty
Input voltage at 50% duty
VSOFT (50%)

2.7

V
Soft term. voltage at
50% duty
Maximum duty
Duty Max
83
90
97
%
Soft term. input current
Maximum oscillation
frequency
ISOFT
fOSCmax
−50

−43

−36
700
kHz
Oscillation frequency
Oscillation upper limit
voltage
fOSC
VOSCH
130
3.2
180
3.6
230
4.0
kHz
V
CF = 270 pF
CF = 270 pF
Oscillation lower limit
voltage
Oscillation voltage
VOSCL
1.2
1.4
1.6
V
CF = 270 pF
∆VOSC
1.9
2.2
2.5
V
CF = 270 pF
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 4 of 12
M62281P/FP
(Ta = 25°C, VCC = 14 V, unless otherwise noted)
Block
Output
Item
Symbol
Output low voltage
Output high voltage
Output voltage rise time
Output voltage fall time
Limits
Typ.
Max.
Unit
VOL1

0.04
0.4
V
VOL2

0.3
1.4
V
VOH1
12.0
12.7

V
VOH2
11.5
12.5

V
TRISE
TFALL


50
35


ns
ns
Min.
Test Conditions
VCC = 14 V,
IO = 10 mA
VCC = 14 V,
IO = 100 mA
VCC = 14 V,
IO = −10 mA
VCC = 14 V,
IO = −100 mA
No load
No load
Function Description and Application
EA IN, EA OUT Terminal
Circuit for EA OUT terminal is connected to constant current load (370 µA Typ.) shown in figure 1. Output voltage of
error amp. is controlled by the output transistor to provide current-sense comp. with the controlled voltage.
370 µA
EA OUT
To current-sense
comp.
Figure 1 Circuit Diagram of EA OUT Terminal
1. Peripheral circuit of Error Amp
Detected voltage divided by R1 and R2 is input to EA IN terminal in such case as fly-back system where VCC line
voltage is proportional to output voltage, or in the case that the voltage detection is made on the primary side. In
this case operating region is set by R1 and R2, and AC gain by R1//R2, RF.
From detecting voltage
Reference voltage (2.5 V)
+
R1
−
EA IN
R2
EA
OUT
RF
Figure 2 Method to Detect The Voltage on The Primary Side
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 5 of 12
M62281P/FP
In the case that feed forward system by photo-coupler is applied, following two methods are available.
One is the method by error amp. as in figure 3-1, the other is by the direct connection to photo-coupler as in figure
3-2.
When photo-coupler is directly connected to EA OUT terminal, input terminal of error amp. is connected to GND,
photo-coupler is connected directly to EA OUT terminal.
VCC
R1
Reference voltage (2.5 V)
+
RIN
EA IN
−
EA
OUT
R2
RF
Figure 3-1 Method to Use Photo-Coupler (1)
Reference voltage (2.5 V)
+
−
EA IN
EA OUT
Figure 3-2 Method to Use Photo-Coupler (2)
In figure 3-1, AC gain is represented as :
AV =  RF / RIN 
Proper gain setting is about 40 dB.
RF should be 52 kΩ or more due to the current source capability of error amp.
R1, R2 should meet the condition as below so that the voltage of EA IN terminal should not be over 5 V.
R2 • VCC / (R1 + R2) ≤ 5 V
Due to the input impedance of EA IN terminal, the current in R1, R2 should be less than several mA.
CT (OVP) Terminal
Timer type latch circuit works as follows.
Constant charge current flows out from CT terminal to the external capacitor when CLM is operative.
When the voltage of CT terminal rises up to over 4.0 V (Typ.), the latch circuit operates to make functions of this IC
inoperative. Inoperative status is sustained until supply voltage becomes less than stop voltage. The value for start-up
register has to be set so that the current over 1.8 mA (Typ.) can flow the resistor because the stop status has to be kept
by the current in start-up resistor R1 shown in application circuit.
When timer latch circuit is operative, supply current increases at high voltage as shown in figure 4 to avoid the damage
caused by unnecessarily in creased supply voltage.
Inoperative status goes back to operation by forcibly decreasing the voltage of CT terminal to less then 0.7 V.
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 6 of 12
Supply Current (at timer latch) ICCOFF (mA)
M62281P/FP
3.0
2.5
Latch reset
8.3 V
2.0
1.5
1.0
0.5
0
5
10
15
20
25
30
35
40
Supply Voltage VCC (V)
Figure 4 Supply Current vs. Supply Voltage Characteristics (at Timer Latch)
Even if the timer function is not needed, latch function operates, that is, IC becomes in operative when the voltage of
CT terminal is forced to be high voltage. Therefore, CT terminal can also be used for OVP (over voltage protection).
When only OVP function is needed (timer latch function is not necessary), connect the resistor between CT terminal
and GND. In this case, the above mentioned charge current cannot make the voltage of CT terminal rise up to “H”
threshold, thus latch function does not operate. (Refer to figure 5-1, 5-2)
VCC
OVP function operates
when photo-coupler is ON.
CT
+
Figure 5-1 Method to Use Timer Type Latch And OVP
VCC
OVP function operates
when photo-coupler is ON.
CT
+
Figure 5-2 Method to Use Only OVP
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 7 of 12
M62281P/FP
SOFT (Duty Set-Up) Terminal
The voltage of SOFT terminal determines the maximum duty.
Maximum duty can be set by connecting the resistor as in figure 6 because the constant current compensated for
temperature flows out of this terminal.
And by connecting the capacitor between the terminal and GND, soft start function operates. That is, we can get the
gradual increase of maximum duty at start-up.
SOFT
CSOFT
+
VSOFT
Figure 6 Method to Set Up Duty and SOFT Start Function
Maximum duty is represented as :
Duty (Max.) ≈ (42 • VSOFT) − 59 (%)
where VSOFT = ISOFT • RSOFT (V), ISOFT = 43 µA (Typ.)
If the voltage of SOFT terminal is higher than 3.53 V (Typ.) (upper limit voltage of the oscillation waveform),
maximum duty is internally decided to be 90%.
Soft start time (TSOFT) is represented as :
TSOFT ≈ CSOFT • 31 • 10 (s)
3
TSOFT means the time from start-up until the voltage of SOFT terminal goes up to higher than 1.4 V (Typ.) (lower limit
voltage of the oscillation waveform).
Discharging circuit operative before start-up at VCC is internally equipped so that the soft start never fail to operate at
the restart of voltage supply.
CLM Terminal
This terminal is for pulse-by-pulse current limiting.
Current limiting circuit is almost the same as that of M51995.
CLM terminal is separate from CURRENT SENSE terminal allowing the noise filter to be optimized and the highspeed over current protection.
The voltage detected by the current detecting resistor can be directly input as shown in figure 7-1, if the detected
voltage is about the threshold voltage (200 mV (Typ.)), but if the voltage is larger than the threshold, the voltage has to
be input divided by resistors as shown in figure 7-2.
CLM
OUT
RNF
CNF
RCS
Figure 7-1 Peripheral Circuit of CLM
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 8 of 12
M62281P/FP
CLM
OUT
RNF1
CNF
RNF2
RCS
Figure 7-2 Peripheral Circuit of CLM When The Detected Voltage is High
1000 pF to 22000 pF is recommended for CNF. Be sure to use 100 Ω or less for RNF and RNF1 // RNF2 (*) so that the
detection sensitivity is not influenced by the current flown out from CLM terminal.
Non-inductive resistor is recommended for current detecting resistor.
* RNF1 // RNF2 = (RNF1 • RNF2) / (RNF1 + RNF2)
CURRENT SENSE Terminal
The voltage proportional to the switching current is supplied to this terminal.
Output duty is controlled by comparing this voltage with the output of error amp..
CLM and CURRENT SENSE terminal is separate from each other, so various settings are available depending upon the
application.
CURRENT
SENSE
OUT
RNF
CNF
RCS
VCS
Figure 8 Peripheral Circuit of CURRENT SENSE
RCS is determined by :
VCS = (VEA OUT − 1.3) / 3 (V), where VEA OUT represents the voltage of EA OUT terminal.
CF Terminal
Oscillation frequency is set by capacitor connected to CF terminal.
The waveform of CF terminal is triangular one with the ratio of 9 : 1 for charge-discharge period.
Oscillation frequency is represented as :
fOSC =
1
(19.4 ×
103
× COSC) + (0.4 × 10−6)
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 9 of 12
(Hz)
M62281P/FP
Attention for heat generation
Although the absolute maximum rating of ambient temperature is spelled out as 85°C, it is always annoying to specify
the location this temperature refers to because the power dissipation generated locally in switching regulator is fairly
large and the temperature in the vicinity of the IC varies from place to place.
One of the recommendable ways to solve this problem is to check the temperature on the surface of the IC.
The difference in temperature between IC junction and the surface of IC package is 30°C or less when IC junction
temperature is measured by utilizing the temperature characteristics of p-n junction forward voltage, and the surface
temperature by "thermo-viewer" on the condition that the IC is mounted on the "phenol-base" PC board in normal
atmosphere.
This concludes that maximum case temperature (surface temperature of IC package) rating is 100°C with adequate
margin considering the absolute maximum rating of junction temperature is 150°C.
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 10 of 12
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 11 of 12
AC
input
CFIN
+
R2
+
CT
+
CVCC
EA
IN
CF
CF
VCC
GND
CLM
EMIT
Note
CURRENT
SENSE
OUT
COLLECT Note
TL431
RCS
+
Note: GND terminal is connected to emitter terminal as M62281FP in IC inside.
And VCC terminal is connected to collector terminal as M62281FP in IC inside.
+
EA
OUT
SOFT
CT (OVP)
CSOFT
R1
DC
output
M62281P/FP
M62281 Application Circuit (Feed-Forward)
RDUTY
Rush current
prevention circuit
Line filter
M62281P/FP
Package Dimensions
JEITA Package Code
P-SOP10-5.7x6.8-1.27
RENESAS Code
PRSP0010DB-A
MASS[Typ.]
0.2g
E
6
*1
HE
10
Previous Code
10P2N-A
F
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
1
A2
5
Index mark
A1
c
*2
Reference
Symbol
A
L
D
*3
e
bp
Detail F
y
D
E
A2
A1
A
bp
c
HE
e
y
L
RENESAS Code
PRDP0014AA-A
Previous Code
14P4
8
1
7
0
0.35
0.18
0°
7.82
1.12
0.3
Nom Max
6.8 6.9
5.7 5.8
1.8
0.1 0.2
2.1
0.4 0.5
0.2 0.25
8°
8.12 8.42
1.27 1.42
0.1
0.5 0.7
MASS[Typ.]
1.0g
c
*1
E
14
Min
6.7
5.6
e1
JEITA Package Code
P-DIP14-6.3x19-2.54
Dimension in Millimeters
D
L
A1
A
A2
*2
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
e
*3
b3
SEATING PLANE
bp
Reference
Symbol
e1
D
E
A
A1
A2
bp
b3
c
e
L
REJ03D0840-0201 Rev.2.01 Nov 14, 2007
Page 12 of 12
Dimension in Millimeters
Min Nom Max
7.32 7.62 7.92
18.8 19.0 19.2
6.15 6.3 6.45
4.5
0.51
3.3
0.4 0.5 0.6
1.4 1.5 1.8
0.22 0.27 0.34
0°
15°
2.29 2.54 2.79
3.0
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