M51996AP/AFP Switching Regulator Control REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Description M51996A is the primary switching regulator controller which is especially designed to get the regulated DC voltage from AC power supply. This IC can directly drive the MOS FET with fast rise and fast fall output pulse and with a large-drive totempole output. Type M51996A has the functions of not only high frequency OSC and fast output drive but also current limit with fast response and high sensibility so the true “fast switching regulator” can be realized. The M51996A is equivalent to the M51978 with externally re-settable OVP (over voltage protection) circuit. Features • • • • • 500kHz operation to MOS FET Output current : ±1 A Output rise time 60 ns, fall time 40 ns Modified totempole output method with small through current Compact and light-weight power supply Small start-up current : 100 µA typ. Big difference between “start-up voltage” and “stop voltage” makes the smoothing capacitor of the power input section small. Start-up threshold 16 V , stop voltage 10 V Packages with high power dissipation are used to with-stand the heat generated by the gate-drive current of MOS FET. 14-pin DIP, 16-pin SOP 1.5W (at 25°C) • Simplified peripheral circuit with protection circuit and built-in large-capacity totempole output High-speed current limiting circuit using pulse-by-pulse method (CLM+pin) Over-voltage protection circuit with an externally re-settable latch (OVP) Protection circuit for output miss action at low supply voltage (UVLO) • High-performance and highly functional power supply Triangular wave oscillator for easy dead time setting SOFT start function by expanding period Application Feed forward regulator, fly-back regulator REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 1 of 35 M51996AP/AFP Recommended Operating Conditions • • • • Supply voltage range: 12 to 30 V Operating frequency: less than 500 kHz Oscillator frequency setting resistance T-ON pin resistance RON: 10 k to 75 kΩ • T-OFF pin resistance ROFF: 2 k to30 kΩ Block Diagram REG (7.8 V) VCC F/B 7.1 V 5.8 V Voltage regulator 15.2 k 3k 1S 500 6S − DET OP AMP Under voltage lockout 1S + 1S 2.5 V OVP Latch PWM Comparator PWM Collector latch VOUT CF T-ON Oscillator (triangle) Emitter Current limit detection T-OFF SOFT REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 2 of 35 CLM+ GND M51996AP/AFP Pin Arrangement M51996AP Collector 1 14 VCC VOUT 2 13 CLM+ Emitter 3 12 GND OVP 4 11 T-OFF F/B 5 10 CF DET 6 9 T-ON REG 7 8 SOFT (Top view) Outline: PRDP0014AA-A (14P4) M51996AFP Collector 1 16 VCC VOUT 2 15 CLM+ Emitter 3 14 GND Heat sink pin 4 13 Heat sink pin OVP 5 12 T-OFF F/B 6 11 CF DET 7 10 T-ON REG 8 9 SOFT (Top view) Outline: PRSP0016DE-A (16P2N-A) Note: Connect the heat sink pin to GND. REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 3 of 35 M51996AP/AFP Absolute Maximum Ratings Item Symbol Ratings Unit 31 31 V V ±1 ±0.15 A IVREG VSOFT −6 VREG + 0.2 mA V CLM+ terminal voltage DET terminal voltage VCLM+ VDET −0.3 to +3 6 V V OVP terminal current F/B terminal current IOVP IFB 10 –10 mA mA T-ON terminal input current T-OFF terminal input current ITON ITOFF –1 –2 mA mA Power dissipation Thermal derating Pd Kθ 1.5 12 W mW/°C Operating temperature Storage temperature Topr Tstg −30 to +85 −40 to +125 °C °C Supply voltage Collector voltage VCC VC Output current IO VREG terminal output current SOFT terminal voltage Condition Peak Continuous Ta = 25°C Ta > 25°C Notes: 1. “+” sign shows the direction of current flowing into the IC and “−” sign shows the current flowing out from the IC. 2. The low impedance voltage supply should not be applied to the OVP terminal. REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 4 of 35 M51996AP/AFP Electrical Characteristics (VCC = 18 V, Ta = 25°C, unless otherwise noted) Block Supply voltage/ circuit current F/B OVP CLM+ Item Symbol Limits Typ. Max. Unit VCC(STOP) — 30 V VCC(START) 15.2 16.2 17.2 V Operation stop voltage VCC(START), VCC(STOP) difference VCC(STOP) ∆VCC 9.0 5.0 9.9 6.3 10.9 7.6 V V Stand-by current ICCL 65 50 100 100 150 200 µA VCC = 14.5 V, Ta = 25°C VCC = 14.5 V, –30 ≤ Ta ≤ 85°C Operating circuit current ICCO 7.3 8 11 12 17 19 mA VCC = 15 V, f = 188 kHz VCC = 30 V, f = 188 kHz Circuit current in OVP state ICCOVP 1.3 140 2.0 210 3.0 320 mA µA VCC = 25 V VCC = 9.5 V Current at 0% duty Current at maximum duty IFBMIND IFBMAXD –2.1 –0.9 –1.5 –0.6 –1.0 –0.4 mA mA F/B terminal input current F/B terminal input current Current difference between max and 0% duty F/B terminal voltage ∆IFB –1.35 –0.99 –0.70 mA ∆IFB = IFBMIND − IFBMAXD VFB 4.9 5.9 7.1 V OVP terminal resistance OVP terminal H threshold voltage RFB 420 600 780 Ω VTHOVPH 540 750 960 mV OVP terminal hysteresis voltage OVP terminal threshold current ∆VTHOVP — 30 — mV ITHOVP 80 150 250 µA OVP terminal input current OVP reset supply voltage IINOVP 80 150 250 µA VOVP = 400 mV VCCOVPC 7.5 9.0 10.0 V OVP terminal is open. (high impedance) Difference supply voltage between operation stop and OVP reset Current from OVP terminal for OVP reset VCC(STOP) − VCCOVPC 0.55 1.20 — V ITHOVPC –480 –320 –213 µA CLM+ terminal threshold voltage VTHCLM+ –210 180 –140 200 –93 220 mV CLM+ terminal current Delay time from CLM+ to VOUT IINCLM+ TPDCLM+ –280 — –200 150 –140 — µA ns Operating supply voltage range Operation start up voltage VCC REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 5 of 35 Min. Test Conditions ∆VCC = VCC(START) − VCC(STOP) F/B terminal input current = 0.95 mA ∆VTHOVP = VTHOVPH − VTHOVPL VCC = 30 V VCC = 18 V VCLM+ = 0 V M51996AP/AFP (VCC = 18 V, Ta = 25°C, unless otherwise noted) Block Oscillator SOFT Min. Limits Typ. Max. Unit Test Conditions Oscillating frequency Maximum ON duty fOSC TDUTY 170 47 188 50 207 53 kHz % RON = 20 kΩ, ROFF = 17 kΩ CF = 220 pF, –5 ≤ Ta ≤ 85°C Upper limit voltage of oscillation waveform Lower limit voltage of oscillation waveform VOSCH 3.97 4.37 4.77 V VOSCL 1.76 1.96 2.16 V Voltage difference between upper limit and lower limit of OSC waveform T-ON terminal voltage ∆VOSC 2.11 2.41 2.71 V VT-ON 3.8 4.5 5.4 V VT-OFF fOSCSOFT 2.9 170 3.5 188 4.2 207 V kHz ROFF = 17 kΩ RON = 20 kΩ, ROFF = 17 kΩ CF = 220 pF 111 131 151 19.0 23.3 27.0 Item T-OFF terminal voltage Oscillating VSOFT = frequency 5.5 V during VSOFT = SOFT 2.5 V operation VSOFT = Symbol RON = 20 kΩ, ROFF = 17 kΩ CF = 220 pF RON = 20 kΩ 0.2 V REG Output SOFT terminal input current SOFT terminal discharging current ISOFTIN –0.5 –0.1 — µA VSOFT = 1 V ISOFDIS 1 3.3 — mA Discharge current of SOFT terminal at VCC less than VCC(STOP) Regulator output voltage Output low voltage VREG 6.8 7.8 8.8 V VOL1 — 0.04 0.4 V VCC = 18 V, IO = 10 mA VOL2 VOL3 — — 0.7 0.85 1.4 1.0 V V VCC = 18 V, IO = 100 mA VCC = 5 V, IO = 1 mA VOL4 VOH1 — 16.0 1.3 16.7 2.0 — V V VCC = 5 V, IO = 100 mA VCC = 18 V, IO = –10 mA VOH2 TRISE 15.5 — 16.5 60 — — V ns VCC = 18 V, IO = –100 mA Output voltage fall time Detection voltage TFALL VDET — 2.4 40 2.5 — 2.6 ns V DET terminal input current Voltage gain of detection amp IINDET — 1.0 3.0 µA GAVDET 30 40 — dB Output high voltage Output voltage rise time Detection REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 6 of 35 VDET = 2.5 V M51996AP/AFP Main Characteristics Thermal Derating (Maximum Rating) Circuit Current vs. Supply Voltage (Normal Operation) 16 m RON = 18 kΩ fOSC = 500 kHz 14 m ROFF = 20 kΩ 1500 Circuit Current ICC (A) Power Dissipation Pd (mW) 1800 1200 900 600 300 fOSC = 100 kHz 150 µ 100 µ Ta = 25 °C Ta = 85 °C Ta = −30 °C 0 0 25 75 85 100 50 125 10 20 30 40 Supply Voltage VCC (V) SOFT Terminal Input Voltage vs. Expansion Rate of Period SOFT Terminal Input Voltage vs. Expansion Rate of Period (fOSC = 100 kHz) (1) RON = 15 kΩ, ROFF = 27 kΩ (2) RON = 18 kΩ, ROFF = 24 kΩ (3) RON = 22 kΩ, ROFF = 22 kΩ (4) RON = 24 kΩ, ROFF = 20 kΩ (5) RON = 22 kΩ, ROFF = 12 kΩ (6) RON = 36 kΩ, ROFF = 6.2 kΩ 4.0 3.0 2.0 (2) 1.0 (1) 2 4 (3) (4) (5) 6 (6) 8 10 12 14 16 18 20 SOFT Terminal Input Voltage VSOFT (V) Ambient Temperature Ta (°C) 5.0 0 0 0 150 5.0 (fOSC = 500 kHz) (1) RON = 15 kΩ, ROFF = 27 kΩ (2) RON = 18 kΩ, ROFF = 24 kΩ (3) RON = 22 kΩ, ROFF = 22 kΩ (4) RON = 24 kΩ, ROFF = 20 kΩ (5) RON = 22 kΩ, ROFF = 12 kΩ (6) RON = 36 kΩ, ROFF = 6.2 kΩ 4.0 3.0 2.0 (2) (3) (4) 1.0 (1) 0 0 2 4 (5) 6 (6) 8 10 12 14 16 18 20 Expansion Rate of Period (Times) Expansion Rate of Period (Times) SOFT Terminal Input Current vs. Input Voltage CLM+ Terminal Threshold Voltage vs. Ambient Temperature −100 Ta = 25 °C Ta = 85 °C Ta = −30 °C −90 −80 −70 −60 −50 −40 −30 −20 −10 0 0 1 2 3 4 5 6 7 8 9 10 SOFT Terminal Input Voltage VSOFT (V) REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 7 of 35 CLM+ Terminal Threshold Voltage VTHCLM+ (mV) SOFT Terminal Input Voltage VSOFT (V) 10 m 50 µ 0 SOFT Terminal Input Current ISOFTIN (nA) 12 m 210 205 200 195 190 −60 −40 −20 0 20 40 60 80 100 Ambient Temperature Ta (°C) REG Output Voltage vs. Ambient Temperature CLM+ Terminal Current vs. CLM+ Terminal Voltage 400 Ta = 25 °C Ta = 85 °C Ta = −30 °C 300 200 100 REG Output Voltage VREG (V) CLM+ Terminal Current IINCLM+ (µA) M51996AP/AFP 8.0 7.5 20 40 60 80 100 CLM+ Terminal Voltage VCLM+ (V) Ambient Temperature Ta (°C) Output High Voltage vs. Source Current Output Low Voltage vs. Sink Current 4.5 VCC = 18 V 4.2 Ta = 25°C 3.9 3.6 3.3 3.0 2.7 2.4 2.1 1.8 1.5 1.2 10−3 3 10−2 Output Low Voltage VOL (V) 5.0 3 10−1 3 100 3 4.5 Ta = 25°C 4.0 3.5 3.0 2.5 VCC = 18 V VCC = 5 V 2.0 1.5 1.0 0.5 0 10−3 101 3 10−2 3 10−1 3 100 3 101 Source Current IOH (A) Sink Current IOL (A) Detection Voltage vs. Ambient Temperature Detection Terminal Input Current vs. Ambient Temperature 2.55 2.50 2.45 2.40 −60 −40 −20 0 20 40 60 80 100 Ambient Temperature Ta (°C) REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 8 of 35 Detection Terminal Input Current IINDET (µA) Output High Voltage VCC-VOH (V) RC = ∞ RC = 3.6 k RC = 1.5 k 7.0 −60 −40 −20 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Detection Voltage VDET (V) 8.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0 −60 −40 −20 0 20 40 60 80 100 Ambient Temperature Ta (°C) Voltage Gain of Detection AMP vs. Frequency ON Duty vs. F/B Terminal Input Current 50 50 40 40 35 30 25 20 15 20 5 0 102 3 103 3 104 3 105 3 0 106 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 Frequency f (Hz) F/B Terminal Input Current IF/B (mA) ON Duty vs. F/B Terminal Input Current ON Duty vs. F/B Terminal Input Current 50 30 20 (fOSC = 500 kHz) RON = 18 kΩ ROFF = 20 kΩ Ta = 25 °C Ta = 85 °C Ta = −30 °C 40 ON Duty (%) (fOSC = 200 kHz) RON = 18 kΩ ROFF = 20 kΩ Ta = 25 °C Ta = 85 °C Ta = −30 °C 40 ON Duty (%) 30 10 10 50 30 20 10 10 0 0 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 F/B Terminal Input Current IF/B (mA) F/B Terminal Input Current IF/B (mA) Upper & Lower Limit Voltage of OSC vs. Ambient Temperature Oscillating Frequency vs. CF Terminal Capacitance RON = 18 kΩ 5.2 ROFF = 20 kΩ 4.8 4.4 fOSC = 500 kHz fOSC = 200 kHz fOSC = 100 kHz 4.0 fOSC = 100 kHz fOSC = 200 kHz fOSC = 500 kHz 2.2 2.0 1.8 −60 −40 −20 0 20 40 60 80 100 Ambient Temperature Ta (°C) REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 9 of 35 Oscillating Frequency fOSC (kHz) Upper & Lower Limit Voltage of OSC VOSCH, VOSCL (V) (fOSC = 100 kHz) RON = 18 kΩ ROFF = 20 kΩ Ta = 25 °C Ta = 85 °C Ta = −30 °C 45 ON Duty (%) Voltage Gain of Detection AMP GDET (dB) M51996AP/AFP 104 3 103 3 102 3 RON = 22 kΩ ROFF = 12 kΩ RON = 36 kΩ ROFF = 6.2 kΩ 101 RON = 24 kΩ ROFF = 20 kΩ 3 100 0 10 3 101 3 102 3 103 3 CF Terminal Capacitance (pF) 104 M51996AP/AFP Oscillator Frequency vs. Ambient Temperature ON Duty vs. ROFF 100 ON Duty (%) 80 RON = 75 kΩ 70 60 51 kΩ 50 36 kΩ 24 kΩ 22 kΩ 18 kΩ 15 kΩ 10 kΩ 40 30 20 10 0 100 3 5 7 101 3 100 90 80 −60 −40 −20 5 7 102 20 40 60 80 100 ON Duty vs. Ambient Temperature 100 RON = 24 kΩ ROFF = 20 kΩ CF = 47 pF 400 80 300 40 60 RON = 22 kΩ, ROFF = 12 kΩ 60 RON = 24 kΩ, ROFF = 20 kΩ 50 40 30 10 20 RON = 36 kΩ, ROFF = 6.2 kΩ 70 20 0 (fOSC = 100 kHz) 90 ON Duty (%) 500 RON = 22 kΩ, ROFF = 22 kΩ RON = 18 kΩ, ROFF = 24 kΩ RON = 15 kΩ, ROFF = 27 kΩ 0 −60 −40 −20 80 100 0 20 40 60 80 100 Ambient Temperature Ta (°C) Ambient Temperature Ta (°C) ON Duty vs. Ambient Temperature ON Duty vs. Ambient Temperature 100 100 (fOSC = 200 kHz) 90 80 80 RON = 24 kΩ, ROFF = 20 kΩ 50 40 30 RON = 22 kΩ, ROFF = 22 kΩ 0 20 40 60 80 100 Ambient Temperature Ta (°C) REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 10 of 35 RON = 22 kΩ, ROFF = 12 kΩ 60 RON = 24 kΩ, ROFF = 20 kΩ 50 40 30 10 RON = 15 kΩ, ROFF = 27 kΩ RON = 36 kΩ, ROFF = 6.2 kΩ 70 20 RON = 18 kΩ, ROFF = 24 kΩ 0 −60 −40 −20 ON Duty (%) RON = 22 kΩ, ROFF = 12 kΩ 60 (fOSC = 500 kHz) 90 RON = 36 kΩ, ROFF = 6.2 kΩ 70 10 0 Oscillator Frequency vs. Ambient Temperature 200 −60 −40 −20 ON Duty (%) 110 Ambient Temperature Ta (°C) 600 20 RON = 24 kΩ ROFF = 20 kΩ CF = 330 pF ROFF (kΩ) 700 Oscillator Frequency fOSC (kHz) Oscillator Frequency fOSC (kHz) 120 90 RON = 22 kΩ, ROFF = 22 kΩ RON = 18 kΩ, ROFF = 24 kΩ RON = 15 kΩ, ROFF = 27 kΩ 0 −60 −40 −20 0 20 40 60 80 100 Ambient Temperature Ta (°C) OVP Terminal Threshold Voltage vs. Ambient Temperature OVP Terminal Input Current vs. Input Voltage 1m 1.1 Ta = 25 °C Ta = 85 °C Ta = −30 °C OVP Terminal Threshold Voltage VTHOVP (V) OVP Terminal Input Current IOVP (A) M51996AP/AFP 100 µ 10 µ 1µ 0.9 0.4 0.6 0.8 H threshold voltage (VTHOVPH) 0.8 0.7 0.6 L threshold voltage (VTHOVPL) 0.5 0.4 0.3 0.2 VCC = 18 V 1.0 1.0 −40 −20 Circuit Current ICC (mA) 8.0 OVP reset point 8.87 V (−30 °C) 8.94 V (25 °C) 9.23 V (85 °C) 7.0 6.0 Ta = 25 °C Ta = 85 °C Ta = −30 °C 5.0 4.0 3.0 2.0 1.0 0 0 10 20 30 40 Supply Voltage VCC (V) Current from OVP Terminal for OVP Reset ITHOVPC (µA) OVP Terminal Input Voltage VOVP (V) Circuit Current vs. Supply Voltage (OVP Operation) 0 20 40 60 80 100 Ambient Temperature Ta (°C) Current from OVP Terminal for OVP Reset vs. Supply Voltage 800 Ta = 25 °C Ta = 85 °C Ta = −30 °C 700 600 500 400 300 200 100 0 0 5 10 15 20 25 30 35 40 Supply Voltage VCC (V) Output Through Current Waveform at Rising Edge of Output Pulse Output Through Current Waveform at Falling Edge of Output Pulse Horizontal-axis: 20 ns/div Vertical-axis: 50 mA/div Horizontal-axis: 20 ns/div Vertical-axis: 5 mA/div REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 11 of 35 M51996AP/AFP Application Example Rush current prevention circuit (1) Application Example for Feed Forward Regulator + R1 VCC Collector VOUT AC input Line filter REG R CLM+ + CFIN DC output + R2 Emitter M51996A CVCC GND SOFT DET OVP F/B T-ON CF T-OFF + RON CF ROFF Feedback OVP (TL431) Rush current prevention circuit (2) Application Example for Fly-back Regulator + R1 R21 RFB CFB VCC Collector VOUT AC input Line filter F/B + CLM+ DET + REG CFIN CVCC R22 M51996A Emitter R RNF GND SOFT OVP T-ON CF T-OFF CNF RON REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 12 of 35 CF ROFF RCLM DC output M51996AP/AFP Function Description Type M51996AP and M51996AFP are especially designed for off-line primary PWM control IC of switching mode power supply to get DC voltage from AC power supply. Using this IC, smart SMPS can be realized with reasonable cost and compact size as the number of external electric parts can be reduced and also parts can be replaced by reasonable one. In the following circuit diagram, MOS FET is used for output transistor, however bipolar transistor can be replaced with no problem. Start-up Circuit Section The start-up current is such low current level as typical 100 µA, as shown in figure 1, when the VCC voltage is increased from low level to start-up voltage VCC(START). Circuit Current ICC (mA) In this voltage range, only a few parts in this IC, which has the function to make the output voltage low level, is alive and ICC current is used to keep output low level. The large voltage difference between VCC(START) and VCC(STOP) makes start-up easy, because it takes rather long duration from VCC(START) to VCC(STOP). ICCO ≈ 11 mA ICCL ≈ 100 µA VCC VCC (STOP) (START) ≈ 9.9 V ≈ 16.2 V Supply Voltage VCC (V) Figure 1 Circuit Current vs. Supply Voltage REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 13 of 35 M51996AP/AFP Oscillator Section The oscillation waveform is the triangle one. The ON-duration of output pulse depends on the rising duration of the triangle waveform and dead-time is decided by the falling duration. The rising duration is determined by the product of external resistor RON and capacitor CF and the falling duration is mainly determined by the product of resistor ROFF and capacitor CF. Waveform of CF terminal VOSCH ≈ 4.4 V VOSCL ≈ 2.0 V Waveform of VOUT terminal in Max ON duty condition VOH VOL Figure 2 OSC. Waveform at Normal Condition (no-operation of intermittent action and OSC control circuit) 1. Oscillator operation when SOFT circuit does not operate Figure 3 shows the equivalent charging and discharging circuit diagram of oscillator. The current flows through RON from the constant voltage source of 5.8 V. CF is charged up by the same amplitude as RON current, when internal switch SW1, SW2 is switched to “charging side”. The rise rate of CF terminal is given as ≈ VT-ON RON × CF (V/s) ………………………………………… (1) where VT-ON ≈ 4.5 V The maximum on duration is approximately given as ≈ (VOSCH − VOSCL) × RON × CF (s) ………………… (2) VT-ON where VOSCH ≈ 4.4 V VOSCL ≈ 2.0 V CF is discharged by the summed-up of ROFF current and one sixteenth (1/16) of RON current by the function of Q2, Q3 and Q4 when SW1, SW2 are switched to “discharge side”. So fall rate of CF terminal is given as ≈ VT-OFF ROFF × CF + VT-ON 16 × RON × CF (V/s) ………………… (3) The minimum off duration approximately is given as ≈ (VOSCH − VOSCL) × CF VT-OFF ROFF + VT-ON (s) …………………… (4) 16 × RON The cycle time of oscillation is given by the summation of equations 2 and 4. The frequency including the dead-time is not influenced by the temperature because of the built-in temperature compensating circuit. REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 14 of 35 M51996AP/AFP 5.8 V Q4 1/16 T-ON Q1 Charging SW1 Q3 RON T-OFF From VF signal Vz = 4.2 V ROFF SW2 CF Switched by charging and discharging signal CF Q2 Discharging M51996A Figure 3 Schematic Diagram of Charging and Discharging Control Circuit for OSC Capacitor CF 2. Oscillator operation when the SOFT (soft start) circuit is operating. Output transistor is protected from rush current by CLM function at the start time of power on. SOFT terminal is used to improve the rising response of the output voltage of power supply (prevention of overshooting). The ON duration of output is kept constant, and the OFF duration is extended as the SOFT terminal voltage becomes lower by the soft start circuit of this IC. The maximum value of extension is set internally at approximately sixteen times of the maximum ON duration. The features of this method are as follows : (1) It is ideal for primary control as IC driving current is supplied from the third winding of the main transformer at the start-up because constant ON duration is obtained from start-up. (2) It is possible to get a wide dynamic range for ON/OFF ratio by pulse-by-pulse current limit circuit. (3) The response characteristics at power-on is not affected by input voltage as the pulse-by-pulse limit current value is not affected by the input voltage. Figure 4 shows the circuit diagram of the soft start. If SOFT terminal voltage is low, T-OFF terminal voltage becomes low and VT-OFF in equations (3) and (4) become low. To REG Terminal To REG Terminal RSOFT SOFT terminal CSOFT T-OFF terminal Vz ≈ 4.2 V GND terminal Discharging transistor Note IC's internal circuit Note: Active when operation stops. Figure 4 Circuit Diagram of SOFT Terminal Section and T-OFF Terminal Section REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 15 of 35 M51996AP/AFP VOSCH ≈ 4.4 V Waveform of CF terminal VOSCL ≈ 2.0 V t Waveform of VOUT terminal in Max ON duty condition VOH VOL t Figure 5 Oscillator Waveform When the SOFT Circuit is Operating Start from 0 V VOSCH Voltage waveform of CF Terminal VOSCL 0 t The first output pulse VOH Waveform of VOUT terminal in Max ON duty condition No output pulse VOL 0 t Operation start Figure 6 Relationship Between Oscillator Waveform and Output Waveform at Start-up Figure 5 shows the relationship between oscillator waveform and output pulse. If the SOFT terminal voltage is VSOFT, the rise rate of CF terminal given as ≈ VT-ON RON × CF (V/s) ………………………………………… (5) The fall rate of oscillation waveform is given as ≈ VSOFT − VBE ROFF × CF + VT-ON 16 × RON × CF (V/s) ………………… (6) Where VSOFT ; SOFT terminal applied voltage VBE ≈ 0.65 V If VSOFT − VBE < 0, VSOFT − VBE = 0 If VSOFT − VBE > VT-OFF (≈ 3.5 V), VSOFT − VBE = VT-OFF REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 16 of 35 M51996AP/AFP PWM Comparator, PWM Latch and Current Limit Latch Section Figure 7 shows the schematic diagram of PWM comparator and PWM latch section. The on-duration of output waveform coincides with the rising duration of CF terminal waveform, when the no output current flows from F/B terminal. When the F/B terminal has finite impedance and current flows out from F/B terminal, “A” point potential shown in figure 7 depends on this current. So the “A” point potential is close to GND level when the flow-out current becomes large. “A” point potential is compared with the CF terminal oscillator waveform and PWM comparator, and the latch circuit is set when the potential of oscillator waveform is higher than “A” point potential. The latch circuit is reset during the dead-time of oscillation (falling duration of oscillation current). So the “B” point potential or output waveform of latch circuit is the one shown in figure 8. The final output waveform or “C” point potential is got by combining the “B” point signal and dead-time signal logically. (please refer to figure 8) ≈ 7.1 V 6S 15.2 k 3k 500 Ω 5.8 V 200 µA Point A − + 1S PWM COMP. F/B Latch current CF To output *1 Point C Point D M51996A Point B *2 From OSC CLM+ Notes: 1. Resistor to determine current limit sensitivety 2. High level during dead time Figure 7 PWM Comparator PWM Latch and Current Limit Latch Section OSC waveform Waveform at point A Waveform of OSC & point A Point B Point C Figure 8 Waveforms of PWM Comparator Input Point A, Latch Circuit Points B and C REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 17 of 35 M51996AP/AFP When the current-limit signal is applied before the crossing instant of “A” pint potential and CF terminal voltage shown in figure 7, this signal makes the output “off” and the off state will continue until next cycle. Figure 9 shows the timing relation among them. If the current limiting circuit is set, no waveform is generated at output terminal, however this state is reset during the succeeding dead-time. So this current limiting circuit is able to have the function in every cycle, and is named “pulse-by-pulse current limit”. There happen some noise voltage on RCLM during the switching of power transistor due to the snubber circuit and stray capacitor of the transformer windings. OSC waveform of CF terminal VTHCLM ≈ 200 mV Waveform of CLM+ terminal Current limit signal to set latch Waveform of VOUT terminal Figure 9 Operating Waveform of Current Limiting Circuit To eliminate the abnormal operation by the noise voltage, the low pass filter, which consists of RNF and CNF is used as shown in figure 10. It is recommended to use 10 to 100 Ω for RNF because such range of RNF is not influenced by the flow-out current of some 200 µA from CLM+ terminal and CNF is designed to have the enough value to absorb the noise voltage. M51996A VOUT Point D RNF CLM+ CNF RCLM+ GND Figure 10 Connection Diagram of Current Limit Circuit REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 18 of 35 M51996AP/AFP Voltage Detector Circuit (DET) Section The DET terminal can be used to control the output voltage which is determined by the winding ratio of fly back transformer in fly-back system or in case of common ground circuit of primary and secondary in feed forward system. The circuit diagram is quite similar to that of shunt regulator type 431 as shown in figure 11. As well known from figure 11 and figure 12, the output of OP AMP has the current-sink ability, when the DET terminal voltage is higher than 2.5 V. But it becomes high impedance state when lower than 2.5 V DET terminal and F/B terminal have inverting phase characteristics each other, so it is recommended to connect the resistor and capacitor in series between them for phase compensation. It is very important one can not connect by resistor directly as there is the voltage difference between them and the capacitor has the DC stopper function. ≈ 7.1 V 500 Ω 3k 1S 6S F/B DET 5.4 k 10.8 k 10.8 k 10 S 1.2 k Figure 11 Voltage Detector Circuit Section (DET) ≈ 7.1 V 3k 1S 500 Ω 6S F/B OP AMP − DET + 2.5 V Figure 12 Schematic Diagram of Voltage Detector Circuit Section (DET) REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 19 of 35 M51996AP/AFP OVP Circuit (Over Voltage Protection Circuit) Section OVP circuit is basically positive feedback circuit constructed by Q2, Q3 as shown in figure 13. Q2, Q3 turn on and the circuit operation of IC stops, when the input signal is applied to OVP terminal. (threshold voltage ≈ 750 mV) The current value of I2 is about 150µA when the OVP does not operates but it decreases to about 2 µA when OVP operates. It is necessary to input the sufficient larger current (800 µA to 8 mA) than I2 for triggering the OVP operation. The reason to decrease I2 is that it is necessary that ICC at the OVP rest supply voltage is small. It is necessary that OVP state holds by circuit current from R1 in the application example, so this IC has the characteristic of small ICC at the OVP reset supply voltage (≈ stand-by current + 20 µA) On the other hand, the circuit current is large in the higher supply voltage, so the supply voltage of this IC doesn’t become so high by the voltage drop across R1. This characteristic is shown in figure 14. The OVP terminal input current in the voltage lower than the OVP threshold voltage is based on I2 and the input current in the voltage higher than the OVP threshold voltage is the sum of the current flowing to the base of Q3 and the current flowing from the collector of Q2 to the base. For holding in the latch state, it is necessary that the OVP terminal voltage is kept in the voltage higher than VBE of Q3. So if the capacitor is connected between the OVP terminal and GND, even though Q2 turns on in a moment by the surge voltage, etc, this latch action does not hold if the OVP terminal voltage does not become higher than VBE of Q3 by charging this capacitor. For resetting OVP state, it is necessary to make the OVP terminal voltage lower than the OVP L threshold voltage or make VCC lower than the OVP reset supply voltage. As the OVP reset voltage is settled on the rather high voltage of 9.0 V, SMPS can be reset in rather short time from the switch-off of the AC power source if the smoothing capacitor is not so large value. VCC 7.8 V 100 µA 8k I1 12 k Q1 Q2 400 OVP Q3 2.5 k GND I2 Note: I1 = 0 when OVP operates Figure 13 Detail Diagram of OVP Circuit REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 20 of 35 M51996AP/AFP Circuit Current ICC (mA) 8 OVP reset point 7 8.87 V (−30 °C) 8.94 V (25 °C) 6 9.23 V (85 °C) Ta = 25 °C Ta = 85 °C Ta = −30 °C 5 4 3 2 1 0 0 5 10 15 20 25 30 35 40 Supply Voltage VCC (V) Figure 14 Circuit Current vs. Supply Voltage (OVP Operation) Output Section It is required that the output circuit have the high sink and source abilities for MOS FET drive. It is well known that the “totempole circuit has high sink and source ability. However, it has the demerit of high through current. For example, the through current may reach such the high current level of 1 A, if type M51996A has the “conventional” totempole circuit. For the high frequency application such as higher than 100 kHz, this through current is very important factor and will cause not only the large ICC current and the inevitable heat-up of IC but also the noise voltage. This IC uses the improved totempole circuit, so without deteriorating the characteristic of operating speed, its through current is approximately 100 mA. REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 21 of 35 M51996AP/AFP Application Note of Type M51996AP/AFP Design of Start-up Circuit and The Power Supply of IC 1. The start-up circuit when it is not necessary to set the start and stop input voltage Rectified DC voltage from smoothing capacitor Main transformer R1 VF VCC Third winding of bias winding + M51996A CVCC GND Figure 15 Start-up Circuit Diagram When it is Not Necessary to Set The Start and Stop Input Voltage Figure 15 shows one of the example circuit diagram of the start-up circuit which is used when it is not necessary to set the start and stop voltage. It is recommended that the current more than 300 µA flows through R1 in order to overcome the operation start-up current ICC(START) and CVCC is in the range of 10 to 47 µF. The product of R1 by CVCC causes the time delay of operation, so the response time will be long if the product is too much large. Just after the start-up, the ICC current is supplied from CVCC, however, under the steady state condition, IC will be supplied from the third winding or bias winding of transformer, the winding ratio of the third winding must be designed so that the induced voltage may be higher than the operation-stop voltage VCC(STOP). The VCC voltage is recommended to be 12 V to 17 V as the normal and optimum gate voltage is 10 to 15 V and the output voltage (VOH) of type M51996AP/AFP is about (VCC − 2 V). It is not necessary that the induced voltage is settled higher than the operation start-up voltage VCC(START), and the high gate drive voltage causes high gate dissipation, on the other hand, too low gate drive voltage does not make the MOS FET fully on-state or the saturation state. 2. The start-up circuit when it is not necessary to set the start and stop input voltage It is recommend to use the third winding of “forward winding” or “positive polarity” as shown in figure 16, when the DC source voltages at both the IC operation start and stop must be settled at the specified values. The input voltage (VIN(START)), at which the IC operation starts, is decided by R1 and R2 utilizing the low start-up current characteristics of type M51996AP/AFP. The input voltage (VIN(STOP)), at which the IC operation stops, is decided by the ratio of third winding of transformer. The VIN(START) and VIN(STOP) are given by following equations. VIN (START) ≈ R1 × ICCL + ( R1 + 1) × VCC (START) ……… (7) R2 VIN (STOP) ≈ (VCC (STOP) − VF) × NP 1 + V'IN RIP (P-P) …… (8) NB 2 Where ICCL is the operation start-up current of IC VCC(START) is the operation start-up voltage of IC VCC(STOP) is the operation stop voltage of IC VF is the forward voltage of rectifier diode V’IN(P-P) is the peak to peak ripple voltage of VCC terminal ≈ NB V'IN RIP (P-P) NP It is required that the VIN(START) must be higher than VIN(STOP). REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 22 of 35 M51996AP/AFP When the third winding is the “fly back winding” or “reverse polarity”, the VIN(START) can be fixed, however, VIN(STOP) can not be settled by this system, so the auxiliary circuit is required. Rectified DC voltage from smoothing capacitor VIN NP R1 VF VCC NB M51996A R2 Primary winding of transformer Third winding of transformer + CVCC GND Figure 16 Start-up Circuit Diagram When It is Not Necessary to Set The Start and Stop Input Voltage 3. Notice to the VCC, VCC line and GND line Collector Main transformer third winding VCC M51996A + CVCC Output RCLM Emitter GND Figure 17 How to Design The Conductor-pattern of Type M51996A on PC Board (schematic example) To avoid the abnormal IC operation, it is recommended to design the VCC is not vary abruptly and has few spike voltage, which is induced from the stray capacity between the winding of main transformer. To reduce the spike voltage, the CVCC, which is connected between VCC and ground, must have the good high frequency characteristics. To design the conductor-pattern on PC board, following cautions must be considered as shown in figure 17. (1) To separate the emitter line of type M51996A from the GND line of the IC (2) The locate the CVCC as near as possible to type M51996A and connect directly (3) To separate the collector line of type M51996A from the VCC line of the IC (4) To connect the ground terminals of peripheral parts of ICs to GND of type M51996A as short as possible REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 23 of 35 M51996AP/AFP 4. Power supply circuit for easy start-up When IC start to operate, the voltage of the CVCC begins to decrease till the CVCC becomes to be charged from the third winding of main-transformer as the ICC of the IC increases abruptly. In case shown in figure 15 and 16, some “unstable start-up” or “fall to start-up” may happen, as the charging interval of CVCC is very short duration; that is the charging does occur only the duration while the induced winding voltage is higher than the CVCC voltage, if the induced winding voltage is nearly equal to the “operation-stop voltage” of type M51996A. It is recommended to use the 10 to 47 µF for CVCC1, and about 5 times capacity bigger than CVCC1 for CVCC2. R1 Main transformer third winding VCC + M51996A CVCC1 + CVCC2 GND Figure 18 DC Source Circuit for Stable Start-up REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 24 of 35 M51996AP/AFP OVP Circuit 1. To avoid the miss operation of OVP It is recommended to connect the capacitor between OVP terminal and GND for avoiding the miss operation by the spike noise. The OVP terminal is connected with the sink current source (≈ 150 µA) in IC when OVP does not operate, for absorbing the leak current of the photo coupler in the application. So the resistance between the OVP terminal and GND for leak-cut is not necessary. If the resistance is connected, the supply current at the OVP reset supply voltage becomes large. As the result, the OVP reset supply voltage may become higher than the operation stop voltage. In that case, the OVP action is reset when the OVP is triggered at the supply voltage a little high than the operation stop voltage. So it should be avoided absolutely to connect the resistance between the OVP terminal and GND. To REG or VCC 5.6 k VCC M51996A Photo coupler OVP + GND Figure 19 Peripheral Circuit of OVP Terminal 2. Application circuit to make the OVP-reset time fast The reset time may becomes problem when the discharge time constant of CFIN • (R1 + R2) is long. Under such the circuit condition, it is recommend to discharge the CVCC forcedly and to make the VCC low value; This makes the OVP-reset time fast. To main transformer R1 + + CFIN CVCC R2 VCC M51996A GND The time constant of this part should be short Figure 20 Example Circuit Diagram to Make The OVP-reset-time Fast REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 25 of 35 M51996AP/AFP 3. OVP setting method using the induced third winding voltage on fly back system For the over voltage protection (OVP), the induced fly back type third winding voltage can be utilized, as the induced third winding voltage depends on the output voltage. Figure 21 shows one of the example circuit diagram. Main transformer third winding VCC OVP M51996A 470 Ω + CVCC GND Figure 21 OVP Setting Method Using The Induced Third Winding Voltage on Fly Back System 4. Method to control for ON/OFF using the OVP terminal You can reset OVP to lower the OVP terminal voltage lower than VTHOVPL. So you can control for ON/OFF using this nature. The application is shown in figure 22. The circuit turns off by SW OFF and turns on by SW ON in this application. Of course you can make use of the transistor or photo-transistor instead of SW. REG M51996A 5.1 k ON/OFF SW Figure 22 Method to Control for ON/OFF Using The OVP Terminal REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 26 of 35 M51996AP/AFP Current Limiting Circuit 1. Peripheral circuit of CLM+ terminal Figure 23 shows the example circuit diagrams around the CLM+ terminal. It is required to connect the low pass filter, in order to reduce the spike current component, as the main current or drain current contains the spike current especially during the turn-on duration of MOS FET. 1,000 pF to 22,000 pF is recommended for CNF and the RNF1 and RNF2 have the function both to adjust the “currentdetecting-sensitivity” and to consist the low pass filter. To design the RNF1 and RNF2, it is required to consider the influence of CLM+ terminal source current (IINCLM+), which value is in the range of 90 to 270 µA. In order to be not influenced from these resistor paralleled value of RNF1 and RNF2, (RNF1//RNF2) is recommended to be less than 100 Ω. The RCLM should be the non-inductive resistor. CFIN R1 + Input smoothing capacitor VCC Collector VOUT + CVCC M51996A GND RNF1 CLM+ Emitter CNF RNF2 RCLM Figure 23 Peripheral Circuit Diagram of CLM+ Terminal 2. Over current limiting curve (1) In case of feed forward system I2 IP1 I1 IP2 CLM I2 I1 RCLM (a) Feed forward system (b) Primary and secondary current Figure 24 Primary and Secondary Current Waveforms Under The Current Limiting Operation Condition on Feed Forward System Figure 24 shows the primary and secondary current wave-forms under the current limiting operation. At the typical application of pulse by pulse primary current detecting circuit, the secondary current depends on the primary current. As the peak value of secondary current is limited to specified value, the characteristics curve of output voltage versus output current become to the one as shown in figure 25. The demerit of the pulse by pulse current limiting system is that the output pulse width can not reduce to less than some value because of the delay time of low pass filter connected to the CLM+ terminal and propagation delay time TPDCLM from CLM+ terminal to output terminal of type M51996A. The typical TPDCLM+ is 100 ns. As the frequency becomes higher, the delay time must be shorter. And as the secondary output voltage becomes higher, the dynamic range of on-duty must be wider; it means that it is required to make the on-duration much more narrower. So this system has the demerit at the higher oscillating frequency and higher output voltage applications. To prevent that the SOFT terminal is used to lower the frequency when the curve starts to become vertical. REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 27 of 35 Output Voltage M51996AP/AFP Output Current Figure 25 Over Current Limiting Curve on Feed Forward System If the curve becomes vertical because of an excess current, the output voltage is lowered and no feedback current flows from feedback photo-coupler; the PWM comparator operates to enlarge the duty sufficiently, but the signal from the CLM+ section operates to make the pulse width narrower. Under the condition in which I2 in figure 24 does not become 0, the output voltage is proportional to the product of the input voltage VIN (primary side voltage of the main transformer) and on duty. If the bias winding is positive, VCC is approximately proportional to VIN. The existence of feed back current of the photo-coupler is known by measuring the F/B terminal voltage which becomes less than 2VBE in the internal circuit of REG terminal and F/B terminal if the output current flows from the F/B terminal. REG 3k 1S 500 6S F/B M51996A Figure 26 Relationship Between REG Terminal and F/B Terminal Figure 27 shows an application example. Q1 is turned on when normal output voltage is controlled at a certain value. The SOFT terminal is clamped to a high-level voltage. If the output voltage decreases and the curve starts to drop, no feed back current flows, Q1 is turned off and the SOFT terminal responds to the smoothed output voltage. It is recommended to use an R1 and R2 of 10 kΩ to 30 kΩ. An R3 of 20 to 100 kΩ and C of 1000 pF to 8200 pF should be used. REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 28 of 35 M51996AP/AFP D2 VCC Bias winding of the main transformer + Collector CVCC VOUT M51996A To output transistor R3 SOFT C F/B REG R1 R2 D1 Q1 Photo-coupler for feed back signal Figure 27 Current to Lower Frequency During Over Current To change the knee point of frequency drop, use the circuit in figure 28. SOFT VOUT SOFT VOUT VOUT SOFT To make the knee point low To make the knee point high Figure 28 Method to Control The Knee Point of Frequency Drop To have a normal SOFT start function in the circuit in figure 27, use the circuit in figure 29. It is recommended to use an R4 of 10 kΩ. D2 VCC Bias winding of the main transformer + CVCC Collector VOUT M51996A SOFT R4 R3 To output transistor C F/B REG RSOFT R1 Q2 CSOFT R2 + Q1 D1 Photo-coupler for feed back signal Figure 29 Circuit to Use Frequency Drop During The Over Current and Normal Soft Start REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 29 of 35 M51996AP/AFP DC Output Voltage (2) In case of fly back system The DC output voltage of SMPS depends on the VCC voltage of type M51996A when the polarity of the third winding is negative and the system is fly back. So the operation of type M51996A will stop when the VCC becomes lower than “Operation-stop voltage” of M51996A when the DC output voltage of SMPS decreases under specified value at over load condition. Point that VCC voltage or third winding voltage decreases under "Operation-stop voltage" DC Output Current Figure 30 Over Current Limiting Curve on Fly Back System VCC Collector R3 SOFT M51996A + CVCC R4 F/B REG R1 R2 To photo-coupler for feed back signal Figure 31 Current to Lower The Frequency During The Over Current in The Fly Back System However, the M51996A will non-operate and operate intermittently, as the VCC voltage rises in accordance with the decrease of ICC current. The fly back system has the constant output power characteristics as shown in figure 30 when the peak primary current and the operating frequency are constant. To avoid an increases of the output current, the frequency is lowered when the DC output voltage of SMPS starts to drop using the SOFT terminal. VCC is divided and is input to the SOFT terminal as shown in figure 31, because the voltage in proportional to the output voltage is obtained from the bias winding. In this application example, the current flowing to R3 added to the start-up current. So please use high resistance or 100 kΩ to 200 kΩ for R3. The start-up current is not affected by R3 if R3 is connected to CVCC2 in the circuit shown in figure 18. REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 30 of 35 M51996AP/AFP Output Circuit 1. The output terminal characteristics at the VCC voltage lower than the “Operation-stop” voltage The output terminal has the current sink ability even though the VCC voltage lower than the “Operation-stop” voltage or VCC(STOP) (It means that the terminal is “Output low state” and please refer characteristics of output low voltage versus sink current.) This characteristics has the merit not to damage the MOS FET at the stop of operation when the VCC voltage decreases lower than the voltage of VCC(STOP), as the gate charge of MOS FET, which shows the capacitive load characteristics to the output terminal, is drawn out rapidly. The output terminal has the draw-out ability above the VCC voltage of 2 V, however, lower than the 2V, it loses the ability and the output terminal potential may rise due to the leakage current. In this case, it is recommended to connect the resistor of 100 kΩ between gate and source of MOS FET as shown in figure 32. To main transformer VOUT M51996A 100 kΩ RCLM Figure 32 Circuit Diagram to Prevent The MOS-FET Gate potential Rising 2. MOS FET gate drive power dissipation Figure 33 shows the relation between the applied gate voltage and the stored gate charge. In the region 1, the charge is mainly stored at CGS as the depletion is spread and CGD is small owing to the off-state of MOS FET and the high drain voltage. In the region 2, the CGD is multiplied by the “mirror effect” as the characteristics of MOS FET transfers from offstate to on-state. In the region 3, both the CGD and CGS affect to the characteristics as the MOS FET is on-state and the drain voltage is low. Gate-source Voltage VGS (V) 20 Drain ID VDS = 80 V 200 V 320 V 15 10 CGD (3) Gate CDS (2) VD CGS 5 (1) VGS ID = 4 A Source 0 0 4 8 12 16 20 Total Stored Gate Charge QGSH (nC) Figure 33 The Relation Between Applied Gate-source Voltage and Stored Gate Charge The charging and discharging current caused by this gate charge makes the gate power dissipation. The relation between gate drive current ID and total gate charge QGSH is shown by following equation; ID = QGSH • fOSC ……………………………………………… (9) Where fOSC is switching frequency REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 31 of 35 M51996AP/AFP As the gate drive current may reach up to several tenths milliamperes at 500 kHz operation, depending on the size of MOS FET, the power dissipation caused by the gate current can not be neglected. In this case, following action will be considered to avoid heat up of type M51996A. (1) To attach the heat sink to type M51996A (2) To use the printed circuit board with the good thermal conductivity (3) To use the buffer circuit shown next section 3. Output buffer circuit It is recommended to use the output buffer circuit as shown in figure 34, when type M51996A drives the large capacitive load or bipolar transistor. VOUT M51996A Figure 34 Output Buffer Circuit Diagram DET Circuit Figure 35 shows how to use the DET circuit for the voltage detector and error amplifier. For the phase shift compensation, it is recommended to connected the CR network between DET terminal and F/B terminal. A C Detecting voltage C1 R1 F/B C2 M51996A R3 DET B R2 C4 Figure 35 How to Use The DET Circuit for The Voltage Detector Log G (dB) Figure 36 shows the gain-frequency characteristics between point B and point C shown in figure 35. GAVDET (DC voltage gain) G1 Log ω ω1 ω2 Figure 36 Gain-frequency Characteristics Between Point B and C Shown in Figure 35 The G1, ω1 and ω2 are given by following equations; G1 = R3 ……………………… (10) R1 / R2 ω1 = 1 ………………………… (11) C2 • R3 ω2 = C1 + C2 C1 • C2 • R3 ………………… (12) REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 32 of 35 M51996AP/AFP At the start of the operation, there happen to be no output pulse due to F/B terminal current through C1 and C2, as the potential of F/B terminal rises sharply just after the start of the operation. Not to lack the output pulse, is recommended to connect the capacitor C4 as shown by broken line. Please take notice that the current flows through the R1 and R2 are superposed to ICC(START). Not to superpose, R1 is connected to CVCC2 as shown in figure 18. How to Get The Narrow Pulse Width During The Start of Operation Figure 37 shows how to get the narrow pulse width during the start of the operation. If the pulse train of forcedly narrowed pulse-width continues too long, the misstart of operation may happen, so it is recommended to make the output pulse width narrow only for a few pulse at the start of operation. 0.1 µF is recommended for the C. F/B M51996A 100 Ω To photo coupler C Figure 37 How to Get The Narrow Pulse Width During The Start of Operation How to Synchronize with External Circuit Type M51996A has no function to synchronize with external circuit, however, there is some application circuit for synchronization as shown in figure 38. M51996A T-ON RON CF CF T-OFF ROFF Q1 Synchronous pulse Oscillating waveform 0V Synchronize waveform 0V Minimum pulse width of synchronous pulse Maximum pulse width of synchronous pulse Figure 38 How to Synchronize With External Circuit REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 33 of 35 M51996AP/AFP Driver Circuit for Bipolar Transistor When the bipolar transistor is used instead of MOS FET, the base current of bipolar transistor must be sinked by the negative base voltage source for the switching-off duration, in order to make the switching speed of bipolar transistor fast one. In this case, over current can not be detected by detecting resistor in series to bipolar transistor, so it is recommended to use the CT (current transformer). VCC VCC Collector VOUT M51996A −VSS (−2 V to −5 V) GND Emitter Figure 39 Driver Circuit Diagram (1) for Bipolar Transistor For the low current rating transistor, type M51996A can drive it directly as shown in figure 40. VCC Collector VOUT Bipolar transistor M51996A GND Emitter Figure 40 Driver Circuit Diagram (2) for Bipolar Transistor Attention for Heat Generation The maximum ambient temperature of type M51996A is +85°C, however the ambient temperature in vicinity of the IC is not uniform and varies place by place, as the amount of power dissipation is fearfully large and the power dissipation is generated locally in the switching regulator. So it is one of the good idea to check the IC package temperature. The temperature difference between IC junction and the surface of IC package is 15°C or less, when the IC junction temperature is measured by temperature dependency of forward voltage of pin junction, and IC package temperature is measured by "thermo-viewer", and also the IC is mounted on the “phenol-base” PC board in normal atmosphere. So it is concluded that the maximum case temperature (surface temperature of IC) rating is 120°C with adequate margin. REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 34 of 35 M51996AP/AFP Package Dimensions JEITA Package Code P-SOP16-5.3x10.1-1.27 RENESAS Code PRSP0016DE-A Previous Code 16P2N-A 9 *1 E HE 16 MASS[Typ.] 0.2g F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 8 Index mark A2 A1 c D Reference Symbol L A *2 e *3 y bp Detail F D E A2 A1 A bp c HE e y L RENESAS Code PRDP0014AA-A Previous Code 14P4 8 1 7 MASS[Typ.] 1.0g c *1 E 14 Min Nom Max 10.0 10.1 10.2 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0° 8° 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8 e1 JEITA Package Code P-DIP14-6.3x19-2.54 Dimension in Millimeters D L A1 A A2 *2 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. e *3 b3 SEATING PLANE bp Reference Symbol e1 D E A A1 A2 bp b3 c e L REJ03D0836-0201 Rev.2.01 Nov 14, 2007 Page 35 of 35 Dimension in Millimeters Min Nom Max 7.32 7.62 7.92 18.8 19.0 19.2 6.15 6.3 6.45 4.5 0.51 3.3 0.4 0.5 0.6 1.4 1.5 1.8 0.22 0.27 0.34 0° 15° 2.29 2.54 2.79 3.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. 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