HA16178P/FP
Power Factor Correction Controller IC
REJ03D0903-0100
Rev.1.00
Jun 12, 2007
Description
The HA16178P/FP is a power-factor correction (PFC) controller IC.
This IC adopts continuous conduction mode as PFC operation.
Various functions such as over voltage detection, over current detection, soft start, feedback-loop disconnection
detection, are incorporated in a single chip. This eliminates a significant amount of external circuitry.
PFC operation can be turned on and off by an external control signal. By using this function, PFC operation can be
disabled at low input voltage, allowing remote control from the secondary side.
A soft-start control pin provides for the easy adjustment of soft-start operation, and can be used to prevent overshooting
of the output voltage.
Features
• Maximum ratings
Power-supply voltage Vcc: 24 V
Operating junction temperature Tjopr: –40 to 125°C
• Electrical characteristics
VREF output voltage VREF: 5.0 V ± 3%
UVLO operation start voltage VH: 10.5 ± 0.7 V
UVLO operation stop voltage VL: 9.0 ± 0.5 V
PFC output maximum ON duty Dmax-out: 95% (typ.)
• Functions
Continuous conduction mode
Over voltage detection
Over current detection
Soft start
Feedback loop disconnection detection
PFC function on/off control
Package lineup: SOP-16 and DILP-16
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HA16178P/FP
Pin Arrangement
OUT 1
16 VCC
PGND 2
15 SS
SGND 3
14 EO
NC 4
13 FB
PFC-ON 5
12 IAC
VREF 6
11 NC
CAO 7
10 CT
CS 8
9 RT
(Top view)
Pin Description
Pin No.
Pin Name
I/O
Function
1
2
OUT
PGND
Output
—
3
4
SGND
NC
—
—
5
6
PFC-ON
VREF
7
8
CAO
CS
Output
Input/Output
Current control error amplifier output
Current sense signal input
9
10
RT
CT
Input/Output
Output
Timing resistor for operational frequency adjust
Timing capacitor for operational frequency adjust
11
12
NC
IAC
—
Input
13
14
FB
EO
Input
Output
Voltage control error amplifier input
Voltage control error amplifier output
15
16
SS
VCC
Output
Input
Timing capacitor for soft start time adjust
Power supply voltage input
Input
Output
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Power MOS FET gate driver output
Ground
Ground
No connection
PFC function on/off signal input
Reference voltage output
No connection
Multiplier reference current input
HA16178P/FP
Block Diagram
VCC
16
5 V Internal Bias
H
L
9
15.4 µs
VREF In
GOOD Out
RAMP
3.6 V
VREF GOOD
0.65 V
65 kHz
Oscillator
CAO
7
IAC
R
Q
S
Q
R
Q
S
Q
1
OUT
VREF
IMO = K × {IAC × (VEO – 1 V)}
SS
CAMP
IAC
IMO
VE
O
12
Gate Driver
± 1.0 A (PEAK)
UVL
10
6
9.0 V
PFC-DT
770 ns
CT
5 V VREF
Generator
UVLO
27.5 V
RT
VREF
10.5 V
VREF
K
CS
55 k
3.3 k
8
CLIMIT
Gain
Select
K = 0.20
Gain
Selector
EO
–0.30 V
K = 0.05
VREF
14
2.5 V
FB
2.688 V
2.638 V
VAMP
13
15
SS
25 µA
B+OVP
PGND
0.50 V
2
PFC-ON
FB LOW
PFC-OFF
5
0.1 µ
1.75 V
1.60 V
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SGND
3
HA16178P/FP
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Ratings
24
Unit
V
Note
±1.0
±0.1
A
A
3
–0.3 to Vcc
–0.3 to Vref
V
V
4
5
–0.3 to Vcaoh
–0.3 to Veoh
V
V
–0.3 to +6.5
300
V
µA
–200
±800
µA
µA
Supply voltage
VCC
OUT peak current
OUT DC current
Ipk-out
Idc-out
Terminal voltage
Vi-group1
Vi-group2
CAO voltage
EO voltage
Vcao
Veo
PFC-ON voltage
PFC-ON clamp current
Vpfc-on
Ipfc-on-clamp
RT current
CT current
Irt
Ict
IAC current
CS voltage
Iiac
Vi-cs
1
–1.5 to 0.3
mA
V
VREF current
Power dissipation
Io-ref
Pt
–5
1
mA
W
Operating junction temperature
Storage temperature
Tj-opr
Tstg
–40 to 125
–55 to 150
°C
°C
Notes: 1.
2.
3.
4.
Rated voltages are with reference to the GND pin.
For rated currents, inflow to the IC is indicated by (+), and outflow by (–).
The transient current when driving a capacitive load.
This is the rated voltage for the following pins:
OUT
5. This is the rated voltage for the following pins:
VREF, FB, IAC, SS, RT, CT
6. HA16178P (DILP) type: θja = 120°C/W
7. HA16178FP (SOP) type: θja = 120°C/W
This is value mounted on glass epoxy board of 10% wiring density and 40 mm × 40 mm × 1.6 mm.
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6, 7
HA16178P/FP
Electrical Characteristics
(Ta = 25°C, VCC = 12 V, RT = 27 kΩ, CT = 1000 pF)
Supply
VREF
Item
Start threshold
Symbol
VH
Min
9.8
Typ
10.5
Max
11.2
Unit
V
Test Conditions
Shutdown threshold
UVLO hysteresis
VL
dVUVL
8.5
1.0
9.0
1.5
9.5
2.0
V
V
Start-up current
Is temperature stability
Is
dIs/dTa
140
—
200
–0.3
260
—
µA
%/°C
Operating current
Output voltage
Icc
Vref
3.45
4.85
4.5
5.00
6.45
5.15
mA
V
IAC = 0 A, CL = 0 F
Isource = 1 mA
Line regulation
Vref-line
—
5
20
mV
Isource = 1 mA,
VCC = 12 V to 23 V
Isource = 1 mA to 5 mA
VCC = 9.5 V
1
*
Load regulation
Vref-load
—
5
20
mV
Temperature stability
Initial accuracy
dVref
fout
—
58.5
±80
65
—
71.5
ppm/°C
kHz
Ta = –40 to 125°C *
Measured pin: OUT
fout temperature stability
fout voltage stability
dfout/dTa
fout-line
—
–1.5
±0.1
0.5
—
1.5
%/°C
%
Ta = –40 to 125°C *
VCC = 12 V to 18 V
CT peak voltage
Ramp valley voltage
Vct-H
Vct-L
—
—
3.6
0.65
4.0
—
V
V
Soft start
RT voltage
Sink current
Vrt
Iss
1.07
15.0
1.25
25.0
1.43
35.0
V
µA
SS = 2 V
Current
limit
Threshold voltage1
Delay to output
VCL1
td-CL
–0.33
—
–0.30
280
–0.27
500
V
ns
PFC-ON = 2 V
CS = 0 to –1 V
VAMP
Feedback voltage
Input bias current
Vfb
Ifb
2.40
–0.3
2.50
0
2.60
0.3
V
µA
FB-EO Short
Measured pin: FB
Open loop gain
High voltage
Av-v
Veoh
—
5.2
60
5.7
—
6.2
dB
V
*
FB = 2.3 V, EO: Open
Low voltage
Source current
Veol
Isrc-eo
—
—
0.1
–120
0.3
—
V
µA
FB = 2.7 V, EO: Open
FB = 1.0 V, EO = 2.5 V
Sink current
Transconductance
Isnk-eo
Gm-v
—
150
120
200
—
290
µA
µA/V
FB = 4.0 V, EO = 2.5 V
FB = 2.5 V, EO = 2.5 V
Input offset voltage
Open loop gain
Vio-ca
Av-ca
—
—
(–10)
60
0
—
mV
dB
High voltage
Low voltage
Vcaoh
Vcaol
5.2
—
5.7
0.1
6.2
0.3
V
V
Source current
Sink current
Isrc-ca
Isnk-ca
—
—
–90
90
—
—
µA
µA
Transconductance
Gm-c
150
200
290
µA/V
Oscillator
CAMP
Note:
1. Design spec.
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1
1
1
*
1
*
1
1
*
1
*
1
CAO = 2.5 V *
1
CAO = 2.5 V *
1
*
HA16178P/FP
(Ta = 25°C, VCC = 12 V, RT = 27 kΩ, CT = 1000 pF)
IAC/
Multiplier
Item
IAC PIN voltage
Symbol
Viac
Min
1.6
Typ
2.3
Max
3.0
Unit
V
Terminal offset current
Output current
(PFC-ON = 2.5 V)
Imo-offset
Imo1
–136
—
–90
–20
–73
—
µA
µA
IAC = 0 A, CS = 0 V
1,2
EO = 2 V, IAC = 100 µA *
Imo2
Imo3
—
—
–60
–5
—
—
µA
µA
EO = 4 V, IAC = 100 µA *
1,2
EO = 2 V, IAC = 100 µA *
PFC-CS resistance
Imo4
Rmo
—
—
–15
3.3
—
—
µA
kΩ
EO = 4 V, IAC = 100 µA *
1
*
Gain voltage
Minimum duty cycle
Vpfc-gain
Dmin-out
(3.4)
—
(4.1)
—
(4.7)
0
V
%
Gain = 0.125*
CAO = 4.0 V
Maximum duty cycle
Rise time
Dmax-out
tr-out
90
—
95
30
98
100
%
ns
CAO = 0 V
CL = 1000 pF
Fall time
Low voltage
tf-out
Vol1-out
—
—
30
0.05
100
0.2
ns
V
CL = 1000 pF
Iout = 20 mA
Vol2-out
Vol3-out
—
—
0.5
0.03
2.0
0.7
V
V
Iout = 200 mA (Pulse Test)
Iout = 10 mA, VCC = 5 V
Voh1-out
Voh2-out
11.5
10.0
11.9
11.0
—
—
V
V
Iout = –20 mA
Iout = –200 mA (Pulse Test)
Output current
(PFC-ON = 5.5 V)
OUT
High voltage
Notes: 1. Design spec.
2. Imo1 to Imo4 defined as,
Imo = (CS Terminal Current) – (Imo-offset)
CAO
IMO = K × {IAC × (VEO – 1 V)}
O
VE
CAMP
IAC
Oscillator
K
IAC
VREF
–0.3 V
3.3 k
55 k
Imo
Terminal Current
Imo-offset
CS
REJ03D0903-0100 Rev.1.00 Jun 12, 2007
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CLIMIT
Test Conditions
IAC = 100 µA
1,2
1,2
1
HA16178P/FP
(Ta = 25°C, VCC = 12 V, RT = 27 kΩ, CT = 1000 pF)
Supervisor/
PG
Note:
Item
PFC enable voltage
Symbol
Von-pfc
Min
1.62
Typ
1.75
Max
1.87
Unit
V
PFC disable voltage
Input current
Voff-pfc
Ipfc-on
1.48
—
1.6
0.1
1.72
1.0
V
µA
Input pin: PFC-ON
PFC-ON = 2 V
B+ OVP set voltage
B+ OVP reset voltage
dVovps
dVovpr
0.125
0.075
0.188
0.138
0.250
0.200
V
V
Input pin: FB *
1
Input pin: FB *
FB low set voltage
Vfbls
0.45
0.50
0.55
V
Input pin: FB
1. dVovps = Vovps – Vref × 0.5
dVovpr = Vovpr – Vref × 0.5
Vovps
Vovpr
FB
Vfbls
OUT
REJ03D0903-0100 Rev.1.00 Jun 12, 2007
Page 7 of 24
Vref × 0.5
Test Conditions
Input pin: PFC-ON
1
HA16178P/FP
Timing Chart
1. Start-up Timing
VCC
10.5 V (VH)
5V
4.0 V
VREF
VREF GOOD
PFC-ON
1.75 V
(Von-pfc)
PFC-OFF
(Internal signal)
SS
CAO
CAO
SS
Soft start
OUT
Normal operation
+B voltage
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HA16178P/FP
2. Oscillator, Gate Driver Output
CT
CAO
Dead time
(Internal signal)
OUT
(Leading edge control)
3. PFC Operation ON/OFF
1.75 V (Von-pfc)
1.6 V (Voff-pfc)
PFC-ON
SS
OUT
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HA16178P/FP
4. FB Supervisor
Vovps
FB
B+OVP
(Internal signal)
FB LOW
(Internal signal)
SS
OUT
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Page 10 of 24
Vovpr
0.5 V (FB LOW)
HA16178P/FP
5. PFC ON/OFF Function
Em
Rec+
R1
720 k
Rec–
R2
20 k
5
PFC-ON
C1
2.2 µ
PFC ON/OFF control
1.75 V
1.60 V
2 × Em
R2
×
π
R1 + R2
2 × √2 × Vac
R2
=
×
π
R1 + R2
VPFC-ON (DC) × π
R1 + R2
×
Vac =
2 × √2
R2
VPFC-ON (DC) =
Vac
71.9 V
65.8 V
1.75 V
1.60 V
PFC-ON
PFC-OFF
(Internal signal)
PFC ON status
REJ03D0903-0100 Rev.1.00 Jun 12, 2007
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HA16178P/FP
Description of Pin Functions
OUT Pin:
The power MOS FET gate-drive signal is output from this pin, and takes the form of a rectangular waveform with an
amplitude of VCC-GND.
PGND Pin:
The ground terminal for OUT driver.
SGND Pin:
The ground terminal for internal circuits.
PFC-ON Pin:
This pin is applied smoothing voltage of rectified AC voltage. When 1.75 V (typ.) or more is applied to this pin, PFC
operation starts. When the voltage is 1.6 V (typ.) or lower, the PFC operation stops.
VREF Pin:
Temperature-compensated voltage with an accuracy of 5 V ± 3% is output from this pin. The pin should supply no
more than 5 mA (max.) source current. This pin has no sink capabilities.
CAO Pin:
This pin is the current-error amplifier output, and is connected to the phase-compensation circuit of the current-error
amp. The result of comparison of the voltage on this pin and the CT pin produces the pulse output from the OUT pin.
CS Pin:
Current detection pin. The current is controlled to be proportional to the AC voltage and the power factor is corrected.
When the voltage on this pin drops to –0.3 V (typ.) or below, over current detection circuit operates, and OUT pin is
stopped.
RT Pin:
A pin for frequency adjustment of the oscillator.
CT Pin:
A pin for frequency adjustment of the oscillator.
IAC Pin:
This pin is for detecting the input AC voltage waveform. For processing within the IC, the AC voltage waveform is
converted to current information.
FB Pin:
This pin is the input to the voltage error amp. This pin is applied to voltage divided PFC output with resistors. The
feedback loop is intended to keep 2.5 V (typ.).
EO Pin:
This pin is the output of the voltage error amp. This pin is connected to the phase-compensation circuit of the voltage
error amp. The voltage on this pin is the input signal to the internal multiplier.
SS Pin:
This pin is connected to GND or VREF via a capacitor. This pin is pulled up to the VREF pin voltage until PFC
operation starts. When the voltage on the PFC-ON pin has reached 1.75 V (typ.) PFC operation is start and this pin
flows 25 µA source current. Operation of the CAO pin is affected by that of the SS pin, the pulse width of the OUT pin
is limited, and this prevents overshooting when start up.
VCC Pin:
IC power-supply pin. The IC starts up at 10.5 V (typ.), and stops at 9 V (typ.).
REJ03D0903-0100 Rev.1.00 Jun 12, 2007
Page 12 of 24
HA16178P/FP
Description of Functions
1. UVL Circuit
The UVL circuit monitors the Vcc voltage. When the voltage is lower than 9.0 V, the IC is stopped. When the voltage
is higher than 10.5 V, IC is started.
When operation of the IC is stopped by the UVL circuit, the driver circuit output is fixed low, output of VREF is
stopped, and the oscillator is stopped.
VCC
9 V (VL)
10.5 V (VH)
5V
VREF
4.0 V
CAO
CT
OUT
Figure 1 UVL Operation
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HA16178P/FP
2. Operating Frequency
The HA16178 operating frequency fosc is determined by adjusting the timing resistor Rt (the RT pin, pin 9) and the
timing capacitance Ct (the CT pin, pin 10). The operating frequency is approximated by the following expression:
fosc =
1.755 × 106
(kHz)
Rt (kΩ) × Ct (pF)
When the IC is operated at high frequencies, the expression becomes less accurate due to IC internal delay time, etc.
Please confirm operation the value with the actually mounted IC. The maximum operating frequency is 400 kHz. As a
reference, the operating frequency data when the timing resistor and the timing capacitance are changed is shown in the
below figure.
Operating Frequency (kHz)
1000
Timing capacitance
Ct
100
470 pF
1000 pF
2200 pF
10
4700 pF
1
1
10
100
Timing Resistance (kΩ)
Figure 2 Operating Frequency Characteristics
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HA16178P/FP
3. Soft Start
This function prevents applying excessive stress on external components and overshooting of the PFC output voltage (B
+ voltage) when start up. The pulse width is gradually widening from 0% duty cycle. During soft-start operation, the
SS and CAO signals lower with link. The duty cycle is controlled by the CAO signal.
The soft-start time can be set by an external capacity.
PFC-ON
1.75 V
CAO
SS
SS
CAO
CT
OUT
PFC output voltage
Figure 3 Soft-Start Operation Waveform
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HA16178P/FP
Main Characteristics
Standby Current vs. Power Supply Voltage Characteristics
250
Ta = 25°C
Is (µA)
200
150
100
50
0
0
1
2
3
4
5
6
Vcc (V)
7
8
9
10
11
Power Dissipation vs. Power Supply Voltage Characteristics
8
7.5
Ta = 25°C
CL = 1000 pF
7
Icc (mA)
6.5
6
5.5
5
4.5
4
3.5
10
12
14
16
18
Vcc (V)
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20
22
24
HA16178P/FP
Reference Voltage Temperature Characteristics
5.2
Vcc = 12 V
Iref = –1 mA
5.15
VREF (V)
5.1
5.05
5
4.95
4.9
4.85
4.8
–40
–20
0
20
40
Ta (°C)
60
80
100
120
100
120
Operating Frequency Temperature Characteristics
75
73
Frequency (kHz)
71
Vcc = 12 V
RT= 27 kΩ
CT = 1000 pF
69
67
65
63
61
59
57
55
–40
–20
0
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20
40
Ta (°C)
60
80
HA16178P/FP
Start-up Voltage Temperature Characteristics
11.5
11.3
11.1
VH (V)
10.9
10.7
10.5
10.3
10.1
9.9
9.7
9.5
–40
–20
0
20
40
Ta (°C)
60
80
100
120
100
120
Shutdown Voltage Temperature Characteristics
9.6
9.4
VL (V)
9.2
9
8.8
8.6
8.4
–40
–20
0
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20
40
Ta (°C)
60
80
HA16178P/FP
Standby Current Temperature Characteristics
280
Vcc = 9.5 V
260
240
Is (µA)
220
200
180
160
140
120
–40
–20
0
20
40
Ta (°C)
60
80
100
120
100
120
Operating Current Temperature Characteristics
7
6.5
Vcc = 12 V
CL = 0 pF
Icc (mA)
6
5.5
5
4.5
4
3.5
3
–40
–20
0
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20
40
Ta (°C)
60
80
HA16178P/FP
VAMP Feedback Voltage Temperature Characteristics
2.7
Vcc = 12 V
FB-EO Short
2.65
2.6
Vfb (V)
2.55
2.5
2.45
2.4
2.35
2.3
–40
–20
0
20
40
Ta (°C)
60
80
100
120
EO Pin Voltage vs. CS Pin Current Characteristics
100
Ta = 25°C
Vcc = 12 V
Iac = 100 µA
90
80
–Imo (µA)
70
60
PFC-ON = 2.5 V
50
40
30
20
10
PFC-ON = 5.5 V
0
0
1
2
3
Veo (V)
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4
5
HA16178P/FP
Vamp Frequency Characteristics
80
200
Gain (dB)
150
40
100
20
50
0
0
–20
–50
–40
–100
–60
–150
–80
10E+0
100E+0
1E+3
10E+3
100E+3
Frequency f (Hz)
1E+6
Phase (deg.)
Ta = 25°C
Vcc = 12 V
60
–200
10E+6
Camp Frequency Characteristics
80
200
Gain (dB)
150
40
100
20
50
0
0
–20
–50
–40
–100
–60
–150
–80
10E+0
100E+0
1E+3
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10E+3
100E+3
Frequency f (Hz)
1E+6
–200
10E+6
Phase (deg.)
Ta = 25°C
Vcc = 12 V
60
HA16178P/FP
Precautions on Usage
1. CS Pin
The CS pin is used to for detection in PFC control led current. When power supply is started up, the voltage drop of
inrush current must not exceed the maximum rated value of the CS pin.
2. VREF Pin
For stabilization, be sure to connect a capacitor between the pin and ground. It possible to occur overshoot of VREF by
connected capacitance. The degree of the overshoot will depend on the value of the connected capacitor. Pay particular
attention to this point if you intend to use the VREF pin voltage as reference voltage for an external circuit.
Vref Peak Voltage (V)
Vref Overshoot
7
6.5
6
5.5
5
0.01
0.1
Cref (µF)
1
Figure 4 Overshoot on the VREF Pin vs. Capacitance
3. PFC-ON Pin
In design of worldwide power supply, it is possible that calculated voltage exceed maximum rated voltage of PFC-ON
pin. Actually, as a clamp circuit is included in the PFC-ON pin, the voltage is clamped however, clamp current must
not exceed 300 µA.
4. OUT Pin
Undershooting or overshooting may occur due to the wiring of the OUT pin. These may bring to malfunctions of the IC.
In such a case, prevent the undershooting or overshooting by using a Schottky barrier diode, etc.
5. Pattern Layout
In designing the pattern layout, pay as much attention as is possible to the following points.
(1) Place the stabilizing capacitor for the VREF pin as close to the IC as possible, and keep the wiring short.
(2) Place the timing resistor of the RT pin as close to the IC as possible, and keep the wiring short.
(3) Place the phase compensation circuit for the CAO pin as close to the IC as possible, and keep the wiring short.
(4) Place the timing capacitor for the CT pin as close to the IC as possible, and keep the wiring short.
(5) Place the stabilizing capacitor for the VCC pin as close to the IC as possible, and keep the wiring short.
(6) Place the IC pins and their wiring as far from high-voltage switching lines (particularly the drain voltage for the
power MOS FET) as possible and in general design the wiring to minimize switching noise.
(7) It is probable that stability of operation is achieved by inputting signals via filters to pins with input functions. Note,
however, that such filter circuits can affect the bias conditions for pins that have both input and output functions.
6. About NC Terminal
NC terminal uses open.
REJ03D0903-0100 Rev.1.00 Jun 12, 2007
Page 22 of 24
HA16178P/FP
System Diagram
Rec+
B+
T1
Q1
680 k
To FB
470 µ
(450 V)
Rec–
From OUT
from
auxiliary
B+ OUT
(385 V dc)
680 k
VRB1
GND
4.7 µ
24 V
VCC
16
5 V Internal Bias
L
RT
15.4 µs
CT
0.65 V
RAMP
3.6 V
1000 p
VREF GOOD
65 kHz
Oscillator
VREF
CAO
3.3 n 30 k
7
470 p
3M
100
R
Q
S
Q
1
OUT
IMO
VE
VREF
CS
55 k
3.3 k
CLIMIT
Gain
Select
0.01 µ
820 k
Q
K
8
0.016
(5 W)
S
To
Q1 gate
Gate Driver
±1.0 A (PEAK)
IAC
O
1.75 M
1000 p
Q
SS
CAMP
12
R
VREF
IMO = K × {IAC × (VEO – 1 V)}
IAC
0.1 µ
VREF In
GOOD Out
UVL
10
6
9.0 V
PFC-DT
770 ns
9
5 V VREF
Generator
UVLO
27.5 V
27 k
VREF
10.5 V
H
K = 0.20
Gain
Selector
EO
–0.30 V
VREF
K = 0.05
VREF
14
2.5 V
4.7 µ
15
33 n
SS
FB
2.688 V
2.638 V
VAMP
13
From
VRB1 (B+ monitor1)
25 µA
B+OVP
PGND
2
720 k
0.50 V
PFC-ON
FB LOW
5
2.2 µ
20 k
PFC-OFF
SGND
0.1 µ
1.75 V
1.60 V
REJ03D0903-0100 Rev.1.00 Jun 12, 2007
Page 23 of 24
3
HA16178P/FP
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
Previous Code
DP-16FV
MASS[Typ.]
1.05g
D
9
E
16
1
8
b3
0.89
A1
A
Z
L
Reference
Symbol
θ
bp
e
e1
D
E
A
A1
bp
b3
c
θ
e
Z
L
c
e1
( Ni/Pd/Au plating )
JEITA Package Code
P-SOP16-5.5x10.06-1.27
RENESAS Code
PRSP0016DH-B
*1
Previous Code
FP-16DAV
Dimension in Millimeters
Min
Nom Max
7.62
19.2 20.32
6.3 7.4
5.06
0.51
0.40 0.48 0.56
1.30
0.19 0.25 0.31
0°
15°
2.29 2.54 2.79
1.12
2.54
MASS[Typ.]
0.24g
D
F
16
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
9
c
HE
*2
E
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
1
Z
8
e
*3
bp
x
Reference
Symbol
M
A
L1
A1
θ
y
L
Detail F
REJ03D0903-0100 Rev.1.00 Jun 12, 2007
Page 24 of 24
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Dimension in Millimeters
Min Nom Max
10.06 10.5
5.50
0.00 0.10 0.20
2.20
0.34 0.40 0.46
0.15 0.20 0.25
0°
8°
7.50 7.80 8.00
1.27
0.12
0.15
0.80
0.50 0.70 0.90
1.15
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