IRMCK182M High Performance Sensorless Motor Control IC Description IRMCK182M is a high performance One Time Programmable ROM based motion control IC designed primarily for appliance applications which contains two computation engines integrated into one monolithic chip. One is the Flexible Motion Control Engine (MCETM) for sensorless control of permanent magnet motors or induction motors; the other is an 8-bit high-speed microcontroller (8051). The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the complex sensorless control algorithms, such as the Angle Estimator, are provided as complete predefined control blocks. A unique analog/digital circuit and algorithm fully supports single shunt or leg shunt current reconstruction. IRMCK182M comes in a 32 pin QFN 5x5 package. Features Product Summary • Maximum clock input (fcrystal) Maximum Internal clock (SYSCLK) Maximum 8051 clock (8051CLK) MCETM computation data range 8051/MCE Data RAM MCE Program RAM PWM carrier frequency A/D input channels A/D converter resolution A/D converter conversion speed Analog output (PWM) resolution UART baud rate (typ) Number of digital I/O (max) Package (lead free) Maximum 3.3V operating current • • • • • • • TM MCE (Flexible Motion Control Engine) Dedicated computation engine for high efficiency sinusoidal sensorless motor control Built-in hardware peripheral for single or two shunt current feedback reconstruction and analog circuits Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine control JTAG programming port for emulation/debugger Serial communication interface (UART) Watchdog timer with independent internal clock Internal 32Kbyte OTP ROM 3.3V single supply Base Part Number Package Type IRMCK182M QFN32 1 www.irf.com Standard Pack 60 MHz 128MHz 32MHz 16 bit signed 2KB 12KB 20 bits/ SYSCLK 4 12 bits 2 μsec 8 bits 57.6 Kbps 7 QFN32 60mA Orderable Part Number Form Quantity Tape and Reel 3000 IRMCK182MTR Tray 3120 IRMCK182MTY © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 Table of Contents 1 2 3 4 Overview ....................................................................................................................................5 Pinout .........................................................................................................................................6 IRMCK182M Block Diagram and Main Functions......................................................................7 Application connection and Pin function ....................................................................................9 4.1 4.2 4.3 4.4 4.5 5 8051 Peripheral Interface Group .......................................................................................10 Motion Peripheral Interface Group ....................................................................................11 Analog Interface Group .....................................................................................................11 Power Interface Group ......................................................................................................11 Test Interface Group .........................................................................................................11 DC Characteristics ...................................................................................................................13 5.1 5.2 5.3 5.4 5.5 5.6 6 Absolute Maximum Ratings ...............................................................................................13 System Clock Frequency and Power Consumption ..........................................................13 Digital I/O DC Characteristics ............................................................................................14 Analog I/O (IFBU+,IFBU-,IFBUO, IFBV+,IFBV-,IFBVO) DC Characteristics .................... 15 Under Voltage Lockout DC characteristics ........................................................................16 Itrip comparator DC characteristics ...................................................................................16 AC Characteristics ...................................................................................................................17 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 7 8 9 10 11 Digital PLL AC Characteristics ..........................................................................................17 Analog to Digital Converter AC Characteristics .................................................................18 Op amp AC Characteristics ...............................................................................................19 SYNC to SVPWM and A/D Conversion AC Timing ...........................................................20 GATEKILL to SVPWM AC Timing .....................................................................................21 Itrip AC Timing...................................................................................................................21 UART AC Timing ...............................................................................................................21 CAPTURE Input AC Timing ..............................................................................................23 OTP Programming Timing .................................................................................................24 JTAG AC Timing ...............................................................................................................25 I/O Structure.............................................................................................................................26 Pin List .....................................................................................................................................29 Package Dimensions ...............................................................................................................31 Part Marking Information..........................................................................................................32 Qualification Information ..........................................................................................................32 2 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 List of Tables Table 1 Absolute Maximum Ratings ......................................................................................................... 13 Table 2 System Clock Frequency ............................................................................................................. 13 Table 3 Digital I/O DC Characteristics ...................................................................................................... 14 Table 5 Analog I/O DC Characteristics .................................................................................................... 15 Table 6 UVcc DC Characteristics .............................................................................................................. 16 Table 7 Itrip DC Characteristics................................................................................................................. 16 Table 8 PLL AC Characteristics ................................................................................................................ 17 Table 9 A/D Converter AC Characteristics .............................................................................................. 18 Table 10 Current Sensing OP Amp AC Characteristics ........................................................................ 19 Table 11 SYNC AC Characteristics .......................................................................................................... 20 Table 12 GATEKILL to SVPWM AC Timing ............................................................................................ 21 Table 13 Itrip AC Timing ............................................................................................................................. 21 Table 14 UART AC Timing ......................................................................................................................... 22 Table 15 CAPTURE AC Timing................................................................................................................. 23 Table 16 OTP Programming Timing ......................................................................................................... 24 Table 17 JTAG AC Timing ......................................................................................................................... 25 Table 18 Pin List .......................................................................................................................................... 30 3 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 List of Figures Figure 1 Typical Application Block Diagram Using IRMCK182M .....................................................5 Figure 2 Pinout of IRMCK182M........................................................................................................6 Figure 3 Crystal circuit example .....................................................................................................17 Figure 4 Voltage droop and S/H hold time .....................................................................................18 Figure 5 A capacitor of 47pF is recommended at the output pin of all op amps. ........................... 19 Figure 6 SYNC timing .....................................................................................................................20 Figure 7 Gatekill timing ...................................................................................................................21 Figure 8 ITRIP timing .....................................................................................................................21 Figure 9 UART timing .....................................................................................................................22 Figure 10 CAPTURE timing............................................................................................................23 Figure 11 OTP programming timing ...............................................................................................24 Figure 12 JTAG timing ...................................................................................................................25 Figure 13 PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output ....................................26 Figure 14 All digital I/O except motor PWM output.........................................................................26 Figure 15 RESET, GATEKILL I/O ..................................................................................................27 Figure 16 Analog input ...................................................................................................................27 Figure 17 Analog operational amplifier output and AREF I/O structure .........................................27 Figure 18 VPP programming pin I/O structure ...............................................................................28 Figure 19 VSS and AVSS pin structure ..........................................................................................28 Figure 20 VDD1 and VDDCAP pin structure ..................................................................................28 Figure 21 XTAL0/XTAL1 pins structure ..........................................................................................28 4 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 1 Overview IRMCK182M is a new generation International Rectifier integrated circuit device primarily designed as a one-chip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCK182M provides a built-in closed loop sensorless control algorithm using the unique flexible Motion Control Engine (MCETM) for permanent magnet motors as well as induction motors. The MCETM consists of a collection of control elements, motion peripherals; a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCK182M also employs a unique single shunt current reconstruction circuit in addition to two leg shunt current sensing circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC. Motion control programming is achieved using a dedicated graphical compiler integrated into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 high-speed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application schematic using the IRMCK182M. IRMCK182M contains 32K bytes of OTP program ROM, and comes in a 32-pin QFN package. Host Communication (RS232C) Appliance PM motor Drive Galvanic isolation 15V Passive EMI Fillter PM motor IPM or SPM Or IM motor Gate signal IRS2336D IRMCK182 Power Supply 3.3V 7 Digital I/O 4 Analog Input Figure 1 Typical Application Block Diagram Using IRMCK182M 5 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 2 Pinout TCK TCK TDI/P5.1 TDI/P5.1 TDO/P5.3 TDO/P5.3 TMS/P5.2 TMS/P5.2 VPP/GATEKILL VPP/GATEKILL PWMUH PWMUH PWMVH PWMVH PWMWH PWMWH Pin out shown is based on QFN 5x5 32 pin package. 32 32 31 31 30 30 29 29 28 28 27 27 26 26 25 25 RESET RESET 11 24 PWMUL 24 PWMUL P1.1/RXD P1.1/RXD 22 23 23 PWMVL PWMVL P1.2/TXD P1.2/TXD 33 22 PWMWL 22 PWMWL XTAL0 XTAL0 44 XTAL1 XTAL1 55 VDD1 VDD1 66 19 19 VDDCAP VDDCAP VSS VSS 77 18 18 AVSS AVSS VDDCAP VDDCAP 88 17 IFBVO 17 IFBVO MCK182 21 VSS 21 VSS (Top (Top View) View) 11 11 12 12 13 13 14 14 15 15 16 16 AIN1 AIN1 IFBUIFBU- IFBU+ IFBU+ IFBUO IFBUO IFBVIFBV- IFBV+ IFBV+ 10 10 AIN0 AIN0 P2.6/AOPWM0 P2.6/AOPWM0 99 20 20 VDD1 VDD1 Figure 2 Pinout of IRMCK182M 6 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 3 IRMCK182M Block Diagram and Main Functions IRMCK182M block diagram is shown in Figure 3. Mini-Motion Control Engine (MiniMCE) D/A (PWM) Speed command Capture Timer Counnter0,1,2 Watchdog Timer SND Program ROM/RAM 32kB UART RCV GATEKILL From shunt resistor AIN0 PORT 1 8bit CPU Core PORT 2 Digital I/Os To IGBT gate drive Low Loss SVPWM Single Shunt Motor Current Reconstruction 8bit uP Address/data bus Host Interface 6 PORT 5 Local RAM 2kbyte 8bit (8051) microcontroller Motion Control Modules Dual Port RAM 2kbyte MCE Program RAM 12kbyte AIN1 A/D MUX S/H Motion Control Bus 2 Monitoring IFBU IFBV 3 analog input 3 Interrupt Control Motion Control Sequencer 4 Emulator Debugger JTAG 2 Ceramic Resonator (4MHz) Freq Synthesizer 32MHz 128MHz Figure 3 IRMCK182M Block Diagram IRMCK182M contains the following functions for sensorless AC motor control applications: • Motion Control Engine (MCETM) o Sensorless FOC (complete sensorless field oriented control) o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) o Ramp o Limit o Angle estimate (sensorless control) o Inverse Clark transformation o Vector rotator o Bit latch o Peak detect 7 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 • o Transition o Multiply-divide (signed and unsigned) o Divide (signed and unsigned) o Adder o Subtractor o Comparator o Counter o Accumulator o Switch o Shift o ATAN (arc tangent) o Function block (any curve fitting, nonlinear function) o 16 bit wide Logic operations (AND, OR, XOR, NOT, NEGATE) o MCETM program memory and dual port RAM (max 12K+2k byte) o MCETM control sequencer 8051 microcontroller o Two 16 bit timer/counters o One 16 bit periodic timer o One 16 bit watchdog timer o One 16 bit capture timer o Up to 7 discrete I/Os o 4 channel 12 bit A/D Buffered (current sensing) two channels (0 – 1.2V input) Unbuffered two channels (0 – 1.2V input) o JTAG port (4 pins) o Up to three channels of analog output (8 bit PWM) o UART o 32K byte OTP program ROM o 2K byte data RAM 8 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 4 Application connection and Pin function System Clock XTAL0 XTAL1 4MHz Crystal Host Microcontroller (RS232C) P1.2/TXD P1.1/RXD Frequency Synthesizer Low Loss Space Vector PWM System clock Motion Control Modules RS232C Dual Port Memory (2kB) & MCE Memory (12kB) P1.1/RXD P1.2/TXD PORT1 P1.5 P2.6/AOPWM0 Digital I/O Control PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL GATEKILL Motion Control Sequencer Single Shunt Current Sensing HVIC Gate Drive IRS2336D AVREF P2.7/AOPWM1 PORT2 IFBU+ S/H IFBUIFBUO AVREF TDI/P5.1 TDO/P5.3 TMS/P5.2 PORT5 Timers IFBV+ IFBV- S/H IFBVO Watchdog Timer Local RAM (2kByte) P2.6/AOPWM0 PWM1 Analog Output 12bit A/D & MUX Motor 4 AIN0,AIN1 Other analog input (0-1.2V) Optional External Voltage Reference (0.6V) TCLK JTAG Control (OTP programming & Emulation) P5.1/TDI P5.2/TMS TDO RESET OTP Programming Voltage (6.5V) P1.5/VPP/GK 3.3V Program RAM (32kByte) JTAG Interface AVSS AVDD RESET System Reset 8051 CPU VDD1 VSS IRMCK182 3.3V 1.8V Voltage Regulator VDDCAP 1.8V Figure 4 IRMCK182M Connection Diagram 9 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 4.1 8051 Peripheral Interface Group UART Interface P1.2/TXD P1.1/RXD Output, Transmit data from IRMCK182M Input, Receive data to IRMCK182M Discrete I/O Interface P1.1/RXD P1.2/TXD VPP/GK P2.6/AOPWM0 P2.7/AOPWM1 P5.1/TDI P5.2/TMS Input/output port 1.1, can be configured as RXD input Input/output port 1.2, can be configured as TXD output OTP programming voltage, or GATEKILL input Input/output port 2.6, can be configured as AOPWM0 output Input/output port 2.7, can be configured as AOPWM1 output Input port 5.1, configured as JTAG port by default Input port 5.2, configured as JTAG port by default Analog Output Interface P2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 with programmable carrier frequency P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with programmable carrier frequency Crystal Interface XTAL0 Input, connected to crystal XTAL1 Output, connected to crystal Reset Interface RESET 10 www.irf.com Input and Output, system reset, doesn’t require external RC time constant © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 4.2 Motion Peripheral Interface Group PWM PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL Fault GATEKILL 4.3 IFBUIFBUO IFBV+ IFBVIFBVO AIN0 AIN1 Analog power return, (analog internal 1.8V power is shared with VDDCAP) Input, Operational amplifier positive input for single or U-phase leg shunt resistor current sensing Input, Operational amplifier negative input for single or U-phase leg shunt shunt resistor current sensing Output, Operational amplifier output for single or U-phase leg shunt shunt resistor current sensing Input, Operational amplifier positive input for V-phase leg shunt resistor current sensing Input, Operational amplifier negative input for V-phase leg shunt shunt resistor current sensing Output, Operational amplifier output for V-phase leg shunt shunt resistor current sensing Input, Analog input channel 0 (0 – 1.2V), typically configured for DC bus voltage input Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down to AVSS if unused Power Interface Group VDD1 VDDCAP VSS 4.5 Input, upon assertion, this negates all six PWM signals, active low, internally pulled up by 70kΩ Analog Interface Group AVSS IFBU+ 4.4 Output, PWM phase U high side gate signal, internally pulled down by 58kΩ Output, PWM phase U low side gate signal, internally pulled down by 58kΩ Output, PWM phase V high side gate signal, internally pulled down by 58kΩ Output, PWM phase V low side gate signal, internally pulled down by 58kΩ Output, PWM phase W high side gate signal, internally pulled down by 58kΩ Output, PWM phase W low side gate signal, internally pulled down by 58kΩ Digital power (3.3V) Internal 1.8V output, requires capacitors to the pin. Shared with analog power pad internally Note: The internal 1.8V supply is not designed to power any external circuits or devices. Only capacitors should be connected to this pin. Digital common Test Interface Group 11 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 P5.2/TMS TDO P5.1/TDI TCK 12 www.irf.com JTAG test mode input or input/output digital port JTAG data output JTAG data input, or input/output digital port JTAG test clock © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 5 DC Characteristics 5.1 Absolute Maximum Ratings Symbol VDD1 VIA VID VPP TA TS Parameter Supply Voltage Analog Input Voltage Digital Input Voltage OTP Programming voltage Ambient Temperature Storage Temperature Min -0.3 V -0.3 V -0.3 V -0.3V Typ - Max 3.6 V 1.98 V 6.0 V 7.0V -40 ˚C -65 ˚C - 85 ˚C 150 ˚C Condition Respect to VSS Respect to AVSS Respect to VSS Respect to VSS Table 1 Absolute Maximum Ratings Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 5.2 System Clock Frequency and Power Consumption CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max SYSCLK System Clock 32 128 1) PD Power consumption 160 200 Unit MHz mW Table 2 System Clock Frequency Note 1) The value is based on the condition of MCE clock=126MHz, 8051 clock 31.5MHz with a actual motor running by a typical MCE application program and 8051 code. 13 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 5.3 Digital I/O DC Characteristics Symbol VDD1 VPP VIL VIH CIN IL IOL2(2) Parameter Supply Voltage OTP Programming voltage Input Low Voltage Input High Voltage Input capacitance Input leakage current Low level output current Min 3.0 V 6.70V Typ 3.3 V 6.75V Max 3.6 V 6.80V Condition Recommended Recommended -0.3 V 2.0 V - - 0.8 V 3.6 V ±1 μA 33.4 mA Recommended Recommended 17.9 mA 3.6 pF ±10 nA 26.3 mA (1) VO = 3.3 V or 0 V VOL = 0.4 V (1) IOH2(2) High level output current 24.6 mA 49.5 mA 81 mA VOH = 2.4 V (1) Table 3 Digital I/O DC Characteristics Note: (1) Data guaranteed by design. (2) Applied to all digital I/O pins. 14 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 5.4 Analog I/O (IFBU+,IFBU-,IFBUO, IFBV+,IFBV-,IFBVO) DC Characteristics CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max VOFFSET Input Offset Voltage 26 mV VI Input Voltage Range 0V 1.2 V VOUTSW OP amp output 50 mV 1.2 V (1) operating range CIN Input capacitance 3.6 pF RFDBK OP amp feedback 5 kΩ 20 kΩ resistor OP GAINCL CMRR ISRC ISNK Operating Close loop Gain Common Mode Rejection Ratio Op amp output source current Op amp output sink current Condition Recommended (1) Requested between IFBO and IFB- 80 db - - (1) - 80 db - (1) - 1 mA - VOUT = 0.6 V (1) - 100 μA - VOUT = 0.6 V (1) Table 4 Analog I/O DC Characteristics Note: (1) Data guaranteed by design. 15 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 5.5 Under Voltage Lockout DC characteristics Unless specified, Ta = 25˚C. Symbol Parameter UVCC+ UVcc positive going Threshold UVCCUVcc negative going Threshold UVCCH UVcc Hysteresys Min 2.78 V Typ 3.04 V Max 3.23 V 2.78 V 2.97 V 3.23 V - 73 mV - Condition (1) (1) Table 5 UVcc DC Characteristics Note: (1) Data guaranteed by design. 5.6 Itrip comparator DC characteristics Unless specified, VDD1=3.3V, Ta = 25˚C. Symbol Parameter Min Itrip+ Itrip positive going Threshold ItripItrip negative going Threshold ItripH Itrip Hysteresys - Typ 1.22V Max - 1.10V - 120mV - Condition Table 6 Itrip DC Characteristics 16 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 6 AC Characteristics 6.1 Digital PLL AC Characteristics Symbol FCLKIN FPLL FLWPW JS D TLOCK Parameter Crystal input frequency Internal clock frequency Sleep mode output frequency Short time jitter Duty cycle PLL lock time Min 3.2 MHz Typ 4 MHz Max 60 MHz Condition (1) (see figure below) 32 MHz 50 MHz 128 MHz (1) FCLKIN ÷ 256 - - (1) - 200 psec 50 % - 500 μsec (1) (1) (1) Table 7 PLL AC Characteristics Note: (1) Data guaranteed by design. R1=1MΩ R2=1KΩ Xtal C1=30PF C2=30PF Figure 3 Crystal circuit example 17 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 6.2 Analog to Digital Converter AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter TCONV Conversion time THOLD Sample/Hold maximum hold time Min - Typ - Max 2.05 μsec 10 μsec Condition (1) Voltage droop ≤ 15 LSB (see figure below) Table 8 A/D Converter AC Characteristics Note: (1) Data guaranteed by design. Input Voltage Voltage droop S/H Voltage tSAMPLE THOLD Figure 4 Voltage droop and S/H hold time 18 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 6.3 Op amp AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter OPSR OP amp slew rate OPIMP TSET OP input impedance Settling time Min - Typ 10 V/μsec Max - - 108 Ω 400 ns - Condition VDD1 = 3.3 V, CL = 33 pF (1) (1) (2) VDD1 = 3.3 V, CL = 33 pF (1) Table 9 Current Sensing OP Amp AC Characteristics Note: (1) Data guaranteed by design. (2) To guarantee stability of the operational amplifier, it is recommended to load the output pin by a capacitor of 47pF, see Figure 5. Here only the single shunt current amplifier is show but all op amp outputs should be loaded with this capacitor. IRMCK172 IC AVREF External components IFBC+ IFBCIFBCO 47pF Figure 5 A capacitor of 47pF is recommended at the output pin of all op amps. 19 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 6.4 SYNC to SVPWM and A/D Conversion AC Timing twSYNC SYNC tdSYNC1 IU,IV,IW tdSYNC2 AINx tdSYNC3 PWMUx,PWMVx,PWMWx Figure 6 SYNC timing Unless specified, Ta = 25˚C. Symbol Parameter twSYNC SYNC pulse width tdSYNC1 SYNC to current feedback conversion time tdSYNC2 SYNC to AIN0-5 analog input conversion time tdSYNC3 SYNC to PWM output delay time Min - Typ 32 - Max 100 Unit SYSCLK SYSCLK - - 200 SYSCLK (1) - - 2 SYSCLK Table 10 SYNC AC Characteristics Note: (1) AIN1 through AIN5 channels are converted once every 6 SYNC events 20 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 6.5 GATEKILL to SVPWM AC Timing twGK GATEKILL tdGK PWMUx,PWMVx,PWMWx Figure 7 Gatekill timing Unless specified, Ta = 25˚C. Symbol Parameter twGK GATEKILL pulse width tdGK GATEKILL to PWM output delay Min 32 - Typ - Max 100 Unit SYSCLK SYSCLK Table 11 GATEKILL to SVPWM AC Timing 6.6 Itrip AC Timing Itrip tItrip PWMUH,PWMUL, PWMVH,PWMVH, PWMWH,PWMWL Figure 8 ITRIP timing Unless specified, Ta = 25˚C. Symbol Parameter tITRIP Itrip propagation delay Min - Typ - Max 100(sysclk)+1.0usec Unit SYSCLK+usec Table 12 Itrip AC Timing 6.7 UART AC Timing 21 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 TBAUD TXD Data and Parity Bit Start Bit Stop Bit RXD TUARTFIL Figure 9 UART timing Unless specified, Ta = 25˚C. Symbol Parameter TBAUD Baud Rate Period TUARTFIL UART sampling filter period (1) Min - Typ 57600 1/16 Max - Unit bit/sec TBAUD Table 13 UART AC Timing Note: (1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 TBAUD. If three sampled values do not agree, then UART noise error is generated. 22 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 6.8 CAPTURE Input AC Timing TCAPCLK tCAPHIGH CAPTURE PIN tCAPLOW tCRDELAY CREV(H,L) Internal register tCLDELAY CLAST(H,L) Internal register tINTDELAY Interrupt Vector Fetch Interrupt Figure 10 CAPTURE timing Unless specified, Ta = 25˚C. Symbol Parameter TCAPCLK CAPTURE input period tCAPHIGH CAPTURE input high time tCAPLOW CAPTURE input low time tCRDELAY CAPTURE falling edge to capture register latch time tCLDELAY CAPTURE rising edge to capture register latch time tINTDELAY CAPTURE input interrupt latency time Min 8 4 Typ - Max - Unit SYSCLK SYSCLK 4 - - 4 SYSCLK SYSCLK - - 4 SYSCLK - - 4 SYSCLK Table 14 CAPTURE AC Timing 23 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 6.9 OTP Programming Timing 6.75V VDD/VSS/Floating VDD/VSS/Floating VPP TVPS TVPH TCK TDI/TMS Figure 11 OTP programming timing Unless specified, Ta = 25˚C. Symbol Parameter TVPS VPP Setup Time TVPH VPP Hold Time Min 10 15 Typ - Max - Unit nsec nsec Table 15 OTP Programming Timing 24 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 6.10 JTAG AC Timing TJCLK TCK tJLOW tJHIGH tCO TDO tJSETUP tJHOLD TDI/TMS Figure 12 JTAG timing Unless specified, Ta = 25˚C. Symbol Parameter TJCLK TCK Period tJHIGH TCK High Period tJLOW TCK Low Period tCO TCK to TDO propagation delay time tJSETUP TDI/TMS setup time tJHOLD TDI/TMS hold time Min 10 10 0 Typ - Max 50 5 Unit MHz nsec nsec nsec 4 0 - - nsec nsec Table 16 JTAG AC Timing 25 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 7 I/O Structure The following figure shows the motor PWM output (PWMUH/PWMUL/PWMVH/PWMVL/PWMWH/PWMWL) VDD1 (3.3V) Internal digital circuit High true logic 6.0V PIN 270 Ω 6.0V 58k Ω VSS Figure 13 PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output The following figure shows the digital I/O structure except the motor PWM output VDD1 (3.3V) Internal digital circuit Low true logic 70k Ω 6.0V PIN 270 Ω 6.0V VSS Figure 14 All digital I/O except motor PWM output The following figure shows RESET and GATEKILL I/O structure. 26 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 VDD1 (3.3V) RESET GATEKILL circuit 70k Ω 6.0V PIN 270 Ω 6.0V VSS Figure 15 RESET, GATEKILL I/O The following figure shows the analog input structure. VDDCAP(1.8V) Analog input 6.0V PIN 1 Ω Analog Circuit 6.0V AVSS Figure 16 Analog input The following figure shows all analog operational amplifier output pins and AREF pin I/O structure. VDDCAP(1.8V) Analog output 6.0V PIN Analog Circuit 6.0V AVSS Figure 17 Analog operational amplifier output and AREF I/O structure 27 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 The following figure shows the VPP pin structure PIN 270 Ω 8.0V VSS Figure 18 VPP programming pin I/O structure The following figure shows the VSS and AVSS pins structure VDD1 AVDD PIN 6.0V Figure 19 VSS and AVSS pin structure The following figure shows the VDD1 and VDDCAP pin structure PIN 6.0V VSS Figure 20 VDD1 and VDDCAP pin structure The following figure shows the XTAL0 and XTAL1 pins structure VDDCAP(1.8V) 6.0V PIN 1 Ω 6.0V VSS Figure 21 XTAL0/XTAL1 pins structure 28 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 8 Pin List Pin Number Pin Name Internal Pull-up /Pull-down Pin Type 1 2 3 4 5 6 7 8 9 10 RESET P1.1/RXD P1.2/TXD XTAL0 XTAL1 VDD1 VSS VDDCAP P2.6/AOPWM0 AIN0 11 AIN1 I 12 IFBU- I 13 IFBU+ I 14 IFBUO O 15 IFBV- I 16 IFBV+ I 17 IFBVO O 18 19 20 21 22 AVSS VDDCAP VDD1 VSS PWMWL P P P P O 23 PWMVL 24 PWMUL 25 PWMWH 26 PWMVH 29 www.irf.com I/O I/O I/O I O P P P I/O I 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down O O O O Description Reset, low true, Schmitt trigger input UART receiver input or Discrete programmable I/O UART transmitter output or Discrete programmable I/O Crystal input Crystal output 3.3V digital power Digital common Internal 1.8V output, Capacitor(s) to be connected Discrete programmable I/O or PWM 0 digital output Analog input channel 0, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 1, 0-1.2V range, needs to be pulled down to AVSS if unused Single or U-phase leg shunt current sensing OP amp input (-) Single or U-phase leg shunt current sensing OP amp input (+) Single or U-phase leg shunt current sensing OP amp output Single or V-phase leg shunt current sensing OP amp input (-) Single or V-phase leg shunt current sensing OP amp input (+) Single or V-phase leg shunt current sensing OP amp output Analog ground Internal 1.8V output, Capacitor(s) to be connected 3.3V digital power Digital common PWM gate drive for phase W low side, configurable either high or low true. PWM gate drive for phase V low side, configurable either high or low true PWM gate drive for phase U low side, configurable either high or low true PWM gate drive for phase W high side, configurable either high or low true PWM gate drive for phase V high side, configurable either high or low true © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 Pin Number Pin Name 27 PWMUH 28 VPP/GK 29 30 31 32 TMS/P5.2 TDO/P5.3 TDI/P5.1 TCK Internal Pull-up /Pull-down 58 kΩ Pull down Pin Type O I/O P I/O O I/O I Description PWM gate drive for phase U high side, configurable either high or low true OTP programming power (6.5V) and PWM shutdown input JTAG test mode select or Discrete I/O JTAG test data output JTAG test data input or Discrete I/O JTAG test clock Table 17 Pin List 30 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 9 Package Dimensions 31 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 10 Part Marking Information Pin 1 Indentifier IR Logo Part Number MCK182 Date Code YWWP XXXXXX Production Lot 11 Qualification Information †† Qualification Level Industrial (per JEDEC JESD47) Moisture Sensitivity Level MSL2††† (per IPC/JEDEC J-STD-020) Machine Model Class B (per JEDEC standard JESD22-A115) Human Body Model Class 2 (per ANSI/ESDA/JEDEC JS-001) Charged Device Model Class C2 (per JEDEC standard JESD22-C101) Latch-Up Class I, Level B (per JEDEC standard JESD78) ESD RoHS Compliant Yes † Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ †† Higher qualification ratings may be available should the user have such requirements. Please contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. representative for further information. 32 www.irf.com Please contact your International Rectifier sales © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK182 Data and Specifications are subject to change without notice IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information 33 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014