IRMCK143 High Performance Sensorless Motor Control IC Description IRMCK171 is a high performance One Time Programmable ROM based motion control IC designed and optimized for appliance control which contains two computation engines integrated into one monolithic chip. One is the Flexible Motion Control Engine (MCETM) for sensorless control of permanent magnet motors or induction motors; the other is an 8-bit high-speed microcontroller (8051). The user can program a motion control algorithm by connecting these control elements using a graphic compiler. Key components of the complex sensorless control algorithms, such as the Angle Estimator, are provided as complete pre-defined control blocks. A unique analog/digital circuit and algorithm fully supports single shunt or leg shunt current reconstruction. IRMCK143 comes in a 64 pin QFP package. Features Product Summary • Maximum clock input (fcrystal) • • • • • • • • • • • MCETM (Flexible Motion Control Engine) Dedicated computation engine for high efficiency sinusoidal sensorless motor control Built-in hardware peripheral for single or two shunt current feedback reconstruction and analog circuits Supports induction machine and both interior and surface permanent magnet motor sensorless control Loss minimization Space Vector PWM Dedicated PFC PWM Two-channel analog output (PWM) Embedded 8-bit high speed microcontroller (8051) for flexible I/O and man-machine control JTAG programming port for emulation/debugger Serial communication interface (UART) I2C/SPI serial interface Internal 32Kbyte OTP ROM 3.3V single supply 60 MHz Maximum Internal clock (SYSCLK) 128MHz Maximum 8051 clock (8051CLK) TM MCE 32MHz computation data range 16 bit signed 8051/MCE Data RAM 2KB MCE Program RAM 12KB PWM carrier frequency 20 bits/ SYSCLK A/D input channels 7 A/D converter resolution 12 bits A/D converter conversion speed 2 μsec Analog output (PWM) resolution 8 bits UART baud rate (typ) 57.6 Kbps Number of digital I/O (max) 24 Package (lead free) QFP64 Maximum 3.3V operating current 1 Base Part Number Package Type IRMCK143 QFP www.irf.com Standard Pack 60mA Orderable Part Number Form Quantity Tray 1600 IRMCK143TY Tape and Reel 1500 IRMCK143TR © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 Table of Contents Overview...................................................................................................................................... 5 PINOUT ....................................................................................................................................... 6 IRMCK143 Block Diagram and Main Functions ........................................................................ 7 Application connection and Pin function .................................................................................... 9 4.1 8051 Peripheral Interface Group ......................................................................................... 10 4.2 Motion Peripheral Interface Group ..................................................................................... 11 4.3 Analog Interface Group ...................................................................................................... 12 4.4 Power Interface Group ........................................................................................................ 12 4.5 Test Interface Group ........................................................................................................... 13 5 DC Characteristics ..................................................................................................................... 14 5.1 Absolute Maximum Ratings ............................................................................................... 14 5.2 System Clock Frequency and Power Consumption ............................................................ 14 5.3 Digital I/O DC Characteristics ............................................................................................ 15 5.4 Analog I/O DC Characteristics ........................................................................................... 16 5.5 Under Voltage Lockout DC characteristics ........................................................................ 17 5.6 Itrip comparator DC characteristics .................................................................................... 17 5.7 CMEXT and AREF Characteristics .................................................................................... 17 6 AC Characteristics ..................................................................................................................... 18 6.1 Digital PLL AC Characteristics .......................................................................................... 18 6.2 Analog to Digital Converter AC Characteristics ................................................................ 19 6.3 Op amp AC Characteristics................................................................................................. 20 6.4 SYNC to SVPWM and A/D Conversion AC Timing ......................................................... 21 6.5 GATEKILL to SVPWM AC Timing .................................................................................. 22 6.6 Itrip AC Timing .................................................................................................................. 22 6.7 Interrupt AC Timing ........................................................................................................... 23 6.8 I2C AC Timing .................................................................................................................... 24 6.9 SPI AC Timing.................................................................................................................... 25 6.9.1 SPI Write AC timing .................................................................................................... 25 6.9.2 SPI Read AC Timing .................................................................................................... 26 6.10 UART AC Timing ........................................................................................................... 27 6.11 CAPTURE Input AC Timing .......................................................................................... 28 6.12 OTP Programming Timing .............................................................................................. 29 6.13 JTAG AC Timing ............................................................................................................ 30 7 I/O Structure .............................................................................................................................. 31 8 Pin List ....................................................................................................................................... 34 9 Package Dimensions .................................................................................................................. 37 10 Part Marking Information .......................................................................................................... 39 11 Qualification Information .......................................................................................................... 39 1 2 3 4 2 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 List of Tables Table 1. Absolute Maximum Ratings............................................................................................ 14 Table 2. System Clock Frequency ................................................................................................. 14 Table 3. Digital I/O DC Characteristics ........................................................................................ 15 Table 5. Analog I/O DC Characteristics ....................................................................................... 16 Table 6. UVcc DC Characteristics ................................................................................................ 17 Table 7. Itrip DC Characteristics................................................................................................... 17 Table 8. CMEXT and AREF DC Characteristics.......................................................................... 17 Table 9. PLL AC Characteristics .................................................................................................. 18 Table 10 . A/D Converter AC Characteristics............................................................................... 19 Table 11. Current Sensing OP Amp AC Characteristics............................................................... 20 Table 12. SYNC AC Characteristics ............................................................................................. 21 Table 13. GATEKILL to SVPWM AC Timing ............................................................................ 22 Table 14. Itrip AC Timing ............................................................................................................. 22 Table 15. Interrupt AC Timing...................................................................................................... 23 Table 16. I2C AC Timing .............................................................................................................. 24 Table 17. SPI Write AC Timing .................................................................................................... 25 Table 18. SPI Read AC Timing..................................................................................................... 26 Table 19. UART AC Timing ......................................................................................................... 27 Table 20. CAPTURE AC Timing ................................................................................................. 28 Table 21. OTP Programming Timing............................................................................................ 29 Table 22. JTAG AC Timing .......................................................................................................... 30 Table 23. Pin List .......................................................................................................................... 36 3 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 List of Figures Figure 1 Typical Application Block Diagram Using IRMCK143 ..................................................... 5 Figure 2 Pinout of IRMCK143 ........................................................................................................... 6 Figure 3 Crystal circuit example ...................................................................................................... 18 Figure 4 Voltage droop and S/H hold time ...................................................................................... 19 Figure 5 SYNC timing ..................................................................................................................... 21 Figure 6 Gatekill timing ................................................................................................................... 22 Figure 7 ITRIP timing ...................................................................................................................... 22 Figure 8 Interrupt timing .................................................................................................................. 23 Figure 9 I2C Timing ......................................................................................................................... 24 Figure 10 SPI write timing ............................................................................................................... 25 Figure 11 SPI read timing ................................................................................................................ 26 Figure 12 UART timing ................................................................................................................... 27 Figure 13 CAPTURE timing ............................................................................................................ 28 Figure 14 OTP programming timing ................................................................................................ 29 Figure 15 JTAG timing .................................................................................................................... 30 Figure 16 PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output............................. 31 Figure 17 All digital I/O except motor PWM output ....................................................................... 31 Figure 18 RESET, GATEKILL I/O ................................................................................................. 32 Figure 19 Analog input..................................................................................................................... 32 Figure 20 VPP programming pin I/O structure ................................................................................ 32 Figure 21 VDD1,VDDCAP pin I/O structure .................................................................................. 33 Figure 22 VSS,AVSS pin I/O structure............................................................................................ 33 Figure 23 XTAL0/XTAL1 pins structure ........................................................................................ 33 4 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 1 Overview IRMCK143 is a new generation International Rectifier integrated circuit device primarily designed as a one-chip solution for complete inverter controlled appliance motor control applications. Unlike a traditional microcontroller or DSP, the IRMCK143 provides a built-in closed loop sensorless control algorithm using the unique Flexible Motion Control Engine (MCETM) for permanent magnet motors as well as induction motors. The MCETM consists of a collection of control elements, motion peripherals, a dedicated motion control sequencer and dual port RAM to map internal signal nodes. IRMCK143 also employs a unique single shunt current reconstruction circuit to eliminate additional analog/digital circuitry and enables a direct shunt resistor interface to the IC. Motion control programming is achieved using a dedicated graphical compiler integrated into the MATLAB/SimulinkTM development environment. Sequencing, user interface, host communication, and upper layer control tasks can be implemented in the 8051 highspeed 8-bit microcontroller. The 8051 microcontroller is equipped with a JTAG port to facilitate emulation and debugging tools. Figure 1 shows a typical application schematic using the IRMCK143. IRMCK143 contains 32K bytes of OTP program ROM, The IRMCF143 contains 64K bytes of Flash and intended for development purposes only while the IRMCK143 is intended for volume production. Both the development and ROM versions come in a 64pin QFP package with identical pin configuration to facilitate PC board layout and transition to mass production. Host communication Galvanic isolation Appliance Inverter With PFC PFC gate drive Passive EMI Filter IRS2630D Motor (PMSM or IM) IRMCK143 Power Supply 3.3V Optional EEPROM Digial I/O Analog Input Figure 1. 5 www.irf.com 2 18 6 Typical Application Block Diagram Using IRMCK143 © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 PWMUH VPP/P1.5 PFCGKILL PFCPWM GATEKILL P3.0/CS1 TMS/P5.2 TDO/P5.3 TDI/P5.1 TCK RESET P1.1/RXD P1.2/TXD T3.4/T0 T3.5/T1 P3.3/INT1 2 PINOUT 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 XTAL0 1 48 PWMVH XTAL1 2 47 P3.6 P1.0/T2 3 46 P2.1 SCL/SDI-SDO 4 45 P3.7 SDA/CS0 5 44 PWMWH P1.3/SYNC/SCK 6 43 PWMUL P1.4/CAP 7 42 PWMVL P1.6 8 41 PWMWL P1.7 9 40 P3.1/AOPWM2 VDD1 10 IRMCK143 (Top View) 39 VSS 38 VDD1 VSS 11 VDDCAP 12 37 VDDCAP P2.0/NMI 13 36 AVSS P3.2/INT0 14 35 IPFCO P2.2 15 34 IPFC+ P2.3 16 33 IPFC- AREF CMEXT IFBO IFB+ IFB- AIN4 AIN3 AIN2 AIN1 AIN0 VAC+ VAC- VACO P2.7/AOPWM1 P2.6/AOPWM0 P2.5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 2 Pinout of IRMCK143 6 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 3 IRMCK143 Block Diagram and Main Functions IRMCK143 block diagram is shown in Figure . Mini-Motion Control Engine (MiniMCE) D/A (PWM) Speed command Capture Timer Counnter0,1,2 Watchdog Timer SND SCL SDA I2C 8bit CPU Core PORT 1 PORT 2 Digital I/Os Local RAM 2kbyte PORT 3 8bit uP Address/data bus Host Interface Program ROM/RAM 32kB UART RCV To IGBT gate drive Low Loss SVPWM Motion Control Modules Dual Port RAM 2kbyte GATEKILL Single Shunt Motor Current Reconstruction From shunt resistor PFC current sense From shunt resistor To IGBT gate drive PFCPWM GATEKILL MCE Program RAM 12kbyte Interrupt Control 8bit (8051) microcontroller 6 IFB 3 PFCIFB Motion Control Bus 2 Monitoring 3 ACV 3 A/D MUX S/H AIN0 AIN1 analog input AIN2 AIN3 AIN4 4 Emulator Debugger JTAG Motion Control Sequencer 2 Ceramic Resonator (4MHz) Freq Synthesizer 33MHz 128MHz Figure 3. IRMCK143 Block Diagram IRMCK143 contains the following functions for sensorless AC motor control applications: • 7 Motion Control Engine (MCETM) o Proportional plus Integral block o Low pass filter o Differentiator and lag (high pass filter) o Ramp o Limit o Angle estimate (sensorless control) o Inverse Clark transformation o Vector rotator www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 • 8 o Bit latch o Peak detect o Transition o Multiply-divide (signed and unsigned) o Divide (signed and unsigned) o Adder o Subtractor o Comparator o Counter o Accumulator o Switch o Shift o ATAN (arc tangent) o Function block (any curve fitting, nonlinear function) o 16 bit wide Logic operations (AND, OR, XOR, NOT, NEGATE) o MCETM program memory and dual port RAM (6K byte) o MCETM control sequencer 8051 microcontroller o Two 16 bit timer/counters o One 16 bit periodic timer o One 16 bit watchdog timer o One 16 bit capture timer o Up to 24 discrete I/Os o Eight-channel 12 bit A/D Buffered (current sensing) one channel (0 – 1.2V input) Unbuffered seven channels (0 – 1.2V input) o JTAG port (4 pins) o Up to three channels of analog output (8 bit PWM) o UART o I2C/SPI port o 32K byte OTP program ROM o 2K byte data RAM (Configurable to change the size) www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 4 Application connection and Pin function AC 230V System Clock XTAL0 XTAL1 4MHz Crystal Host Microcontroller (RS232C) P1.2/TXD P1.1/RXD SDA Other Communication (I2C) SCL Frequency Synthesizer Low Loss Space Vector PWM System clock Motion Control Modules RS232C I2C/SPI Dual Port Memory (2kB) & MCE Memory (12kB) 3.3V P1.0/T2 P1.3/SYNC P1.4/CAP PORT1 P1.6 P1.7 P2.0/NMI P2.1 Digital I/O Control P2.2 P2.3 P3.4 P3.5 PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL GATEKILL PFC PWM Motion Control Sequencer PFCPWM Single Shunt Current Sensing Shunt resistor HVIC Gate Drive IRS2630D 0.6V PORT2 IFBC+ P2.5 P3.0/INT2 P3.2/INT0 P3.3 To ACV OPamp S/H IFBCIFBCO IPFC+ PORT3 Timers S/H 0.6V IPFCIPFCO Watchdog Timer P2.6/AOPWM0 PWM0 Local RAM (2kByte) P2.7/AOPWM1 PWM1 Analog Output P3.1/AOPWM2 12bit A/D & MUX 0.6V VAC+ 4 AIN0,AIN1,AIN2, AIN3 Other analog input (0-1.2V) AREF CMEXT TCLK TDI TSM TDO RESET OTP Programming Voltage (6.5V) 3.3V Program RAM (20 - 24kByte) JTAG Interface 8051 CPU VDD1 IRMCK143 Figure 4. www.irf.com AVSS RESET VSS 9 Optional External Voltage Reference (0.6V) AVDD System Reset P1.5/VPP Motor VACOMP PWM2 JTAG Control (OTP programming & Emulation) From AC line VAC- 3.3V 1.8V Voltage Regulator VDDCAP 1.8V IRMCK143 Connection Diagram © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 4.1 8051 Peripheral Interface Group UART Interface P1.2/TXD P1.1/RXD Output, Transmit data from IRMCK171 Input, Receive data to IRMCK171 Discrete I/O Interface P1.0/T2 Input/output port 1.0, can be configured as Timer/Counter 2 input P1.1/RXD Input/output port 1.1, can be configured as RXD input P1.2/TXD Input/output port 1.2, can be configured as TXD output P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM P1.4/CAP Input/output port 1.4, can be configured as Capture Timer input VPP/P1.5 OTP programming or Input/output port 1.5 P1.6 Input/output port 1.6 P1.7 Input/output port 1.6 P2.0/NMI Input/output port 2.0, can be configured as non-maskable interrupt input P2.2 Input/output port 2.2 P2.3 Input/output port 2.3 P2.5 Input/output port 2.5 P2.6/AOPWM0 Input/output port 2.6, can be configured as AOPWM0 output P2.7/AOPWM1 Input/output port 2.7, can be configured as AOPWM1 output P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 P3.1/AOPWM2 Input/output port 3.1, can be configured as AOPWM2 output P3.2/NINT0 Input/output port 3.2, can be configured as INT0 input P3.3/NINT1 Input/output port 3.3, can be configured as INT1 input P3.4/T0 Input/output port 3.4, can be configured as T0 input for counter mode P3.5/T1 Input/output port 3.5, can be configured as T1 input for counter mode P3.6 Input/output port 3.6 P3.7 Input/output port 3.7 P5.2/TMS Input port, configured as JTAG port by default Analog Output Interface P2.6/AOPWM0 Input/output, can be configured as 8-bit PWM output 0 with programmable carrier frequency P2.7/AOPWM1 Input/output, can be configured as 8-bit PWM output 1 with programmable carrier frequency P3.1/AOPWM2 Input/output, can be configured as 8-bit PWM output 2 with programmable carrier frequency 10 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 Crystal Interface XTAL0 XTAL1 Input, connected to crystal Output, connected to crystal Reset Interface RESET Input and Output, system reset, doesn’t require external RC time constant I2C Interface SCL/SO-SI SDA/CS0 Output, I2C clock output, or SPI data Input/output, I2C Data line or SPI chip select 0 I2C/SPI Interface SCL/SO-SI Output, I2C clock output, or SPI data SDA/CS0 Input/output, I2C data line or SPI chip select 0 P1.3/SYNC/SCK Input/output port 1.3, can be configured as SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM P3.0/INT2/CS1 Input/output port 3.0, can be configured as INT2 input or SPI chip select 1 4.2 Motion Peripheral Interface Group PWM PWMUH PWMUL PWMVH PWMVL PWMWH PWMWL PFCPWM Fault GATEKILL PFCGKILL 11 www.irf.com Output, PWM phase U high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PWM phase U low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PWM phase V high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PWM phase V low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PWM phase W high side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PWM phase W low side gate signal, internally pulled down by 58kΩ, configured high true at a power up Output, PFCPWM output signal, internally pulled up by 70kΩ, configured low true at a power up Input, upon assertion, this negates all six PWM signals, programmable logic sense, internally pulled up by 70kΩ Input, upon assertion, this negates PFCPWM signal, programmable logic sense, internally pulled up by 70kΩ © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 4.3 Analog Interface Group AVSS AREF CMEXT IFB+ IFBIFBO AIN0 AIN1 AIN2 AIN3 AIN4 VAC5+ VAC5VACO IPFC+ IPFCIPFCO 4.4 Power Interface Group VDD1 VDDCAP VSS 12 Analog power return, (analog internal 1.8V power is shared with VDDCAP) 0.6V buffered output Unbuffered 0.6V, input to the AREF buffer, capacitor needs to be connected. Input, Operational amplifier positive input for shunt resistor current sensing Input, Operational amplifier negative input for shunt resistor current sensing Output, Operational amplifier output for shunt resistor current sensing Input, Analog input channel 0 (0 – 1.2V), typically configured for DC bus voltage input Input, Analog input channel 1 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 2 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 3 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Analog input channel 4 (0 – 1.2V), needs to be pulled down to AVSS if unused Input, Operational amplifier positive input for VAC channel Input, Operational amplifier negative input for VAC channel Output, Operational amplifier output for VAC output, there is a single sample/hold circuit on the output Input, Operational amplifier positive input for PFC current sensing channel Input, Operational amplifier negative input for PFC current channel Output, Operational amplifier output for PFC current sensing channel www.irf.com Digital power (3.3V) Internal 1.8V output, requires capacitors to the pin. Shared with analog power pad internally Note: The internal 1.8V supply is not designed to power any external circuits or devices. Only capacitors should be connected to this pin. Digital common © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 4.5 Test Interface Group P5.2/TMS P5.3/TDO P5.1/TDI TCK 13 www.irf.com JTAG test mode input or a general purpose I/O JTAG data output or a general purpose I/O (Only output) JTAG data input or general purpose I/O JTAG test clock © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 5 DC Characteristics 5.1 Absolute Maximum Ratings Symbol VDD1 VIA VID VPP TA TS Parameter Supply Voltage Analog Input Voltage Digital Input Voltage OTP Programming voltage Ambient Temperature Storage Temperature Table 1. Min -0.3 V -0.3 V -0.3 V -0.3V Typ - Max 3.6 V 1.98 V 6.0 V 7.0V Condition Respect to VSS Respect to AVSS Respect to VSS Respect to VSS -40 ˚C 85 ˚C -65 ˚C 150 ˚C Absolute Maximum Ratings Caution: Stresses beyond those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. 5.2 System Clock Frequency and Power Consumption CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max SYSCLK System Clock 32 128 1) PD Power consumption 160 200 Table 2. System Clock Frequency Unit MHz mW Note 1) The value is based on the condition of MCE clock=126MHz, 8051 clock 31.5MHz with a actual motor running by a typical MCE application program and 8051 code. 14 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 5.3 Digital I/O DC Characteristics Symbol VDD1 VPP VIL VIH CIN IL IOL1(2) IOH1 (2) IOL2(3) IOH2(3) Parameter Supply Voltage OTP Programming voltage Input Low Voltage Input High Voltage Input capacitance Input leakage current Low level output current High level output current Low level output current High level output current Table 3. Min 3.0 V 6.70V Typ 3.3 V 6.75V Max 3.6 V 6.80V Condition Recommended Recommended -0.3 V 2.0 V - - 0.8 V 3.6 V ±1 μA 15.2 mA Recommended Recommended 8.9 mA 3.6 pF ±10 nA 13.2 mA (1) VO = 3.3 V or 0 V VOL = 0.4 V (1) 12.4 mA 24.8 mA 38 mA VOH = 2.4 V (1) 17.9 mA 26.3 mA 33.4 mA VOL = 0.4 V (1) 24.6 mA 49.5 mA 81 mA VOH = 2.4 V (1) Digital I/O DC Characteristics Note: (1) Data guaranteed by design. (2) Applied to SCL/SO-SI, SDA/CS0 pins. (3) Applied to all digital I/O pins except SCL/SO-SI and SDA/CS0 pins. 15 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 5.4 Analog I/O DC Characteristics - OP amp for current sensing (IFB+, IFB-, IFBO) CAREF = 1nF, CMEXT= 100nF. VDD1=3.3V, Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max VOFFSET Input Offset Voltage 26 mV VI Input Voltage Range 0V 1.2 V VOUTSW OP amp output 50 mV 1.2 V (1) operating range CIN Input capacitance 3.6 pF RFDBK OP amp feedback 5 kΩ 20 kΩ resistor OP GAINCL CMRR ISRC ISNK Operating Close loop 80 db Gain Common Mode 80 db Rejection Ratio Op amp output source 1 mA current Op amp output sink 100 μA current Table 4. Analog I/O DC Characteristics Condition VAVDD = 1.8 V Recommended VAVDD = 1.8 V (1) Requested between IFBO and IFB(1) (1) VOUT = 0.6 V (1) VOUT = 0.6 V (1) Note: (1) Data guaranteed by design. 16 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 5.5 Under Voltage Lockout DC characteristics Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max UVCC+ UVcc positive going 2.78 V 3.04 V 3.13 V Threshold UVCCUVcc negative going 2.78 V 2.97 V 3.13 V Threshold UVCCH UVcc Hysteresys 73 mV Table 5. UVcc DC Characteristics 5.6 Itrip comparator DC characteristics Unless specified, VDD1=3.3V, Ta = 25˚C. Symbol Parameter Min Typ Max Itrip+ Itrip positive going 1.22V Threshold ItripItrip negative going 1.10V Threshold ItripH Itrip Hysteresys 120mV Table 6. Itrip DC Characteristics 5.7 Condition Condition VDD1 = 3.3 V VDD1 = 3.3 V CMEXT and AREF Characteristics CAREF = 1nF, CMEXT= 100nF. Unless specified, Ta = 25˚C. Condition Symbol Parameter Min Typ Max VCM CMEXT voltage 495 mV 600 mV 700 mV VAVDD = 1.8 V VAREF Buffer Output Voltage 495 mV 600 mV 700 mV VAVDD = 1.8 V (1) Load regulation (V 1 mV ∆Vo DC 0.6) (1) PSRR Power Supply Rejection 75 db Ratio Table 7. CMEXT and AREF DC Characteristics 17 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 6 AC Characteristics 6.1 Digital PLL AC Characteristics Symbol FCLKIN FPLL FLWPW JS D TLOCK Parameter Min Typ Max Condition (1) Crystal input 3.2 MHz 4 MHz 60 MHz frequency (see figure below) Internal clock 32 MHz 50 MHz 128 MHz (1) frequency (1) Sleep mode output FCLKIN ÷ 256 frequency (1) Short time jitter 200 psec (1) Duty cycle 50 % PLL lock time 500 μsec (1) Table 8. PLL AC Characteristics Note: (1) Data guaranteed by design. R1=1M R2=1K Xtal C1=30PF C2=30PF Figure 3. 18 www.irf.com Crystal circuit example © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 6.2 Analog to Digital Converter AC Characteristics Unless specified, Ta = 25˚C. Symbol Parameter TCONV Conversion time THOLD Sample/Hold maximum hold time Table 9 . Min - Typ - Max 2.05 μsec 10 μsec Condition (1) Voltage droop ≤ 15 LSB (see figure below) A/D Converter AC Characteristics Note: (1) Data guaranteed by design. Input Voltage Voltage droop S/H Voltage tSAMPLE THOLD Figure 4 Voltage droop and S/H hold time 19 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 6.3 Op amp AC Characteristics - OP amp for current sensing (IFB+, IFB-, IFBO) Unless specified, Ta = 25˚C. Symbol Parameter OPSR OP amp slew rate OPIMP TSET OP input impedance Settling time Table 10. Min - Typ 10 V/μsec Max - - 108 Ω 400 ns - Condition VAVDD = 1.8 V, CL = 33 pF (1) (1) VAVDD = 1.8 V, CL = 33 pF (1) Current Sensing OP Amp AC Characteristics Note: (1) Data guaranteed by design. 20 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 6.4 SYNC to SVPWM and A/D Conversion AC Timing twSYNC SYNC tdSYNC1 IU,IV,IW tdSYNC2 AINx tdSYNC3 PWMUx,PWMVx,PWMWx Figure 5 SYNC timing Unless specified, Ta = 25˚C. Symbol Parameter twSYNC SYNC pulse width tdSYNC1 SYNC to current feedback conversion time tdSYNC2 SYNC to AIN0-6 analog input conversion time tdSYNC3 SYNC to PWM output delay time Table 11. Min - Typ 32 - Max 100 Unit SYSCLK SYSCLK - - 200 SYSCLK (1) - - 2 SYSCLK SYNC AC Characteristics Note: (1) AIN1 through AIN6 channels are converted once every 6 SYNC events 21 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 6.5 GATEKILL to SVPWM AC Timing twGK GATEKILL tdGK PWMUx,PWMVx,PWMWx Figure 6 Gatekill timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max twGK GATEKILL pulse 32 width tdGK GATEKILL to PWM 100 output delay Table 12. GATEKILL to SVPWM AC Timing 6.6 Unit SYSCLK SYSCLK Itrip AC Timing Itrip tItrip PWMUH,PWMUL, PWMVH,PWMVH, PWMWH,PWMWL Figure 7 ITRIP timing Unless specified, Ta = 25˚C. Symbol Parameter tITRIP Itrip propagation delay Min Table 13. 22 www.irf.com Typ - Max 100(sysclk)+1.0usec Unit SYSCLK+usec Itrip AC Timing © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 6.7 Interrupt AC Timing twINT P3.2/INT0 P3.3/INT1 tdINT Internal Program Counter Internal Vector Fetch Figure 8 Interrupt timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max twINT INT0, INT1 Interrupt 4 Assertion Time tdINT INT0, INT1 latency 4 Table 14. Interrupt AC Timing 23 www.irf.com Unit SYSCLK SYSCLK © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 6.8 I2C AC Timing TI2CLK TI2CLK SCL tI2ST1 tI2WSETUP tI2WHOLD tI2RSETUP tI2EN1 tI2RHOLD tI2ST2 tI2EN2 SDA Figure 9 I2C Timing Unless specified, Ta = 25˚C. Symbol Parameter 2 TI2CLK I C clock period tI2ST1 I2C SDA start time tI2ST2 I2C SCL start time tI2WSETUP I2C write setup time tI2WHOLD I2C write hold time tI2RSETUP I2C read setup time tI2RHOLD I2C read hold time Min Typ 10 0.25 0.25 0.25 0.25 2 (1) I C filter time 1 2 Table 15. I C AC Timing Max 8192 - Unit SYSCLK TI2CLK TI2CLK TI2CLK TI2CLK SYSCLK SYSCLK Note: (1) I2C read setup time is determined by the programmable filter time applied to I2C communication. 24 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 6.9 SPI AC Timing 6.9.1 SPI Write AC timing TSPICLK P1.3/SYNC/SCK tSPICLKHT tWRDELAY SCL/SO-SI Bit7(MSB) tSPICLKLT Bit0(LSB) tCSDELAY tCSHOLD tCSHIGH SDA/CS0 P3.0/INT2/CS1 Figure 10 SPI write timing Unless specified, Ta = 25˚C. Symbol Parameter TSPICLK SPI clock period tSPICLKHT SPI clock high time tSPICLKLT SPI clock low time tCSDELAY CS to data delay time tWRDELAY CLK falling edge to data delay time tCSHIGH CS high time between two consecutive byte transfer tCSHOLD CS hold time Table 16. 25 www.irf.com Min 4 - Typ 1/2 1/2 - Max 10 10 Unit SYSCLK TSPICLK TSPICLK nsec nsec 1 - - TSPICLK 1 SPI Write AC Timing TSPICLK © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 6.9.2 SPI Read AC Timing TSPICLK P1.3/SYNC/SCK tRDHOLD tSPICLKHT tSPICLKLT tRDSU SCL/SO-SI Bit7(MSB) Bit0(LSB) tCSRD tCSHOLD tCSHIGH SDA/CS0 P3.0/INT2/CS1 Figure 11 SPI read timing Unless specified, Ta = 25˚C. Symbol Parameter TSPICLK SPI clock period tSPICLKHT SPI clock high time tSPICLKLT SPI clock low time tCSRD CS to data delay time tRDSU SPI read data setup time tRDHOLD SPI read data hold time tCSHIGH CS high time between two consecutive byte transfer tCSHOLD CS hold time Table 17. 26 www.irf.com Min 4 10 10 1 Typ 1/2 1/2 - Max 10 - 1 SPI Read AC Timing Unit SYSCLK TSPICLK TSPICLK nsec nsec nsec TSPICLK TSPICLK © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 6.10 UART AC Timing TBAUD TXD Start Bit Data and Parity Bit Stop Bit RXD TUARTFIL Figure 12 UART timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ TBAUD Baud Rate Period 57600 TUARTFIL UART sampling filter 1/16 (1) period Table 18. UART AC Timing Max - Unit bit/sec TBAUD Note: (1) Each bit including start and stop bit is sampled three times at center of a bit at an interval of 1/16 TBAUD. If three sampled values do not agree, then UART noise error is generated. 27 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 6.11 CAPTURE Input AC Timing TCAPCLK tCAPHIGH P1.4/CAP tCAPLOW tCRDELAY CREV(H,L) Internal register tCLDELAY CLAST(H,L) Internal register tINTDELAY Interrupt Vector Fetch Interrupt Figure 13 CAPTURE timing Unless specified, Ta = 25˚C. Symbol Parameter Min Typ Max TCAPCLK CAPTURE input 8 period tCAPHIGH CAPTURE input high 4 time tCAPLOW CAPTURE input low 4 time tCRDELAY CAPTURE falling edge 4 to capture register latch time tCLDELAY CAPTURE rising edge 4 to capture register latch time tINTDELAY CAPTURE input 4 interrupt latency time Table 19. CAPTURE AC Timing 28 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback Unit SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK May 28, 2014 IRMCK143 6.12 OTP Programming Timing 6.75V VDD/VSS/Floating VDD/VSS/Floating VPP TVPS TVPH TCK TDI/TMS Figure 14 OTP programming timing Unless specified, Ta = 25˚C. Symbol Parameter TVPS VPP Setup Time TVPH VPP Hold Time Table 20. 29 www.irf.com Min Typ Max 10 15 OTP Programming Timing © 2014 International Rectifier Submit Datasheet Feedback Unit nsec nsec May 28, 2014 IRMCK143 6.13 JTAG AC Timing TJCLK TCK tJHIGH tJLOW tCO TDO tJSETUP tJHOLD TDI/TMS Figure 15 JTAG timing Unless specified, Ta = 25˚C. Symbol Parameter TJCLK TCK Period tJHIGH TCK High Period tJLOW TCK Low Period tCO TCK to TDO propagation delay time tJSETUP TDI/TMS setup time tJHOLD TDI/TMS hold time Table 21. 30 www.irf.com Min 10 10 0 Typ - 4 0 JTAG AC Timing Max 50 5 Unit MHz nsec nsec nsec - nsec nsec © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 7 I/O Structure The following figure shows the motor PWM output (PWMUH/PWMUL/PWMVH/PWMVL/PWMWH/PWMWL) VDD1 (3.3V) Internal digital circuit High true logic 6.0V PIN 270 Ω 6.0V 58k Ω VSS Figure 16 PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output The following figure shows the digital I/O structure except the motor PWM output VDD1 (3.3V) Internal digital circuit Low true logic 70k Ω 6.0V PIN 270 Ω 6.0V VSS Figure 17 All digital I/O except motor PWM output 31 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 The following figure shows RESET and GATEKILL I/O structure. VDD1 (3.3V) RESET GATEKILL circuit 70k Ω 6.0V PIN 270 Ω 6.0V VSS Figure 18 RESET, GATEKILL I/O The following figure shows the analog input structure. VDDCAP(1.8V) Analog input 6.0V PIN 1 Ω Analog Circuit 6.0V AVSS Figure 19 Analog input The following figure shows the VPP pin I/O structure PIN 270 Ω 8.0V VSS Figure 20 VPP programming pin I/O structure The following figure shows the VDD1,VDDCAP pin I/O structure 32 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 PIN 6.0V VSS Figure 21 VDD1,VDDCAP pin I/O structure The following figure shows the VSS,AVSS pin I/O structure VDD1 AVDD PIN 6.0V Figure 22 VSS,AVSS pin I/O structure The following figure shows the XTAL0 and XTAL1 pins structure VDDCAP(1.8V) 6.0V PIN 1 Ω 6.0V VSS Figure 23 33 www.irf.com XTAL0/XTAL1 pins structure © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 8 Pin List Pin Number 34 Pin Name Internal Pull-up /Pull-down Pin Type 1 2 3 XTAL0 XTAL1 P1.0/T2 I O I/O 4 SCL/SO-SI I/O 5 SDA/CS0 I/O 6 P1.3/SYNC/SCK I/O 7 8 9 10 11 12 13 P1.4/CAP P1.6 P1.7 VDD1 VSS VDDCAP P2.0/NMI I/O I/O 14 15 16 17 18 P3.2/INT0 P2.2 P2.3 P2.5 P2.6/AOPWM0 I/O I/O I/O I/O I/O 19 P2.7/AOPWM1 I/O 20 21 22 23 VACO VACVAC+ AIN0 O I I I 24 AIN1 I 25 AIN2 I www.irf.com P P P I/O Description Crystal input Crystal output Discrete programmable I/O or Timer/Counter 2 input 2 I C clock output (open drain, need pull up) or SPI data 2 I C data (open drain, need pull up) or SPI Chip Select 0 Discrete programmable I/O or SYNC output or SPI clock output, needs to be pulled up to VDD1 in order to boot from I2C EEPROM Discrete programmable I/O or Capture timer input Discrete programmable I/O Discrete programmable I/O 3.3V digital power Digital common Internal 1.8V output, Capacitor(s) to be connected Discrete programmable I/O or Non-maskable Interrupt input Discrete programmable I/O or Interrupt 0 input Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O or PWM 0 digital output Discrete programmable I/O or PWM 1 digital output AC line voltage sensing OP amp output AC line voltage sensing OP amp input (-) AC line voltage sensing OP amp input (+) Analog input channel 0, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 1, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 2, 0-1.2V range, needs to be pulled down to AVSS if unused © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 Pin Number 35 Pin Name Internal Pull-up /Pull-down Pin Type 26 AIN3 I 27 AIN4 I 28 29 30 31 IFBIFB+ IFBO CMEXT I I O O 32 33 AREF IPFC- O I 34 IPFC+ I 35 IPFCO O 36 37 38 39 40 AVSS VDDCAP VDD1 VSS P3.1/AOPWM2 41 PWMWL 42 PWMVL 43 PWMUL 44 PWMWH 45 46 47 48 P3.7 P2.1 P3.6 PWMVH 49 PWMUH 50 P1.5/VPP www.irf.com P P P P I/O 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down 58 kΩ Pull down O O O O I/O I/O I/O O O I/O P Description Analog input channel 3, 0-1.2V range, needs to be pulled down to AVSS if unused Analog input channel 4, 0-1.2V range, needs to be pulled down to AVSS if unused Single shunt current sensing OP amp input (-) Single shunt current sensing OP amp input (+) Single shunt current sensing OP amp output Unbuffered 0.6V output. Capacitor needs to be connected. Analog reference voltage output (0.6V) PFC current sensing OP amp input -, 0-1.2V range, needs to be pulled down to AVSS if unused PFC current sensing OP amp input +, 0-1.2V range, needs to be pulled down to AVSS if unused PFC current sensing OP amp output, 0-1.2V range, Analog common Internal 1.8V output, Capacitor(s) to be connected 3.3V digital power Digital common Discrete programmable I/O or PWM 2 digital output PWM gate drive for phase W low side, configurable either high or low true. PWM gate drive for phase V low side, configurable either high or low true PWM gate drive for phase U low side, configurable either high or low true PWM gate drive for phase W high side, configurable either high or low true Discrete programmable I/O Discrete programmable I/O Discrete programmable I/O PWM gate drive for phase V high side, configurable either high or low true PWM gate drive for phase U high side, configurable either high or low true OTP programming power (6.75V) or Discrete programmable I/O. © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 Pin Number 36 Pin Name Internal Pull-up /Pull-down Pin Type 51 PFCPWM 52 PFCGKILL 53 GATEKILL 54 P3.0/INT2/CS1 55 56 57 58 59 60 P5.2/TMS P5.3/TDO P5.1/TDI TCK RESET P1.1/RXD I/O I/O I/O I I/O I/O 61 P1.1/RXD I/O 62 P3.4/T0 I/O 63 P3.5/T1 I/O 64 P3.3/INT1 www.irf.com I/O 70 kΩ Pull up 70 kΩ Pull up 70 kΩ Pull up I I I/O I/O Table 22. Description PFC PWM gate drive , configurable either high or low PFCPWM shutdown input, active low input. PWM shutdown input, 2-μsec digital filter, active low input. Discrete programmable I/O or external interrupt 2 input or SPI Chip Select 1 JTAG test mode select or Discrete I/O JTAG test data output or digital input JTAG test data input or Discrete I/O JTAG test clock Reset, low true, Schmitt trigger input UART receiver input or Discrete programmable I/O UART transmitter output or Discrete programmable I/O Discrete programmable I/O or Timer/Counter 2 input Discrete programmable I/O or Timer/Counter 2 input Interrupt 1 input or Discrete I/O Pin List © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 9 Package Dimensions 37 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 38 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 10 Part Marking Information IRMCK143 Part Number IR Logo YWWP Date Code XXXXXX Production Lot Pin 1 Indentifier 11 Qualification Information †† Qualification Level Industrial (per JEDEC JESD 47E) Moisture Sensitivity Level MSL3††† (per IPC/JEDEC J-STD-020C) Machine Model Class B (per JEDEC standard JESD22-A114D) Human Body Model Class 2 (per EIA/JEDEC standard EIA/JESD22-A115-A) ESD RoHS Compliant 39 Yes † Qualification standards can be found at International Rectifier’s web site http://www.irf.com/ †† Higher qualification ratings may be available should the user have such requirements. contact your International Rectifier sales representative for further information. ††† Higher MSL ratings may be available for the specific package types listed here. International Rectifier sales representative for further information. www.irf.com Please Please contact your © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014 IRMCK143 Data and Specifications are subject to change without notice IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information 40 www.irf.com © 2014 International Rectifier Submit Datasheet Feedback May 28, 2014