HD74LS190 Synchronous Up / Down Decade Counter (signal clock line) REJ03D0452–0200 Rev.2.00 Jul.15.2005 Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered on a low-to-high-level transition of the clock input if the enable input is low. A high at the enable input inhibits counting. Level changes at the enable input should be made only when the clock input is high. The direction of the count is determined by the level of the down / up input. When low, the counter counts up and when high, it counts down. Level changes at the down / up input should be made only when the clock input is high. This counter is fully programmable; that is, the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. The clock, down / up, and load inputs are buffered to lower the drive requirement which significantly reduces the number of clock drivers, etc., required for long parallel words. Two outputs have been made available to perform the cascading function: ripple clock and maximum / minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycles to the clock when the counter overflows or underflows. The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow conditions exists. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum / minimum count output can be used to accomplish look-ahead for high-speed operation. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS190P DILP-16 pin PRDP0016AE-B (DP-16FV) P — PRSP0016DH-B FP (FP-16DAV) Notes: Please consult the sales office for the above package availability. HD74LS190FPEL SOP-16 pin (JEITA) Rev.3.00, Jul.15.2005, page 1 of 10 EL (2,000 pcs/reel) HD74LS190 Pin Arrangement Data B Input 1 QB 2 QB QA 3 QA Enable G 4 G Down/Up 5 QC 16 VCC 15 Data A CK 14 Clock Ripple Clock 13 Ripple Clock Dn/Up Max/ Min 12 Max/Min 6 QC Load 11 Load QD 7 QD C 10 Data C GND 8 9 Data D B A Outputs Inputs Inputs Outputs Outputs D (Top view) Rev.3.00, Jul.15.2005, page 2 of 10 Inputs HD74LS190 Block Diagram Clock Ripple Clock Down/Up Max/Min Output Data Input A Preset J QA Output QA CK Enable G K QA Clear Data Input B Preset J QB Output QB CK K QB Clear Data Input C Preset J QC Output QC CK K QC Clear Data Input D Preset J QD Output QD CK K QD Clear Load Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage VCC 7 V Input voltage VIN 7 V PT 400 mW Tstg –65 to +150 °C Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Rev.3.00, Jul.15.2005, page 3 of 10 HD74LS190 Recommended Operating Conditions Item Symbol Min Typ Max Unit VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA Operating temperature Topr –20 25 75 °C Clock frequency ƒclock 0 — 20 MHz Clock pulse width tw (CK) 25 — — ns Load pulse width tw (Load) 35 — — ns Setup time tsu 20 — — ns Hold time th (data) 3 — — ns Enable time tenable 40 — — ns Supply voltage Output current Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL VOH Output voltage VOL Input current Enable Others Enable Others Enable Others IIH IIL II min. 2.0 — typ.* — — max. — 0.8 Unit V V 2.7 — — V — — — — — — — — — — — — — — — — 0.4 0.5 60 20 –1.2 –0.4 0.3 0.1 V VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µΑ IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA µA VCC = 5.25 V, VI = 2.7 V mA VCC = 5.25 V, VI = 0.4 V mA VCC = 5.25 V, VI = 7 V Short-circuit output IOS –20 — –100 mA current Supply current** ICC — 20 35 mA Input clamp voltage VIK — — –1.5 V Notes: * VCC = 5 V, Ta = 25°C ** ICC is measured with all outputs open and all inputs grounded. Rev.3.00, Jul.15.2005, page 4 of 10 Condition VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA HD74LS190 Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol Inputs Outputs min. typ. max. Unit ƒmax Clock QA, QB, QC, QD 20 25 — MHz Load QA, QB, QC, QD A, B, C, D QA, QB, QC, QD Clock Ripple Clock Clock QA, QB, QC, QD Clock Max / Min Down / Up Ripple Clock Down / Up Max / Min Enable Ripple Clock — — — — — — — — — — — — — — — 22 33 20 27 13 16 16 24 28 37 30 30 21 22 21 33 50 32 40 20 24 24 36 42 52 45 45 33 33 33 — 22 33 tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Rev.3.00, Jul.15.2005, page 5 of 10 Condition ns ns ns ns ns ns ns ns CL = 15 pF, RL = 2 kΩ HD74LS190 Count Sequences Load A B C D Clock Down/Up Enable G QA QB QC QD Max/Min Ripple Clock 7 8 9 0 Count Up 1 2 2 2 1 Inhibit Load Illustrated below is the following sequence: 1. Load (preset) to BCD seven. 2. Count up to eight, nine (maximum), zero, one and two. 3. Inhibit 4. Count down to one, zero (minimum), nine, eight, and seven. Rev.3.00, Jul.15.2005, page 6 of 10 0 9 8 Count Down 7 HD74LS190 Testing Method Test Circuit VCC Output 4.5V RL Ripple Clock Enable Down/Up Clock See Testing Table Input P.G. Zout = 50Ω Load circuit 1 CL Output Max/Min Same as Load Circuit 1. Output A B QA Same as Load Circuit 1. Output C D Load QB Same as Load Circuit 1. Output QC Same as Load Circuit 1. Output QD Notes: Same as Load Circuit 1. 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Waveforms 1 tTHL tTLH 3V 90% 1.3V Data Input 90% 1.3V 10% 10% tsu 0V tsu 3V Load Input 1.3V 10% 90% tTLH 1.3V 10% 90% 0V tTLH VOH Output Q VOL Note: Input pulse: tTLH, tTHL ≤ 10 ns, PRR = 1 MHz, duty cycle ≤ 50% Rev.3.00, Jul.15.2005, page 7 of 10 HD74LS190 Waveforms 2 Load→Q, Data→Q 3V Load 1.3V 1.3V 0V 3V 1.3V Data (A to D) 1.3V 0V VOH Output Q 1.3V 1.3V 1.3V 1.3V VOL tPHL tPLH Note: tPLH tPHL Conditions on other inputs are irrelevant. Waveforms 3 G→Ripple CK, CK→Ripple CK, Down / Up→Ripple CK, Down / Up→Max / Min 3V Load 0V 3V Down/Up 1.3V 1.3V 0V 3V Clock 1.3V 1.3V 0V 3V G 0V tPHL tPLH tPHL tPLH VOH Ripple/Clock 1.3V 1.3V 1.3V 1.3V VOL tPLH tPHL VOH Max/Min 1.3V 1.3V VOL Note: All data inputs are low. Rev.3.00, Jul.15.2005, page 8 of 10 HD74LS190 Waveforms 4 Clock→Q 3V Load 0V 3V Data 0V 3V Down/Up 0V 3V Clock 1.3V 1.3V 0V VOH Q Enable = 0V Notes: 1.3V 1.3V tPLH tPHL VOL 1. When test the QA, QB, and QC outputs, data inputs A, B and C are shown by the solid line, and data input D is shown by the dashed line. 2. When test the QD output, data inputs A and D are shown by the solid line, and data inputs B and C are held at the low logic level. Waveforms 5 Clock→Max / Min 3V Load 0V 3V A 0V Inputs 3V B, C, D 0V 3V Down/Up 0V 3V Clock 1.3V 1.3V 1.3V 1.3V 0V VOH Max/Min Enable = 0V 1.3V 1.3V 1.3V VOL tPLH Note: 1.3V tPHL tPLH tPHL Data inputs B and C are shown by the dashed line. Data input D is shown by the solid line. Rev.3.00, Jul.15.2005, page 9 of 10 HD74LS190 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 0.20 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.3.00, Jul.15.2005, page 10 of 10 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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