DATASHEET Dual/n-Phase Buck PWM Controller with Integrated Drivers ISL8120 Features The ISL8120 integrates two voltage-mode PWM leading-edge modulation control with input feed-forward synchronous buck PWM controllers to control a dual independent voltage regulator or a 2-phase single output regulator. It also integrates current sharing control for the power module to operate in parallel, which offers high system flexibility. • Wide VIN Range Operation: 3V to 22V - VCC Operation from 3V to 5.60V The ISL8120 integrates an internal linear regulator, which generates VCC from input rail for applications with only one single supply rail. The internal oscillator is adjustable from 150kHz to 1.5MHz, and is able to synchronous to an external clock signal for frequency synchronization and phase paralleling applications. Its PLL circuit can output a phase-shift-programmable clock signal for the system to be expanded to 3-, 4-, 6-, 12- phases with desired interleaving phase shift. • Programmable Phase Shift for 1-, 2-, 3-, 4-, 6-, up to 12-Phase Applications The ISL8120’s Fault Hand Shake feature protects any channel from overloading/stressing due to system faults or phase failure. The undervoltage fault protection features are also designed to prevent a negative transient on the output voltage during falling down. This eliminates the Schottky diode that is used in some systems for protecting the load device from reversed output voltage damage. • Excellent Output Voltage Regulation: 0.6V ±0.6%/±0.9% Internal Reference Over Commercial/Industrial Temperature • Frequency Synchronization • Fault Hand Shake Capability for High System Reliability • Digital Soft-Start with Pre-Charged Output Start-up Capability • Dual Independent Channel Enable Inputs with Precision Voltage Monitor and Voltage Feed-forward Capability - Programmable Input Voltage POR and its Hysteresis with a Resistor Divider at EN Input • Extensive Circuit Protection Functions: Output Overvoltage, Undervoltage, Overcurrent protection, Over temperature and Pre-Power-On-Reset Overvoltage Protection Option Applications • Power Supply for Datacom/Telecom and POL Related Literature • Paralleling Power Module • Technical Brief TB389 “PCB Land Pattern Design and Surface Mount Guidelines for QFN (MLFP) Packages” • DDR I and II Applications • Wide and Narrow Input Voltage Range Buck Regulators • High Current Density Power Supplies • Multiple Outputs VRM and VRD Channels 1 and 2 Gate Drive PVCC 3Ω BOOTn UGATEn PWMn 10kΩ GATE CONTROL LOGIC FAULT LOGIC SHOOTTHROUGH PROTECTION PHASEn 10kΩ LGATEn FIGURE 1. INTEGRATED DRIVER BLOCK DIAGRAM February 9, 2015 FN6641.2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2008, 2009, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL8120 Pin Configuration FB1 VMON1 VSEN1- VSEN1+ ISEN1B ISEN1A VCC BOOT1 ISL8120 (32 LD QFN) TOP VIEW 32 31 30 29 28 27 26 25 COMP1 1 24 UGATE1 ISET 2 23 PHASE1 ISHARE 3 22 LGATE1 EN/VFF1 4 21 PVCC 33 GND FSYNC 5 20 LGATE2 EN/VFF2 6 19 PHASE2 CLKOUT/REFIN 7 18 UGATE2 17 BOOT2 9 10 11 12 13 14 15 16 COMP2 FB2 VMON2 VSEN2- VSEN2+ ISEN2B ISEN2A VIN PGOOD 8 Functional Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1, 9 COMP1, COMP2 These pins are the error amplifier outputs. They should be connected to FB1, FB2 pins through desired compensation networks when both channels are operating independently. When VSEN1-, VSEN2- are pulled within 400mV of VCC, the corresponding error amplifier is disabled and its output (COMP pin) is high impedance. Thus, in multiphase operations, all other SLAVE phases’ COMP pins can tie to the MASTER phase’s COMP1 pin (1st phase), which modulates each phase’s PWM pulse with a single voltage feedback loop. While the error amplifier is not disabled, an independent compensation network is required for each cascaded IC. 2 ISET This pin sources a 15µA offset current plus the average current of both channels in multiphase mode or only Channel 1’s current in independent mode. The voltage (VISET) set by an external resistor (RISET) represents the average current level of the local active channel(s). 3 ISHARE This pin is used for current sharing purposes and is configured to current share bus representing all modules’ average current. It sources 15µA offset current plus the average current of both channels in multiphase mode or Channel 1’s current in independent mode. The share bus (ISHARE pins connected together) voltage (VISHARE) set by an external resistor (RISHARE) represents the average current level of all ISL8120 controller connected to current share bus. The ISHARE bus voltage compares with ISET voltage to generates current share error signal for current correction block of each cascaded controller. The share bus impedance RISHARE should be set as RISET/NCTRL (RISET divided by number of ISL8120 in current sharing controllers). There is a 1.2V threshold for average overcurrent protection on this pin. VISHARE is compared with a 1.2V threshold for average overcurrent protections. For full-scale current, RISHARE should be 1.2V/123µA = ~10k. Typically 10k is used for RSHARE and RSET. 4, 6 EN/VFF1, EN/VFF2 These pins have triple functions. The voltage on EN/FF_ pin is compared with a precision 0.8V threshold for system enable to initiate soft-start. With a voltage lower than the threshold, the corresponding channel can be disabled independently. By connecting these pins to the input rail through a voltage resistor divider, the input voltage can be monitored for UVLO (undervoltage lockout) function. The undervoltage lockout and its hysteresis levels can be programmed by these resistor dividers. The voltages on these pins are also fed into the controller to adjust the sawtooth amplitude of each channel independently to realize the feed-forward function. Furthermore, during fault (such as overvoltage, overcurrent, and over-temperature) conditions, these pins (EN/FF_) are pulled low to communicate the information to other cascaded ICs. Submit Document Feedback 2 FN6641.2 February 9, 2015 ISL8120 Functional Pin Descriptions (Continued) PIN NUMBER SYMBOL DESCRIPTION 5 FSYNC The oscillator switching frequency is adjusted by placing a resistor (RFS) from this pin to GND. The internal oscillator will lock to an external frequency source if this pin is connected to a switching square pulse waveform, typically the CLKOUT input signal from another ISL8120 or an external clock. The internal oscillator synchronizes with the leading edge of the input signal. 7 CLKOUT/REFIN This pin has a dual function depending on the mode in which the chip is operating. It provides a clock signal to synchronize with other ISL8120(s) with its VSEN2- pulled within 400mV of VCC for multiphase (3-, 4-, 6-, 8-, 10-, or 12phase) operation. When the VSEN2- pin is not within 400mV of VCC, ISL8120 is in dual mode (dual independent PWM output). The clockout signal of this pin is not available in this mode, but the ISL8120 can be synchronized to external clock. In dual mode, this pin works as the following two functions: 1. An external reference (0.6V target only) can be in place of the Channel 2’s internal reference through this pin for DDR/tracking applications (see “DDR and Dual Mode Operation” on page 35). 2. The ISL8120 operates as a dual-PWM controller for two independent regulators with selectable phase degree shift, which is programmed by the voltage level on REFIN (see “DDR and Dual Mode Operation” on page 35). 8 PGOOD Provides an open drain Power-Good signal when both channels are within 9% of the nominal output regulation point with 4% hysteresis (13%/9%) and soft-start complete. PGOOD monitors the outputs (VMON1/2) of the internal differential amplifiers. 32, 10 FB1, FB2 These pins are the inverting inputs of the error amplifiers. These pins should be connected to VMON1, VMON2 with the compensation feedback network. No direct connection between FB and VMON pins is allowed. With VSEN2- pulled within 400mV of VCC, the corresponding error amplifier is disabled and the amplifier’s output is high impedance. FB2 is one of the two pins to determine the relative phase relationship between the internal clock of both channels and the CLKOUT signal. See Table 1 on page 22. 31, 11 VMON1, VMON2 These pins are outputs of the unity gain amplifiers. They are connected internally to the OV/UV/PGOOD comparators. These pins should be connected to the FB1, FB2 pins by a standard feedback network when both channels are operating independently. When VSEN1-, VSEN2- are pulled within 400mV of VCC, the corresponding differential amplifier is disabled and its output (VMON pin) is high impedance. In such an event, the VMON pin can be used as an additional monitor of the output voltage with a resistor divider to protect the system against single point of failure, which occurs in the system using the same resistor divider for both of the UV/OV comparator and output voltage feedback. 30, 12 VSEN1-, VSEN2- These pins are the negative inputs of standard unity gain operational amplifier for differential remote sense for the corresponding regulator (Channels 1and 2), and should be connected to the negative rail of the load/processor. When VSEN1-, VSEN2- are pulled within 400mV of VCC, the corresponding error amplifier and differential amplifier are disabled and their outputs are high impedance. Both VSEN2+ and FB2 input signal levels determine the relative phases between the internal controllers as well as the CLKOUT signal. See Table 1 on page 22. When configured as multiple power modules (each module with independent voltage loop) operating in parallel, in order to implement the current sharing control, a resistor (100 typ.) needs to be inserted between the VSEN1- pin and the output voltage negative sense point (between VSEN1- and lower voltage sense resistor), as shown in the “Typical Application Circuits” “Multiple Power Modules in Parallel with Current Sharing Control” on page 13. This introduces a correction voltage for the modules with lower load current to keep the current distribution balanced among modules. The module with the highest load current will automatically become the master module. The recommended value for the VSEN1- resistor is 100 and it should not be large in order to keep the unit gain amplifier input impedance compatibility. 29, 13 VSEN1+, VSEN2+ These pins are the positive inputs of the standard unity gain operational amplifier for differential remote sense for the corresponding channel (Channels 1 and 2), and should be connected to the positive rail of the load/processor. These pins can also provide precision output voltage trimming capability by pulling a resistor from this pin to the positive rail of the load (trimming down) or the return (typical VSEN1-, VSEN2- pins) of the load (trimming up). The typical input impedance of VSEN+ with respect to VSEN- is 600k. By setting the resistor divider connected from the output voltage to the input of the differential amplifier, the desired output voltage can be programmed. To minimize the system accuracy error introduced by the input impedance of the differential amplifier, a resistor below 1k is recommended to be used for the lower leg (ROS) of the feedback resistor divider. With VSEN2- pulled within 400mV of VCC, the corresponding error amplifier is disabled and VSEN2+ is one of the two pins to determine the relative phase relationship between the internal clock of both channels and the CLKOUT signal. See Table 1 on page 22 for details. 28, 14 ISEN1B, ISEN2B These pins are the inverting (-) inputs of the current sensing amplifiers to provide rDS(ON), DCR, or precision resistor current sensing together with the ISEN1A, ISEN2A pins. Refer to “Typical Application Circuits” “2-Phase Operation with DCR Sensing” on page 7 for DCR sensing set up and “2-Phase Operation with rDS(ON) Sensing” on page 8 for rDS(ON) sensing set up. Submit Document Feedback 3 FN6641.2 February 9, 2015 ISL8120 Functional Pin Descriptions (Continued) PIN NUMBER SYMBOL 27, 15 ISEN1A, ISEN2A 16 VIN This pin is the input of the internal linear regulator. It should be tied directly to the input rail. The internal linear device is protected against reverse bias generated by the remaining charge of the decoupling capacitor at PVCC when losing the input rail. When used with an external 3.3V to 5V supply, this pin should be tied directly to PVCC. 25, 17 BOOT1, BOOT2 These pins provide the bootstrap biases for the high-side drivers. Internal bootstrap diodes connected to the PVCC pin provide the necessary bootstrap charge. Its typical operational voltage range is 2.5V to 5.6V. 24, 18 UGATE1, UGATE2 These pins provide the gate signals to drive the high-side devices and should be connected to the MOSFETs’ gates. 23, 19 PHASE1, PHASE2 Connect these pins to the source of the high-side MOSFETs and the drain of the low-side MOSFETs. These pins represent the return path for the high-side gate drives. 22, 20 LGATE1, LGATE2 These pins provide the drive for the low-side devices and should be connected to the MOSFETs’ gates. 21 PVCC This pin is the output of the internal series linear regulator. It provides the bias for both low-side and high-side drives. Its operational voltage range is 3V to 5.6V. The decoupling ceramic capacitor in the PVCC pin is 10µF. 26 VCC This pin provides bias power for the analog circuitry. An RC filter is recommended between the connection of this pin to a 3V to 5.6V bias (typically PVCC). R is suggested to be a 5Ω resistor. And in 3.3V applications, the R could be shorted to allow the low end input in concerns of the VCC falling threshold. The VCC decoupling capacitor is strongly recommended to be as large as a 10µF ceramic capacitor. This pin can be powered either by the internal linear regulator or by an external voltage source. 33 GND The bottom pad is the signal and power ground plane. All voltage levels are referenced to this pad. This pad provides a return path for the low-side MOSFET drives and internal power circuitries as well as all analog signals. Connect this pad to the circuit ground with the shortest possible path (more than 5 to 6 vias to the internal ground plane, placed on the soldering pad are recommended). DESCRIPTION These pins are the non-inverting (+) inputs of the current sensing amplifiers to provide rDS(ON), DCR, or precision resistor current sensing together with the ISEN1B, ISEN2B pins. Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG.# ISL8120CRZ ISL8120 CRZ 0 to +70 32 Ld QFN L32.5x5B ISL8120IRZ ISL8120 IRZ -40 to +85 32 Ld QFN L32.5x5B 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8120. For more information on MSL please see techbrief TB363. Submit Document Feedback 4 FN6641.2 February 9, 2015 ISL8120 Table of Contents Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-Phase Operation with DCR Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2-Phase Operation with rDS(ON) Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Dual Regulators with DCR Sensing and Remote Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Double Data Rate I or II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3-Phase Regulator with Precision Resistor Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Phase Operation with DCR Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Multiple Power Modules in Parallel with Current Sharing Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3-Phase Regulator with Resistor Sensing and 1 Phase Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 Phase Operation with DCR Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Feed-forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage and Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRE-POR Overvoltage Protection (PRE-POR-OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Over-Temperature Protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductor Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resistive Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Sharing Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Series Linear and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency Synchronization and Phase Lock Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Amplifier for Remote Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reference and System Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR and Dual Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 24 24 25 25 26 26 26 27 27 28 29 32 33 33 33 34 35 36 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Submit Document Feedback 5 FN6641.2 February 9, 2015 ISL8120 Controller Block Diagram PGOOD VCC VIN 8 26 16 PGOOD CIRCUIT VCC 400mV EN1 EN2 VMON1 VMON2 CH1_FAULT CH2_FAULT INTERNAL LINEAR REGULATOR POWER-ON RESET 21 PVCC SAW1 25 BOOT1 ICSH_CORR INT. VREF VSEN1- 30 MOSFET DRIVER E/A SS1 VSEN1+ 29 CURRENT BALANCE CIRCUIT FB1 32 PWM1 1 CHANNEL CURRENT SAMPLING COMP1 1 OV/UV COMP1 INT. VREF CHANNEL 1 CH1 OCP SOFT-START AND FAULT LOGIC EN1 EN/VFF1 4 22 LGATE1 Ch1 Fault IAVG_CS ICS1 ICSH_ERR EN_TH 23 PHASE1 PWM1 VMON1 31 24 UGATE1 27 ISEN1A 28 ISEN1B ICS1 7-CYCLE DELAY 108µA AVG_OCP IEN_HYS 1.2V EN/VFF1 EN/VFF2 SAW1 MASTER CLOCK OSCILLATOR GENERATOR FSYNC 5 CLKOUT/ REFIN VCC 400mV CURRENT SHARE BLOCK ICSH_ERR 3 ISHARE 2 ISET M/D CONTROL INT. VREF 7 ICSH_CORR RELATIVE PHASE CONTROL M/D CONTROL ICS1 AVERAGE ICS2 CURRENT IAVG_CS+15µA M/D = 1 (Multiphase operation) : IAVG_CS = (ICS1+ICS2) / 2 M/D = 0 (Dual-output Operation) : IAVG_CS = ICS1 PVCC VSEN2- 12 SAW2 VSEN2+ FB2 VSEN2+ 13 17 BOOT2 VMON2 11 E/A SS2 FB2 10 CURRENT BALANCE CIRCUIT COMP2 9 EN_TH INT. VREF EN2 EN/VFF2 6 OV/UV COMP2 MOSFET DRIVER PWM2 CHANNEL 2 SOFT-START AND FAULT LOGIC IEN_HYS AVG_OCP CH2 OCP IAVG_CS 19 PHASE2 Ch2 Fault ICS2 ICSH_ERR 7-CYCLE DELAY 18 UGATE2 20 LGATE2 108µA ICS2 PWM1 2 CHANNEL CURRENT SAMPLING 15 ISEN2A 14 ISEN2B M/D CONTROL EP Submit Document Feedback 6 FN6641.2 February 9, 2015 ISL8120 Typical Application Circuits 2-Phase Operation with DCR Sensing VIN +3V TO +22V CHFIN RCC CF1 VCC CBIN CF2 PVCC BOOT1 CBOOT1 UGATE1 VIN Q1 LOUT1 VOUT<VCC - 1.8V PHASE1 CF3 COUT1 Q2 LGATE1 EN/VFF1, 2 ISEN1A ISEN1B ISL8120 Local sensing (secondary sensing point) RISEN1 10 COMP1/2 Z COMP1 10 FB1 RSET ISET VMON1/2 ISHARE ROS1 VSEN1- VSENSE+ RFB1 VSEN1+ CSEN1 VSENSERemote sensing PGOOD VIN BOOT2 RFS UGATE2 FSYNC CBOOT2 Q3 LOUT2 PHASE2 LGATE2 Q4 CLKOUT ISEN2A RISEN2 ISEN2B VCC OR GND VCC OR GND VCC FB2 VSEN2- VSEN2+ GND Submit Document Feedback 7 FN6641.2 February 9, 2015 ISL8120 Typical Application Circuits (Continued) 2-Phase Operation with rDS(ON) Sensing VIN +3V TO +22V CHFIN RCC CF1 VCC CBIN CF2 PVCC BOOT1 CBOOT1 UGATE1 VIN Q1 LOUT1 VOUT PHASE1 CF3 ISEN1B RISEN1 EN/FF1, 2 COUT1 Q2 LGATE1 ISEN1A Local sensing (secondary sensing point) 10 ISL8120 COMP1/2 10 ZCOMP1 FB1 RSET ISET VMON1/2 ISHARE VSENSE+ RFB1 VSEN1+ ROS1 VSEN1- CSEN1 VSENSERemote sensing PGOOD VIN BOOT2 CBOOT2 RFS UGATE2 FSYNC Q3 LOUT2 PHASE2 ISEN2B RISEN2 Q4 LGATE2 ISEN2A CLKOUT/REFIN VCC OR GND VCC FB2 VCC OR GND VSEN2- VSEN2+ GND Submit Document Feedback 8 FN6641.2 February 9, 2015 ISL8120 Typical Application Circuits (Continued) Dual Regulators with DCR Sensing and Remote Sense VIN +3.3 TO +22V RCC CF2 CHFIN CBIN CF1 VCC PVCC BOOT1 CBOOT1 UGATE1 VIN Q1 LOUT1 PHASE1 CF3 VOUT1 COUT1 LGATE1 Q2 2k VIN ISEN1A COMP1 ISL8120 10 RISEN1 ISEN1B EN/FF1 10 ZCOMP1 FB1 ZFB1 VMON1 VCC CLKOUT/REFIN VSENSE1+ RFB1 VSEN1+ ROS1 VSEN1- PGOOD CSEN1 VSENSE1- VIN BOOT2 CBOOT2 RFS UGATE2 FSYNC Q3 LOUT2 PHASE2 VOUT2 Q4 LGATE2 COUT2 2k VIN ISEN2A 10 ISEN2B EN/FF2 COMP2 RISEN2 10 ZCOMP2 FB2 ZFB2 RSET VMON2 ISET GND Submit Document Feedback RFB2 VSEN2+ ISHARE 9 VSEN2- ROS2 CSEN2 VSENSE2+ VSENSE2- FN6641.2 February 9, 2015 ISL8120 Typical Application Circuits (Continued) Double Data Rate I or II VIN +3.3 TO +22V RCC CF2 CHFIN CBIN CF1 VCC PVCC BOOT1 CBOOT1 UGATE1 VIN Q1 CF3 2.5V (DDR I) 1.8V (DDR II) LOUT1 PHASE1 VDDQ RFS COUT1 LGATE1 FSYNC Q2 2k ISEN1A ISL8120 10 RISEN1 ISEN1B 10 COMP1 Z COMP1 FB1 ZFB1 VMON1 VSENSE1+ RFB1 VSEN1+ VDDQ ROS1 VSEN1- CSEN1 VSENSE1- R*(VTT/0.6-1) (Notes 4, 5) CLKOUT/REFIN 1nF R VDDQ Or VIN BOOT2 CBOOT2 UGATE2 (Or tie REFIN pin to VMON1 pin) Q3 1.25V (DDR I) 0.9V (DDR II) LOUT2 PHASE2 VTT LGATE2 COUT2 Q4 ( VDDQ/2) 2k ISEN2A 10 ISEN2B RISEN2 COMP2 Z COMP1 10 FB2 PGOOD ZFB1 VMON2 RSET ISET RFB2 VSEN2+ ISHARE GND VSEN2- ROS2 CSEN2 VSENSE2+ VSENSE2- NOTES: 4. Setting the upper resistor to be a little higher than R*(VDDQ/0.6 - 1) will set the final REFIN voltage (stead state voltage after soft-start) derived from the VDDQ to be a little higher than internal 0.6V reference. In this way, the VTT final voltage will use the internal 0.6V reference after soft-start. The other way is to add more delay at EN/VFF1 pin to have Channel 2 tracking VDDQ (check Table 1 on page 22 for more details). 5. Another way to set REFIN voltage is to connect VMON1 directly to the REFIN pin. Submit Document Feedback 10 FN6641.2 February 9, 2015 ISL8120 Typical Application Circuits (Continued) 3-Phase Regulator with Precision Resistor Sensing VIN +3V TO +22V VCC CF1 CF2 RCC CIN PVCC BOOT1 CBOOT2 VIN CF3 UGATE1 LOUT2 PHASE1 ISL8120 EN/FF1 Q1 LGATE1 PHASE 2 Q2 ISEN1A CLKOUT/REFIN PGOOD RISEN2 ISEN1B COMP1 FB1 BOOT2 VMON1 UGATE2 PHASE2 VSEN1+ LGATE2 VSEN1- ISEN2A VCC GND ISEN2B EN/FF2 FSYNC FB2 VMON2 ISHARE VSEN2+ ISET VSEN2- R R VOUT COUT RCC VCC CF1 VIN FSYNC UGATE1 EN/FF1,2 PGOOD BOOT2 PHASE 1 AND 3 UGATE2 LGATE1 VSENSE ZCOMP1 ZFB1 VMON1/2 LGATE2 VSEN1- ISEN2B GND VCC VSENSE RISEN1 ISEN1B FB1 ISEN2A VCC 10 Q2 RFB1 VSEN1+ RISEN3 10 ISEN1A COMP1/2 PHASE2 Q4 CBOOT1 LOUT1 ISL8120 CBOOT3 Q3 Q1 PHASE1 RFS LOUT3 VIN BOOT1 CF3 VIN CF2 PVCC ROS1 CSEN1 ISHARE FB2 VSEN2+ R VSEN2- CLKOUT/REFIN GND ISET R Submit Document Feedback 11 FN6641.2 February 9, 2015 ISL8120 Typical Application Circuits (Continued) 4 Phase Operation with DCR Sensing VIN +3V TO +22V CIN RCC VCC CF1 BOOT1 CF3 CBOOT2 VIN UGATE1 CLKOUT/REFIN PHASE1 PGOOD EN/FF Bus Q1 LGATE1 LOUT2 VOUT COUT Q2 EN/FF1, 2 ISEN1A VSEN1, 2+ FB2 VCC VSEN1,2- VIN ISL8120 ISEN1B PHASE 2 AND 4 Q3 Q4 10 RISEN2 COMP1/2 BOOT2 CBOOT4 LOUT4 CF2 PVCC 10 FB1 UGATE2 VMON1/2 RFB1 PHASE2 ISET ROS1 R GND LGATE2 ISEN2A COS 2ND DIVIDER TO AVOID SINGLE POINT FAILURE VSENSE1+ VSENSE1- FSYNC ISEN2B ISHARE RISEN4 R RCC VCC CF1 VIN FSYNC UGATE1 BOOT2 CBOOT3 LOUT3 PGOOD Q3 Q1 CBOOT1 LOUT1 PHASE1 RFS VIN VIN BOOT1 CF3 EN/FF Bus CF2 PVCC LGATE1 EN/FF1, 2 ISL8120 ISEN1A PHASE 1 AND 3 ISEN1B UGATE2 COMP1/2 PHASE2 Q2 RISEN1 ZCOMP1 ZFB1 FB1 VMON1/2 Q4 LGATE2 RFB1 VSEN1+ ISEN2A RISEN3 VSEN1- ROS1 CSEN1 ISEN2B VCC VCC VCC ISHARE FB2 VSEN2+ R VSEN2- CLKOUT/REFIN GND ISET R Submit Document Feedback 12 FN6641.2 February 9, 2015 ISL8120 Typical Application Circuits (Continued) Multiple Power Modules in Parallel with Current Sharing Control VIN +3V to +22V CIN VCC CF4 RCC2 BOOT1 CBOOT3 VIN CF6 EN CF5 PVCC UGATE1 PGOOD PHASE1 FSYNC LGATE1 Q5 LOUT3 COUT2 Q6 2k EN/FF1, 2 ISEN1A VIN BOOT2 ISEN1B CBOOT4 LOUT4 VOUT2 RISEN3 UGATE2 Q7 PHASE2 COMP1/2 ISL8120 Q8 LGATE2 ZFB2 FB1 RFB2 VSEN1+ ISEN2A VCC VCC ROS2 VSEN1- ISEN2B VCC 10 ZCOMP2 VMON1/2 2k RISEN4 10 2-PHASE MODULE #1 VSEN2+ FB2 CSEN2 VSENSE2+ VSENSE2- RCSR2 VLOAD CLKOUT/REFIN ISHARE VSEN2- GND ISET R R VCC CF1 RCC1 CF2 PVCC VIN BOOT1 VIN CF3 UGATE1 Q1 CBOOT1 LOUT1 VOUT1 PHASE1 LGATE1 EN/FF1, 2 EN PGOOD VIN 2k ISEN1A BOOT2 UGATE2 Q3 COMP1/2 PHASE2 10 ZCOMP1 ZFB1 FB1 ISL8120 Q4 RISEN1 ISEN1B CBOOT2 LOUT2 COUT1 Q2 VMON1/2 LGATE2 ISEN2A RISEN2 ISHARE VCC VCC VSEN2+ FB2 ROS1 VSEN1- ISEN2B VCC RFB1 VSEN1+ 2k 10 CSEN1 VSENSE1+ VSENSE1- RCSR1 2-PHASE R MODULE #2 FSYNC VSEN2GND ISET R Submit Document Feedback 13 FN6641.2 February 9, 2015 ISL8120 Typical Application Circuits (Continued) 3-Phase Regulator with Resistor Sensing and 1 Phase Regulator VIN +3V TO +22V VCC CF1 CIN CF2 RCC PVCC BOOT1 CBOOT2 VIN CF3 UGATE1 Q1 LOUT2 VOUT1 PHASE1 EN/FF1 EN VOUT1 LGATE1 Q2 COUT1 EN/FF2 EN VOUT2 VIN PGOOD ISEN1A BOOT2 ISEN1B COMP1 CBOOT4 FB1 UGATE2 Q3 LOUT4 VOUT2 PHASE2 COUT2 VSEN1+ VSEN1- ISEN2A VSENSE1+ VCC ISET 10 ISEN2B 10 ZFB2 RISEN4 FSYNC FB2 ISHARE VMON2 VSEN2+ VSEN2- VSENSE1R ZCOMP2 VSENSE2+ 10 10 VMON1 ISL8120 LGATE2 Q4 RISEN2 GND R PHASE 2 VSENSE2- VCC CF1 RCC VIN BOOT1 VIN FSYNC CF3 UGATE1 CBOOT1 LOUT1 Q1 PHASE1 RFS LGATE1 EN/FF1, 2 EN VOUT1 CF2 PVCC Q2 PGOOD VIN BOOT2 ISL8120 Q3 UGATE2 COMP1/2 PHASE2 Q4 RISEN1 ISEN1B CBOOT3 LOUT3 ISEN1A ZCOMP1 FB1 ZFB1 VMON1/2 LGATE2 RFB1 VSEN1+ ISEN2A VSEN1- ROS1 CSEN1 ISEN2B VCC RISEN3 GND VCC FB2 VSEN2+ ISHARE PHASE 1 AND 3 VSEN2- 14 R ISET VSEN2+ Submit Document Feedback CLKOUT/REFIN GND R FN6641.2 February 9, 2015 ISL8120 Typical Application Circuits (Continued) 6 Phase Operation with DCR Sensing +3V TO +22V VIN RCC VCC CF1 VIN CLKOUT/REFIN CF3 EN/FF1, 2 CIN PVCC BOOT1 CF2 UGATE1 PHASE1 LGATE1 Q1 Q2 PGOOD GND VCC VIN FB2 VSEN2+ VSEN2BOOT2 CBOOT6 LOUT6 Q3 Q4 ISL8120 PHASE 3 AND 6 UGATE2 PHASE2 LGATE2 ISEN2B RISEN3 VCC R RCC VCC CF1 VIN CF3 VIN Q4 UGATE2 PHASE2 ISL8120 LGATE2 ISEN2B GND VCC OR GND VCC FB2 VSEN2+ VSEN2- CF3 PHASE 2 AND 5 GND VCC CF1 FSYNC RCC VIN UGATE2 PHASE2 LGATE2 15 FB2 VSEN2+ VSEN2- ISHARE ISET R PVCC BOOT1 Q1 VOUT1 COUT1 RISEN1 10 ZFB1 10 ZCOMP1 VMON2 VSEN1ISHARE GND CBOOT1 LOUT1 Q2 ROS1 PHASE 1 AND 4 VIN CF2 VSEN1+ ISEN2A ISEN2B GND VCC OR GND VCC RISEN2 COMP1/2 FB1 VMON1/2 VSEN1+ VSEN1- ISEN1A ISEN1B VMON1 FB1 COMP1/2 ISL8120 RISEN4 Q2 UGATE1 PHASE1 LGATE1 BOOT2 Q4 CBOOT2 LOUT2 R EN/FF1, 2 PGOOD Q3 Q1 VCC CLKOUT/REFIN FSYNC ISEN2A RISEN5 VIN CF2 ISEN1A ISEN1B BOOT2 Q3 PVCC BOOT1 UGATE1 PHASE1 LGATE1 EN/FF1,2 PGOOD Submit Document Feedback COMP1/2 FB1 VMON1/2 VSEN1+ VSEN1ISET FSYNC ISHARE GND RISEN6 VIN CBOOT4 LOUT4 ISEN1A ISEN1B R ISEN2A CBOOT5 LOUT5 CBOOT3 LOUT3 CLKOUT/REFIN ISET RFB1 ROS1 RFB1 CSEN1 VSENSE1+ VSENSE1- R R FN6641.2 February 9, 2015 ISL8120 Absolute Maximum Ratings Thermal Information Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +27V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V BOOT/UGATE Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V Phase Voltage, VPHASE . . . . . . . . . . . . . . . . . . . VBOOT - 7V to VBOOT + 0.3V BOOT to PHASE Voltage, VBOOT - VPHASE . . . . . . . . . . . -0.3V to VCC +0.3V Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V Thermal Resistance (Typical Notes 6, 7) JA(°C/W) JC(°C/W) 32 Ld QFN Package . . . . . . . . . . . . . . . . . . 32 3.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 22V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.6V Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 5.6V Boot to Phase Voltage (Overcharged), VBOOT - VPHASE . . . . . . . . . . . . . <6V Commercial Ambient Temperature Range . . . . . . . . . . . . . . 0°C to +70°C Industrial Ambient Temperature Range . . . . . . . . . . . . . . . -40°C to +85°C Maximum Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 7. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating temperature range, -40°C to +85°C (Industrial) or 0°C to +70°C (Commercial). PARAMETER SYMBOL TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS VCC SUPPLY CURRENT Nominal Supply VIN Current IQ_VIN VIN = 20V; VCC = PVCC; FSW = 500kHz; UGATE, LGATE = open 11 15 20 mA Nominal Supply VIN Current IQ_VIN VIN = 3.3V; VCC = PVCC; FSW = 500kHz; UGATE, LGATE = open 8 12 14 mA Shutdown Supply PVCC Current IPVCC EN = 0V, PVCC = 5V 0.5 1 1.4 mA Shutdown Supply VCC Current IVCC EN = 0V, VCC = 3V 7 10 12 mA IPVCC PVCC = 4V to 5.6V 250 mA PVCC = 3V to 4V 150 mA 1 INTERNAL LINEAR REGULATOR Maximum Current (Note 8) Saturated Equivalent Impedance (Note 8) RLDO P-Channel MOSFET (VIN = 5V) PVCC Voltage Level PVCC IPVCC = 0mA; 0°C < TA < +85°C; VIN = 12V 5.15 5.4 5.65 V IPVCC = 0mA; -40°C < TA < +85°C; VIN = 12V 5.15 5.4 5.95 V Equivalent LDO Output Resistance RLDO_OUT VIN = 12V 0.3 POWER-ON RESET Rising VCC Threshold 2.85 2.97 V Falling VCC Threshold 2.65 2.75 V 0°C < TA < +75°C 2.85 2.97 V -40°C < TA < +85°C 2.85 3.05 2.65 2.75 Rising PVCC Threshold Falling PVCC Threshold Submit Document Feedback 16 V FN6641.2 February 9, 2015 ISL8120 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating temperature range, -40°C to +85°C (Industrial) or 0°C to +70°C (Commercial). (Continued) PARAMETER SYMBOL System Soft-start Delay (Note 8) tSS_DLY TEST CONDITIONS MIN (Note 9) After PLL, VCC, and PVCC PORs, and EN(s) above their thresholds TYP MAX (Note 9) 384 UNITS Cycles ENABLE Turn-On Threshold Voltage Hysteresis Sink Current IEN_HYS 0.75 0.8 0.86 V 0°C < TA < +85°C 25 30 35 µA -40°C < TA < +85°C 23 30 35 µA Undervoltage Lockout Hysteresis (Note 8) VEN_HYS VEN_RTH = 10.6V; VEN_FTH = 9V RUP = 53.6k, RDOWN = 5.23k Sink Current IEN_SINK VENFF = 1V Sink Impedance REN_SINK VENFF = 1V 1.6 V 15.4 mA 64 1500 kHz 406 kHz OSCILLATOR Oscillator Frequency Range 150 Oscillator Frequency RFS = 100k, Figure 30 Total Variation VCC = 5V; -40°C < TA < +85°C Peak-to-Peak Ramp Amplitude VRAMP VCC = 5V, VEN = 0.8V Linear Gain of Ramp Over VEN GRAMP GRAMP = VRAMP/VEN Ramp Peak Voltage VRAMP_PEAK VRAMP VEN = VCC = 5.4V, RUP = 2k Peak-to-Peak Ramp Amplitude VRAMP VEN = VCC = 3V; RUP = 2k Ramp Amplitude Upon Disable VRAMP VEN = 0V; VCC = 3.5V to 5.5V Ramp Amplitude Upon Disable VRAMP VEN = 0V; VCC < 3.4V 377 -9 +9 1 % VP-P 1.25 VEN = VCC Peak-to-Peak Ramp Amplitude Ramp DC Offset 344 VRAMP_OS VCC - 1.4 V 3 VP-P 0.6 VP-P 1 VP-P VCC - 2.4 VP-P 1 V FREQUENCY SYNCHRONIZATION AND PHASE LOCK LOOP Synchronization Frequency VCC = 5V PLL Locking Time VCC = 5.4V; FSW = 400kHz 150 105 VCC = 2.97V; FSW = 400kHz Input Signal Duty Cycle Range (Note 8) 1500 kHz µs 150 10 90 % 410 ns PWM Minimum PWM OFF Time tMIN_OFF Current Sampling Blanking Time (Note 8) 310 tBLANKING 345 175 ns REFERENCE Channel 1 Reference Voltage (Include Error and Differential Amplifiers’ Offsets) VREF1 -0°C < TA < +70°C 0.6 -0.6 -40°C < TA < +85°C 0.6 -0.7 Channel 2 Reference Voltage (Include Error and Differential Amplifiers’ Offsets) VREF2 -0°C < TA < +70°C % V 0.75 0.6 -0.75 17 0.7 -0.75 % V 0.6 -40°C < TA < +85°C Submit Document Feedback V 0.6 % V 0.95 % FN6641.2 February 9, 2015 ISL8120 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating temperature range, -40°C to +85°C (Industrial) or 0°C to +70°C (Commercial). (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS ERROR AMPLIFIER DC Gain (Note 8) Unity Gain-Bandwidth (Note 8) UGBW_EA RL = 10k, CL = 100pF, at COMP Pin 98 dB RL = 10k, CL = 100pF, at COMP Pin 80 MHz Input Common Mode Range (Note 8) -0.2 Output Voltage Swing VCC = 5V Slew Rate (Note 8) SR_EA Input Current (Note 8) IFB VCC - 1.8 0.85 VCC - 1.0 V V RL = 10k, CL = 100pF, at COMP Pin 20 V/µs Positive Direction Into the FB pin 100 nA Output Sink Current ICOMP 3 mA Output Source Current ICOMP 6 mA Disable Threshold (Note 8) VVSEN- VCC - 0.4 V 0 dB 5 MHz DIFFERENTIAL AMPLIFIER DC Gain (Note 8) UG_DA Unity Gain Bandwidth (Note 8) Unity Gain Amplifier UGBW_DA VSEN+ pin Sourcing Current IVSEN+ Maximum Source Current for Current Sharing (See “Typical Application Circuits on page 11) (Note 8) IVSEN1- Input Impedance RVSEN+_to _VSEN- 0.2 1 2.5 µA VSEN1- Source Current for Current Sharing when parallel multiple modules each of which has its own voltage loop 350 µA VVSEN+ /IVSEN+ , VVSEN+ = 0.6V -600 k Output Voltage Swing (Note 8) Input Common Mode Range (Note 8) VVSEN- VMON1, VMON2 = Tri-State Upper Drive Source Resistance RUGATE Upper Drive Sink Resistance 0 VCC - 1.8 V -0.2 VCC - 1.8 V VCC - 0.4 V 45mA Source Current 1.0 RUGATE 45mA Sink Current 1.0 Lower Drive Source Resistance RLGATE 45mA Source Current 1.0 Lower Drive Sink Resistance RLGATE 45mA Sink Current 0.4 Channel Overcurrent Limit (Note 8) ISOURCE VCC = 2.97V to 5.6V 108 µA Channel Overcurrent Limit ISOURCE VCC = 5V; 0°C < TA < +70°C 94 108 122 µA VCC = 5V; -40°C < TA < +85°C 89 108 122 µA Disable Threshold (Note 8) GATE DRIVERS OVERCURRENT PROTECTION Share Pin OC Threshold VOC_ISHARE VCC = 2.97V to 5.6V (comparator offset included) VCC = 5V (comparator offset included) 1.20 1.16 1.20 V 1.22 V CURRENT SHARE Internal Balance Accuracy (Note 8) VCC = 2.97V and 5.6V, 1% Resistor Sense, 10mV Signal ±5 % Internal Balance Accuracy (Note 8) VCC = 4.5V and 5.6V, 1% Resistor Sense, 10mV Signal ±5 % Submit Document Feedback 18 FN6641.2 February 9, 2015 ISL8120 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating temperature range, -40°C to +85°C (Industrial) or 0°C to +70°C (Commercial). (Continued) PARAMETER SYMBOL MIN (Note 9) TEST CONDITIONS External Current Share Accuracy (Note 8) VCC = 2.97V and 5.6V, 1% Resistor Sense, 10mV Signal MAX (Note 9) TYP ±20 UNITS % POWER-GOOD MONITOR Undervoltage Falling Trip Point VUVF Undervoltage Rising Hysteresis VUVR_HYS Overvoltage Rising Trip Point VOVR Overvoltage Falling Hysteresis VOVF_HYS Percentage Below Reference Point -15 -13 Percentage Above UV Trip Point -11 4 Percentage Above Reference Point 11 % 13 Percentage below OV Trip Point % 15 4 % % PGOOD Low Output Voltage IPGOOD = 2mA 0.35 V Sinking Impedance IPGOOD = 2mA 70 Maximum Sinking Current (Note 8) VPGOOD < 0.8V 10 mA OVERVOLTAGE PROTECTION OV Latching Trip Point EN/FF = UGATE = LATCH Low, LGATE = High OV Non-Latching Trip Point (Note 8) EN/FF = Low, UGATE = Low, LGATE = High LGATE Release Trip Point EN/FF = Low/HIGH, UGATE = Low, LGATE = Low 118 120 122 % 113 % 87 % Over-Temperature Trip (Note 8) 150 °C Over-Temperature Release Threshold (Note 8) 125 °C OVER-TEMPERATURE PROTECTION NOTES: 8. Limits should be considered typical and are not production tested. 9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 0.606 0.606 0.604 0.604 0.602 0.602 VFB2 (V) VFB1 (V) Typical Performance Curves 0.600 0.600 0.598 0.598 0.596 0.596 0.594 -50 -25 0 25 50 75 100 TEMPERATURE (°C) FIGURE 2. CHANNEL 1 ACCURACY vs TEMPERATURE Submit Document Feedback 19 125 0.594 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 3. CHANNEL 2 ACCURACY vs TEMPERATURE FN6641.2 February 9, 2015 ISL8120 Typical Performance Curves (Continued) 410 5.7 VIN = 12V; 100mA LOAD 5.6 400 Fsw ( kHz ) PVCC ( V ) 5.5 5.4 5.3 390 380 5.2 370 5.1 5.0 -50 -25 0 25 50 75 100 125 360 -50 150 -25 0 25 TEMPERATURE (°C) 0.810 0.810 0.808 0.808 0.806 0.806 0.804 0.804 0.802 0.800 0.798 0.796 0.796 0.792 50 75 100 125 0.790 -50 150 -25 0 TEMPERATURE (°C) 33 33 32 32 31 30 29 28 25 50 75 100 TEMPERATURE (°C) 125 150 FIGURE 7. VENFF2 ENABLE THRESHOLD vs TEMPERATURE IENFF2_HYST (µA) IENFF1_HYST (µA) FIGURE 6. VENFF1 ENABLE THRESHOLD vs TEMPERATURE 27 -50 150 0.798 0.794 25 125 0.800 0.792 0 100 0.802 0.794 -25 75 FIGURE 5. SWITCHING FREQUENCY vs TEMPERATURE Vth_ENFF1 (V) Vth_ENFF1 (V) FIGURE 4. PVCC vs TEMPERATURE 0.790 -50 50 TEMPERATURE (°C) 31 30 29 28 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) FIGURE 8. ENFF1 HYSTERESIS CURRENT vs TEMPERATURE Submit Document Feedback 20 27 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (°C) FIGURE 9. ENFF2 HYSTERESIS CURRENT vs TEMPERATURE FN6641.2 February 9, 2015 ISL8120 Modes of Operation There are 9 typical operation modes depending upon the signal levels on EN1/FF1, EN2/FF2, VSEN2+, VSEN2-, FB2, and CLKOUT/REFIN. MODE 1: The IC is completely disabled when EN1/FF1 and EN2/FF2 are pulled below 0.8V. MODE 2: With EN1/FF1 pulled low and EN2/FF2 pulled high (Mode 2A), or EN1/FF1 pulled high and EN2/FF2 pulled low (Mode 2B), the ISL8120 operates as a single phase regulator. The current sourcing out from the ISHARE pin represents the first channel current plus 15µA offset current. MODE 3: When VSEN2- is used as a negative sense line, both channels’ phase shift depends upon the voltage level of CLKOUT/REFIN. When the CLKOUT/REFIN pin is within 29% to 45% of VCC, Channel 2 delays 0° over Channel 1 (Mode 3A); when within 45% to 62% of VCC, 90° delay (Mode 3B); when greater than 62% to VCC, 180° delay (Mode 3C). Refer to the “Internal Reference and System Accuracy” on page 34. MODE 4: When VSEN2- is used as a negative remote sense line, and CLKOUT/REFIN is connected to an external voltage ramp lower than the internal soft-start ramp and lower than 0.6V, the external ramp signal will replace Channel 2’s internal soft-start ramp to be tracked at start-up, controller operating in DDR mode. The controller will use the lowest voltage among the internal 0.6V reference, the external voltage in CLKOUT/REFIN pin and the soft-start ramp signal. Channel 1 is delayed 60° behind Channel 2. Refer to the “Internal Reference and System Accuracy” on page 34. MODE 6: With VSEN2- pulled within 400mV of VCC, FB2 pulled high and VSEN2+ pulled low, the internal channels (as 1st and 3rd Phase, respectively) are 240° out-of-phase and operate in 3phase single output mode, combined with another ISL8120 at MODE 2B. The CLKOUT/REFIN pin signals out 120° relative phases to the falling edge of Channel 1’s clock signal to synchronize with the second ISL8120’s Channel 1 (as 2nd Phase). MODE 7: With VSEN2- pulled within 400mV of VCC and FB2 and VSEN2+ pulled high, the internal channel is 180° out-of-phase. The CLKOUT/REFIN pin (rising edge) signals out 90° relative phase to the Channel 1’s clock signal (falling edge of PWM) to synchronize with another ISL8120, which can operate at Mode 3, 4, 5A, or 7A. A 4-phase single output converter can be constructed with two ISL8120s operating in Mode 5A or 7A (Mode 7A). If the share bus is not connected between ICs, each IC could generate an independent output (Mode 7B). When the second ISL8120 operates as two independent regulators (Mode 3) or in DDR mode (Mode 4), then a three independent output system is generated (Mode 7C). Both ICs can also be constructed as a 3-phase converter (0°, 90°, and 180°, not a equal phase shift for 3-phase) with a single phase regulator (270°). MODE 8: The output CLKOUT signal allows expansion for 12phase operation with the cascaded sequencing, as shown in Table 1. No external clock is required in this mode for the desired phase shift. MODE 9: With an external clock, the part can be expanded for 5, 7, 8, 9 10 and 11 phase single output operation with the desired phase shift. MODE 5: With VSEN2- pulled within 400mV of VCC and FB2 pulled to ground, the internal channels are 180° out-of-phase and operate in 2-phase single output mode (5A). The CLKOUT/REFIN pin (rising edge) also signals out clock with 60° phase shift relative to the Channel 1’s clock signal (falling edge of PWM) for 6-phase operation with two other ISL8120s (5B). When the share pins are not connected to each other for the three ICs in sync, two of which can operate in Mode 5A (3 independent outputs can be generated (Mode 5D) and Modes 3 and 4 (to generate 4 independent outputs (Mode 5C) respectively. Submit Document Feedback 21 FN6641.2 February 9, 2015 Submit Document Feedback TABLE 1. 1ST IC (I = INPUT; O = OUTPUT; I/O = INPUT AND OUTPUT, BI-DIRECTION) 22 VSEN2+ (I) CLKOUT/REFIN WRT 1ST (I or O) ISHARE (I/O) REPRESENTS WHICH CHANNEL(S) CURRENT 2ND CHANNEL WRT 1ST (O) (NOTE 10) OPERATION MODE of 2ND IC OPERATION MODE of 3RD IC OUTPUT (See Description for Details) - - - - - - - DISABLED ACTIVE ACTIVE - N/A - - - SINGLE PHASE - 1ST CHANNEL - - - SINGLE PHASE 0° - - DUAL REGULATOR MODE EN1/ FF1 (I) EN2/ FF2 (I) VSEN2(I) FB2 (I) 1 <0.8V <0.8V - 2A <0.8V >0.8V ACTIVE 2B >0.8V <0.8V - MODES OF OPERATION - - 3A >0.8V >0.8V <VCC -0.4V ACTIVE ACTIVE 29% to 45% of VCC (I) 1ST CHANNEL 3B >0.8V >0.8V <VCC -0.4V ACTIVE ACTIVE 45% to 62% of VCC (I) 1ST CHANNEL 90° - - DUAL REGULATOR 3C >0.8V >0.8V <VCC -0.4V ACTIVE ACTIVE > 62% of VCC (I) 1ST CHANNEL 180° - - DUAL REGULATOR 4 >0.8V >0.8V <VCC-0.4V ACTIVE ACTIVE < 29% of VCC (I) 1ST CHANNEL -60° - - DDR MODE NOTE 11 NOTE 11 VCC GND VCC/GND 60° Average of Channel 1 & 2 180° - - 2-PHASE 5B NOTE 11 NOTE 11 VCC GND VCC/GND 60° Average of Channel 1 & 2 180° 5A 5A or 7A 6-PHASE 5C NOTE 11 NOTE 11 VCC GND VCC/GND 60° Average of Channel 1 & 2 180° 5A 5A or 7A 3 OUTPUTs 5D NOTE 11 NOTE 11 VCC GND VCC/GND 60° Average of Channel 1 & 2 180° 5A 3 or 4 4 OUTPUTs 6 NOTE 11 NOTE 11 VCC VCC GND 120° Average of Channel 1 & 2 240° 2B - 3-PHASE 7A NOTE 11 NOTE 11 VCC VCC VCC 90° Average of Channel 1 & 2 180° 5A or 7A - 4-PHASE 7B NOTE 11 NOTE 11 VCC VCC VCC 90° Average of Channel 1 & 2 180° 5A or 7A - 2 OUTPUTs (1st IC in Mode 7A) 7C NOTE 11 NOTE 11 VCC VCC VCC 90° Average of Channel 1 & 2 180° 3, 4 - 3 OUTPUTs (1st IC in Mode 7A) 8 Cascaded IC Operation MODEs 5A+5A+7A+5A+5A+5A/7A, No External Clock Required 12-PHASE 9 External Clock or External Logic Circuits Required for Equal Phase Interval 5, 7, 8, 9, 10, 11, or (PHASE >12) NOTES: FN6641.2 February 9, 2015 10. “2ND CHANNEL WRT 1ST” is referred to as “channel 2 lag channel 1 by the degrees specified by the number in the corresponding table cells”. For example, 90° with 2ND CHANNEL WRT 1ST means channel 2 lags channel 1 by 90°; -60° with 2ND CHANNEL WRT 1ST means channel 2 leads channel 1 by 60°. 11. All EN/FF pins are tied together. ISL8120 5A ISL8120 Functional Description CH1 UG (1ST IC) D 1-D 180° CH2 UG (1ST IC) D 90° 50% CLKOUT (1ST IC) 90° D CH1 UG (2ND IC) 180° CH2 UG (2ND IC) D 4 phase timing diagram (MODE 7A) CH1 UG (1ST IC) D 1-D 240° D CH2 UG (1ST IC) 120° CLKOUT (1ST IC) 50% 120° CH1 UG (2ND IC) 1-D D CH2 UG(2ND IC, OFF, EN2/FF2 = 0) 3-PHASE TIMING DIAGRAM (MODE 6) VCC VSEN2- VSEN2+ FB2 VMON2 CLKOUT/REFIN COMP2 400mV DIFF AMP2 UV/OV COMP2 ERROR AMP2 VREF2 = VREF CLOCK GENERATOR AND RELATIVE PHASES CONTROL CHANNEL 1 PWM CONTROL BLOCK CHANNEL 2 PWM CONTROL BLOCK FIGURE 10. SIMPLIFIED RELATIVE PHASES CONTROL Submit Document Feedback 23 FN6641.2 February 9, 2015 ISL8120 Initialization VIN Initially, the ISL8120 Power-On Reset (POR) circuits continually monitor the bias voltages (PVCC and VCC) and the voltage at the EN pin. The POR function initiates soft-start operation 384 clock cycles after the EN pin voltage is pulled to be above 0.8V, all input supplies exceed their POR thresholds and the PLL locking time expires, as shown in Figure 11. During shutdown or fault conditions, the soft-start is reset quickly while UGATE and LGATE change states immediately (<100ns) upon the input drop below falling POR. ISL8120 R VCC POR 384 Cycles AND EN1/FF1 POR SOFT-START OF CHANNEL 1 384 Cycles AND PVCC POR SOFT-START OF CHANNEL 2 The enable pin can be used as a voltage monitor and to set desired hysteresis with an internal 30µA sinking current going through an external resistor divider. The sinking current is disengaged after the system is enabled. This feature is especially designed for applications that require higher input rail POR for better undervoltage protection. For example, in 12V applications, RUP = 53.6k and RDOWN = 5.23k will set the turn-on threshold (VEN_RTH) to 10.6V and turn-off threshold (VEN_FTH) to 9V, with 1.6V hysteresis (VEN_HYS). The multiphase system can immediately turn off all ICs under fault conditions of one or more phases by pulling all EN/FF pins low. Thus, no bouncing occurs among channels at fault and no single phase could carry all current and be over stressed. R V UP EN_REF R DOWN = --------------------------------------------------------------V EN_FTH – V EN_REF EN_FTH EN_RTH –V RDOWN V EN_HYS = ---------------------------------------------------------UP I N EN_HYS PHASE VCC GRAMP = 1.25 where N is number of EN/FF pins connected together = V EN/FF2 Other than used as a voltage monitor described in the previous section, the voltages applied to the EN/FF pins are also fed to adjust the amplitude of each channel’s individual sawtooth. The amplitude of each channel’s sawtooth is set to 1.25 times the corresponding EN/FF voltage upon its enable (above 0.8V). This helps to maintain a constant gain ( G M = VIN D MAX V RAMP ) contributed by the modulator and the input voltage to achieve optimum loop response over a wide input voltage range. The amplitude of each channel’s sawtooth is set to 1.25 times the corresponding EN/VFF voltage upon its enable (above 0.8V). The sawtooth ramp offset voltage is 1V, and the peak of the sawtooth is limited to VCC - 1.4V. This allows a maximum peak-to-peak amplitude of sawtooth ramp to be VCC - 2.4V. A constant voltage (0.8V) is fed into the ramp generator to maintain a minimum peak-to-peak ramp. FIGURE 11. SOFT-START INITIALIZATION LOGIC V EN/FF1 EN/FF2 Voltage Feed-forward EN2/FF2 POR V EN_HYS R UP = -----------------------------------Nx I EN_HYS EN/FF1 FIGURE 12. TYPICAL 4-PHASE WITH FAULT HANDSHAKE PLL LOCKING VCC POR ISL8120 2-PHASE There is an internal transistor, which will pull-down the EN/FF pin under fault conditions. The multiphase system can immediately turn off all ICs under fault conditions of one or more phases by pulling all EN/FF pins low. Thus, no bouncing occurs among channels at fault and no single phase could carry all current and be over stressed. The pull-up resistor (RUP) should be scaled to sink no more than 5mA current to the EN/VFF pin. Essentially, the EN/FF pins cannot be directly connected to VCC. HIGH = ABOVE POR; LOW = BELOW POR PVCC POR RUP 2-PHASE VCC - 1.4V UPPER LIMIT å EN_HYS V RAMP = LIMIT(V CC_FF G RAMP , VCC - 1.4V - V RAMP_OFFSET 0.8V VCC_FF LIMITER SAWTOOTH AMPLITUDE (DVRAMP) VIN VRAMP_OFFSET = 1.0V LOWER LIMIT (RAMP OFFSET) 0.8V RUP SYSTEM DELAY RDOWN EN/FF 384 Clock Cycles SOFT-START IEN_HYS = 30µA OV, OT, OC, AND PLL LOCKING FAULTS (ONLY FOR EN/FF1) FIGURE 13. SIMPLIFIED ENABLE AND VOLTAGE FEEDFORWARD CIRCUIT Submit Document Feedback 24 FN6641.2 February 9, 2015 ISL8120 With VCC = 5.4V, the ramp has an allowable maximum peak-to-peak voltage of 3V and minimum of 1V. Therefore, the feed-forward voltage effective range is typically 3x. A 384 cycle delay is added after the system reaches its rising POR and prior to the soft-start. The RC timing at the EN/FF pin should be sufficiently small to ensure that the input bus reaches its static state and the internal ramp circuitry stabilizes before soft-start. A large RC could cause the internal ramp amplitude not to synchronize with the input bus voltage during output startup or when recovering from faults. It is recommended to use open drain or open collector to gate this pin for any system delay, as shown in Figure 13. Soft-start The ISL8120 has two independent digital soft-start circuitry with fixed 1280 switching cycles. The soft-start time is inversely proportional to the switching frequency and is determined by the 1280-cycle digital counter. Refer to Figure 14. The full soft-start time from 0V to 0.6V can be estimated using Equation 1. 1280 t SS = ------------f SW (EQ. 1) The ISL8120 has the ability to work under a pre-charged output (see Figure 15). The output voltage would not be yanked down during pre-charged start-up. If the pre-charged output voltage is greater than the final target level but lowered to 120% setpoint, the switching will not start until the FB voltage reduces to the internal soft-start signal or the end of the soft-start is declared (see Figure 16).F SS SETTLING AT VREF + 100mV FIRST PWM PULSE OV = 113% FIRST PWM PULSE VOUT TARGET VOLTAGE FIGURE 16. SOFT-START WITH VOUT BELOW OV BUT ABOVE FINAL TARGET VOLTAGE Power-Good Both channels share the same PGOOD output. Either of the channels indicating out-of-regulation will pull-down the PGOOD pin. The Power-Good comparators monitor the voltage on the VMON pins. The trip points are shown in Figure 17. PGOOD will not be asserted until after the completion of the soft-start cycle of both channels. States of both EN/FF1 and EN/FF2 have impact on the PGOOD signal. If one of the VMON pins’ voltage is out of the threshold window, PGOOD will not pull low until the fault presents for three consecutive clock cycles. ENFF1 0.8V + - EN1 VMON1 + VREF - ENFF2 0.8V + - EN2 PGOOD1 CH1 SOFT-START DONE VMON2 + VREF - PGOOD2 CH2 SOFT-START DONE VMON EN1 PGOOD1 0.0V -100mV t t 1280 = -------------SS F SW PGOOD EN2 PGOOD2 384 ª -------------SS_DLY F SW PGOOD1 PGOOD2 FIGURE 14. SOFT-START WITH VOUT = 0V +20% FIRST PWM PULSE SS SETTLING AT VREF + 100mV VMON1, 2 VMON +13% +9% PRE-CHARGED LEVEL VREF -100mV -9% FIGURE 15. SOFT-START WITH VOUT = UV -13% PGOOD1,2 PGOOD LATCH OFF AFTER 120% OV FIGURE 17. POWER-GOOD THRESHOLD WINDOW Submit Document Feedback 25 FN6641.2 February 9, 2015 ISL8120 Overvoltage and Undervoltage Protection The Overvoltage (OV) and Undervoltage (UV) protection circuitry monitor the voltage on the VMON pins. OV protection is active upon VCC POR. An OV condition (>120%) would latch IC off (the high-side MOSFET to latch off permanently; the low-side MOSFET turns on immediately at the time of OV trip and then turns off after the VMON drops below 87%). The EN/FF and PGOOD are also latched low at OV event. The latch condition can be reset only by recycling VCC. In Dual/DDR mode, each channel is responsible for its own OV event with the corresponding VMON as the monitor. In multiphase mode, both channels respond simultaneously when either triggers an OV event. There is another non-latch OV protection (113% of target level). At the condition of EN/FF low and the output over 113% OV, the lower side MOSFET will turn on until the output drops below 87%. This is to protect the overall power trains in case of only one channel of a multiphase system detecting OV. The low-side MOSFET always turns on at the conditions of EN/FF = LOW and the output voltage above 113% (all VMON pins and EN/FF pins are tied together) and turns off after the output drops below 87%. Thus, in a high phase count application (Multiphase Mode), all cascaded ICs can latch off simultaneously via the EN/FF pins (EN/FF pins are tied together in multiphase mode), and each IC shares the same sink current to reduce the stress and eliminate the bouncing among phases. VMON1 113% 87% OR FORCE LGATE1 HIGH AND EN/FF1 VMON1>120% OR AND MULTIPHASE MODE = HIGH VMON2 113% 87% AND OR EN/FF2 FORCE LGATE2 HIGH FIGURE 18. FORCE LGATE HIGH LOGIC The UV functionality is not enabled until the end of soft-start. In a UV event, if the output drops below -13% of the target level due to some reason (cases when EN/FF is not pulled low) other than OV, OC, OT, and PLL faults, the lower MOSFETs will turn off to avoid any negative voltage ringing. 26 VOUT 3 CYCLES 3 CYCLES UV PGOOD OV LATCH UGATE AND EN/FF LATCH LOW FIGURE 19. PGOOD TIMING UNDER UV AND OV PRE-POR Overvoltage Protection (PRE-POROVP) When both the VCC and PVCC are below PORs (not including EN POR), the UGATE is low and LGATE is floating (high impedance). EN/VFF has no control on LGATE when VCC and PVCC are below their PORs. When VCC and PVCC are above their PORs, the LGATE would not be floating but toggling with its PWM pulses. An internal 10k resistor, connected in between PHASE and LGATE nodes, implements the PRE-POR-OVP circuit. The output of the converter that is equal to phase node voltage via output inductors is then effectively clamped to the low-side MOSFET’s gate threshold voltage, which provides some protection to the load if the upper MOSFET(s) is shorted during start-up, shutdown, or normal operations. For complete protection, the low-side MOSFET should have a gate threshold that is much smaller than the maximum voltage rating of the load. The PRE-POR-OVP works against pre-biased start-up when pre-charged output voltage is higher than the threshold of the low-side MOSFET, however, it can be disabled by placing a resistor from LGATE to ground. The resistor value can be estimated from Equation 2. 10k R -----------------------------------------------------------V pre – biased max -------------------------------------------------- – 1 V th min VMON2 > 120% Submit Document Feedback 120% (EQ. 2) The resistor value should be as large as possible to minimize power dissipation, while providing sufficient margin for the internal 10k and MOSFET’s Vth tolerances. For example, a 2k resistor is recommended for applications using logic-level MOSFET with the maximum pre-biased voltage less than 5V. Over-Temperature Protection (OTP) When the junction temperature of the IC is greater than +150°C (typically), both EN/FF pins pull low to inform other cascaded channels via their EN/FF pins. All connected EN/FFs stay low and release after the IC’s junction temperature drops below +125°C (typically), with a +25°C hysteresis (typical). FN6641.2 February 9, 2015 ISL8120 Inductor Current Sensing The ISL8120 supports inductor DCR sensing, MOSFET’s rDS(ON) sensing, or resistive sensing techniques. The circuits shown in Figures 20, 21, and 22 represent one channel of the controller. This circuitry is identical for both channels. Note that the common mode input voltage range of the current sense amplifiers is VCC - 1.8V. Therefore, the rDS(ON) sensing must be used for applications with output voltage greater than VCC - 1.8V. For example, when VCC = 5.4V, the inductor DCR and the resistive sensing configurations can be used for output voltage less than 3V. For higher output voltage, rDS(ON) sensing configuration must be used. INDUCTOR DCR SENSING VIN I s L UGATE(n) L PHASE(n) VOUT DCR INDUCTOR + + VC(s) R COUT - ISL8120 INTERNAL CIRCUIT VL - LGATE(n) RISEN(n) (PTC) + - ISEN(n)A ISEN(n)B ISEN FIGURE 20. DCR SENSING CONFIGURATION An inductor’s winding is characteristic of a distributed resistance as measured by the DCR (Direct Current Resistance) parameter. Consider the inductor DCR as a separate lumped quantity, as shown in Figure 20. The inductor current, IL; will also pass through the DCR. Equation 3 shows the s-domain equivalent voltage across the inductor VL. (EQ. 3) V L = I L s L + DCR A simple R-C network across the inductor extracts the DCR voltage, as shown in Figure 20. The voltage on the capacitor VC, can be shown to be proportional to the inductor current IL, see Equation 4. L s ------------+ 1 DCR I L DCR V C = -------------------------------------------------------------------- s RC + 1 Submit Document Feedback 27 2 2 D V IN – max – V OUT + 1 – D V OUT R min = ------------------------------------------------------------------------------------------------------------k P R – pkg P (EQ. 5) Where PR-pkg is the maximum power dissipation specification for the resistor package and P is the derating factor for the same parameter (eg.: PR-pkg = 0.063W for 0402 package, P = 80% @ +85°C). k is the margin factor, also to limit temperature raise in the resistor package, recommend using 0.4. Once Rmin has been calculated, solve for the maximum value of C using Equation 6: L C max = -------------------------------R min DCR C I CS n SAMPLE & HOLD If the R-C network components are selected such that the RC time constant (= R*C) matches the inductor time constant (= L/DCR), the voltage across the capacitor VC is equal to the voltage drop across the DCR, i.e. proportional to the inductor current. The value of R should be as small as feasible for best signal-to-noise ratio. Make sure the resistor package size is appropriate for the power dissipated and include this loss in efficiency calculations. In calculating the minimum value of R, the average voltage across C (which is the average ILDCR product) is small and can be neglected. Therefore, the minimum value of R may be approximated using Equation 5. (EQ. 4) (EQ. 6) and choose the next-lowest readily available value. Then substitute the chosen value into the same equation and recalculate the value of R. Choose the 1% resistor standard value closest to this re-calculated value of R. For example, when VIN_MAX = 14.4V, VOUT = 2.5V, L = 1µH and DCR = 1.5m, with 0402 package Equation 5 yields RMIN of 1476 and Equation 6 yields CMAX of 0.45µF. By choosing 0.39µF and recalculating the resistor it yields 1.69k With the internal low-offset current amplifier, the capacitor voltage VC is replicated across the sense resistor RISEN. Therefore, the current out of ISEN(n)B pin, ISEN, is proportional to the inductor current. After 175ns blanking period with respect to the falling edge of the PWM pulse of each channel, the ISEN current is filtered and sampled for 175ns. The sampling current ICS then can be derived as shown by Equation 7: V OUT 1–D I L + ---------------- ---------------- – t MIN_OFF DCR L 2F SW ICS = ---------------------------------------------------------------------------------------------------------------R ISEN (EQ. 7) Where IL is the inductor DC current, FSW is the switching frequency, and tMIN_OFF is 350ns. Resistive Sensing For accurate current sense, a dedicated current-sense resistor RSENSE in series with the output inductor can serve as the current sense element (see Figure 21). This technique is more accurate, but reduces overall converter efficiency due to the additional power loss on the current sense element RSENSE. FN6641.2 February 9, 2015 ISL8120 VIN UGATE(n) I L PHASE(n) Equation 9 shows the sampling current, ICS, when using MOSFET rDS(ON) sensing. L RSENSE VOUT COUT LGATE(n) ISL8120 INTERNAL CIRCUIT I CS n RISEN(n) SAMPLE AND HOLD + - V OUT 1–D I L + ---------------- ---------------- – t MIN_OFF r DS ON L 2F SW I CS = ------------------------------------------------------------------------------------------------------------------------R ISEN (EQ. 9) Both inductor DCR and MOSFET rDS(ON) value will increase as the temperature increases. Therefore the sensed current will increase as the temperature of the current sense element increases. In order to compensate the temperature effect on the sensed current signal, a Positive Temperature Coefficient (PTC) resistor can be selected for the sense resistor RISEN. Overcurrent Protection ISEN(n)A ISEN(n)B ISEN FIGURE 21. SENSE RESISTOR IN SERIES WITH INDUCTOR Equation 8 shows the sampling current, ICS, when using sensing resistor V OUT 1–D IL + ---------------- ---------------- – t MIN_OFF RSENSE L 2F SW ICS = -----------------------------------------------------------------------------------------------------------------------------R ISEN (EQ. 8) For overload and hard short condition, the overcurrent protection reduces the regulator RMS output current much less than full load by putting the controller into hiccup mode. A delay time, equal to 3 soft-start intervals, is inserted to allow the disturbance to be cleared out. After the delay time, the controller then initiates a soft-start interval. If the output voltage comes up and returns to the regulation, PGOOD transitions high. If the OC trip is exceeded during the soft-start interval, the controller pulls EN/VFF low again. The PGOOD signal will remain low and the soft-start interval will be allowed to expire. Another soft-start interval will be initiated after the delay interval. If an overcurrent trip occurs again, this same cycle repeats until the fault is removed. Similar to DCR current sensing approach, the resistive sensing approach can be used with output voltage less than VCC - 1.8V. The OCP function is enabled at start-up. The ISL8120 monitors 2 signals: sampled channel current, ICS, and ISHARE voltage for over current protection. MOSFET rDS(ON) SENSING CHANNEL CURRENT OCP I CS n VIN ISEN IL SAMPLE AND HOLD ISEN(n)B RISEN (PTC) + ISEN(n)A I x r DS ON L + N-CHANNEL MOSFETs ISL8120 INTERNAL CIRCUIT EXTERNAL CIRCUIT FIGURE 22. MOSFET rDS(ON) CURRENT-SENSING CIRCUIT The controller can also sense the channel load current by sampling the voltage across the synchronous MOSFET rDS(ON) (see Figure 22). The amplifier is ground-reference by connecting the ISEN(n)A pin to the source of the synchronous MOSFET. ISEN(n)B pin is connected to the synchronous MOSFET’S drain through the current sense resistor RISEN. The voltage across RISEN is equivalent to the voltage drop across the rDS(ON) of the lower MOSFET while it is conducting. The resulting current out of the ISEN(n)B pin is proportional to the channel current IL. Submit Document Feedback 28 Each sampled channel current, ICS, is compared to 108µA (typ.) for the OCP trip point. The channel over current trip point can be set by using RISEN value such that the over current trip point corresponds to the channel sensing current, ICS, of 108µA. For DCR current sensing, Equation 7, and rDS(ON) current sensing, Equation 9, the RISEN can be estimated from Equations 10 and 11, respectively. V OUT 1–D IOC + ---------------- ---------------- – t MIN_OFF DCR L 2F SW R ISEN = ----------------------------------------------------------------------------------------------------------------------108A (EQ. 10) V OUT 1–D IOC + ---------------- ---------------- – t MIN_OFF r DS ON L 2F SW R ISEN = -------------------------------------------------------------------------------------------------------------------------------108A (EQ. 11) Without temperature compensation, the OCP trip point should be evaluated based on the DCR or MOSFET rDS(ON) values at the maximum device’s temperature. While configured as multi-phase operation (VSEN2- > VCC400mV), the channel OCP has 7 clock cycles delay before entering hiccup mode. In dual-output operation, the 7-clock cycle delay on Channel2 is bypassed so the circuit responds to over current condition immediately. In this mode, the 7-clock cycle delay in Channel1 is still active. The fast OCP response on Channel1 will be rely on the FN6641.2 February 9, 2015 ISL8120 OCP on ISHARE pin where the voltage on this pin represents the Channel1 current. ISHARE OCP Refer to the block diagram, ISHARE pin sources out a current IAVG_CS with 15µA offset. In the 2-phase mode, IAVG_CS is the average of both Channels 1 and 2 sampled currents as calculated in Equation 12. ICS1 + ICS2 IAVG_CS = ----------------------------------2 (EQ. 12) When both channels operate independently, the average function is disabled, and the current correction block of Channel 2 is also disabled. The IAVG_CS is Channel 1 sensed current ICS1. Channel 1 makes any necessary current correction by comparing the voltages at ISET and ISHARE pins (for 3-phase, two ISL8120s configuration). When the share bus does not connect to other ICs, the ISET and ISHARE pins can be shorted together and grounded via a single resistor to ensure zero share error. While in the dual-output mode, IAVG_CS is a copy of channel1’s sampled current. In multiphase operation, the VISHARE represents the average current of all ISL8120 and compares with the ISHARE pin precision 1.2V threshold to determine the overcurrent condition. At the same time, each channel has additional overcurrent trip point at 108µA with 7-cycle delay for channel overcurrent protection. This scheme helps protect against loss of channel(s) in multi-phase mode so that no single channel could carry excessive current in such event. With RISHARE = 10kIt would make the channel current OCP and ISHARE OCP trip at the same over current level; (108µA + 15µA) x 10k1.23V. Note that it is not necessary for the RISHARE to be scaled to trip at the same level as the 108µA OCP comparator if the application allows. For instance, when Channel1 operates independently, the OC trip set by 1.2V comparator can be lower than 108A trip point. To set the ISHARE OCP in the multi-phase configuration, the RISEN must be determined first by using Equations 10 or 11. The IOC in Equations 10 or 11 is overcurrent for each phase, which is approximately IOC_total/number of phases. Upon determining RISET, Equations 7, 8, 9, and 11 can be used to determine ISHARE OCP, as shown in Equation 12. 1.2V R ISHARE = ----------------------------------------------------------------------N CNTL I AVG_CS + 15A i (EQ. 13) i=1 R ISET = R ISHARE N CNTL where NCNTL is the number of the ISL8120 controllers in parallel or multiphase operations. For the RISEN chosen for OCP setting, the final value is usually higher than the number calculated from Equation 9. The reason for which is practical, especially for low DCR applications since the PCB and inductor pad soldering resistance would have large effects in total impedance, affecting the DCR voltage to be sensed. Current Sharing Loop When the ISL8120 operates in 2-phase mode (VSEN2- is pulled within VCC - 400mV), the current control loop keeps Channel 1 and Channel 2 currents in balance. The sensed currents from both channels are combined to create an average current reference (IAVG), which represents average current of both channel currents. The signal IAVG is then subtracted from the individual sensed current (ICS1 or ICS2) to produce a current correction signal for each channel. The block diagram of current sharing control circuit is shown in Figure 24. Submit Document Feedback 29 FN6641.2 February 9, 2015 ISL8120 DCR SENSING IOUT1 VOUT L1 IOUT1 VOUT PHASE1 L1 DCR1 C rDS(ON) SENSING IOUT2 PHASE1 DCR2 DCR1 R R L2 C LOW-SIDE MOSFET RISEN1 RISEN1 VOUT PHASE2 (PTC) (PTC) RISEN2 ISEN1B ISEN1B ISEN1A ISEN2A ISEN1A VCC ISEN2B DCR2 AMP DCR1 AMP ICS2 ICS1 400mV VSEN2- CHANNEL 1 PWM CONTROL BLOCK VSEN2+ E/A CHANNEL 1 CURRENT CORRECTION + BLOCK - IAVG_CS +15µA ISHARE + 2 + IAVG - + - ICSH_ERR CURRENT SHARE BLOCK CHANNEL 2 CURRENT CORRECTION BLOCK CHANNEL 2 PWM CONTROL BLOCK IAVG_CS ISET CHANNEL 1 IAVG_CS +15µA RISET 1.2V AVG_OC COMP ITRIP=108A SOFT-START & FAULT LOGIC 7 CYCLES DELAY CHANNEL 2 SOFT-START & FAULT LOGIC OC2 COMP VISHARE 7 CYCLES DELAY IAVG = (ICS1 + ICS2) / 2 ITRIP=108µA OC1 COMP IAVG_CS = IAVG or ICS1 ICSH_ERR = (VISARE - VISET)/GCS FIGURE 23. SIMPLIFIED CURRENT SAMPLING AND OVERCURRENT PROTECTION Submit Document Feedback 30 FN6641.2 February 9, 2015 ISL8120 IAVG = (ICS1 + ICS2) / 2 IAVG_CS = IAVG or ICS1 ERROR AMP 2 ERROR AMP 1 ISHARE = IAVG_CS + 15µA ISET = IAVG_CS + 15µA ICS1 IAVG_CS - + CURRENT MIRROR BLOCK SHARE BUS RISHARE + - + VERROR1 ICS2 CURRENT MIRROR BLOCK ICSH_ERR ISHARE - + ICSH_ERR IAVG_CS+15µA CURRENT SHARING ERROR BLOCK IAVG_CS+15µA RISET CURRENT CORRECTION BLOCK ICSH_ERR - ICSH_ERR VCC CURRENT CORRECTION BLOCK - VERROR2 400mV IAVG_CS VSEN2- CURRENT CORRECTION BLOCK ISET RISHARE=RISET/NCTRL VSEN1- VSEN1+ VMON1 FIGURE 24. SIMPLIFIED CURRENT SHARE AND INTERNAL BALANCE IMPLEMENTATION VIN REN/VFF_up REN/VFF_low With voltage loop EN/FF1,2 COM1/2 VSEN1+ CLKOUT EN/FF1,2 VSEN1/2- VSEN1ISL81201 ISHARE ISET COM1/2 FSYNC VSEN1/2- VCC ISL81202 ISHARE RISET1 ISET COM1/2 FSYNC VCC ISL81203 ISHARE ISET CLKOUT RISET3 RISET2 RISHARE2 RISHARE1 EN/FF1,2 RISHARE3 SHARE BUS RISHARE_ = RISET_ FIGURE 25. SIMPLIFIED 6-PHASE SINGLE OUTPUT IMPLEMENTATION Submit Document Feedback 31 FN6641.2 February 9, 2015 ISL8120 CURRENT SHARE CONTROL IN MULTIPHASE SINGLE OUTPUT WITH SHARED COMP VOLTAGE In multiphase/multi-IC implementation with one single error amplifier for the voltage loop, all COMP pins must be tied together. Therefore, all other channels’ error amplifiers that are not used in voltage loop should be disabled with their corresponding VSEN- pulled to VCC, as shown in Figure 25. For current sharing purposes, all ISHARE pins must also be tied together. The share bus (VISHARE) represents the average current of all ISL8120s connected to the same ISHARE bus. The ISHARE pin sources a copy of the IAVG_CS with 15µA offset (IAVG_CS equals to IAVG or ICS1 depending upon the configuration). The ISET pin also sources out a copy of IAVG_CS with 15µA offset. The voltage on ISET pin represents individual current for each IC. The current share error signal (ICSH_ERR) is then fed into the current correction block to adjust each channel’s PWM pulse accordingly. operation. The internal linear regulator’s input (VIN) can range between 3V to 22V. PVCC pin is the output of the internal linear regulator and it provides power for both the internal MOSFET drivers through the PVCC pin. VCC pin is the bias input for the IC small signal analog circuitry. By connecting PVCC to VCC pin, the internal linear regulator supplies bias power to VCC. The VCC pin should be connected to the PVCC pin with an RC filter to prevent high frequency driver switching noise from the analog circuitry. When VIN drops below 5.0V, the pass element will saturate; PVCC will track VIN with a dropout of the linear regulator. When used with an external 5V supply, the VIN pin is recommended to be tied directly to PVCC. 2.65V TO 5.6V 2W It is recommended to have 3 analog signals: CLKOUT-SYNC, ISHARE, and EN/FF for communication among the paralleled modules. All the modules are synchronized and the phase shift can also be configured to optimal to reduce the input current ripple by interleaving effects. The connections of these three wires allows the system to be started at the same time and achieve good current balance in start-up without overcurrent trip. Internal Series Linear and Power Dissipation The VIN pin is connected to PVCC with an internal series linear regulator. The PVCC and VIN pins should have the recommended bypass ceramic capacitors (10µF) connected to GND for proper Submit Document Feedback 32 PVCC VCC VIN Z1 Z2 5V FIGURE 26. INTERNAL REGULATOR IMPLEMENTATION The LDO is capable of supplying 250mA with regulated 5.4V output. In 3.3V input applications, when the VIN pin voltage is 3V, the LDO can still supply 150mA while maintaining LDO output voltage higher than VCC falling threshold to keep IC operating. Figure 27 shows the LDO voltage drop under different load current. However, its thermal capability should not be exceeded. The power dissipation inside the IC could be estimated with Equation 14. P IC = VIN – PVCC I VIN + P DR Q G1 N Q1 Q G2 N Q2 I VIN = ------------------------------ + ------------------------------ PVCC F SW + I Q_VIN V GS2 V GS1 (EQ. 14) 6.0 5.5 5.0 PVCC (V) The power module controlled by ISL8120 with its own voltage loop can be paralleled to supply one common output load with its integrated Master-Slave current sharing control, as shown in the “Typical Application Circuits” on page 13. A resistor RCSR need to be inserted between VSEN1- pin and the lower resistor of the voltage sense resistor divider for each module. With this resistor, the correction current sourcing from the VSEN1- pin will create a voltage offset to maintain even current sharing among modules. The recommended value for the VSEN1- resistor RCSR is 100 and it should not be large in order to keep the unity gain amplifier input pin impedance compatibility. The maximum source current from the VSEN1- pin is 350µA, which is combined with RCSR to determine the current sharing regulation range. The generated correction voltage on RCSR is suggested to be within 5% of VREF (0.6V) to avoid fault triggering of UV/OV and PGOOD during dynamic events. 10µF 1µF If one single external resistor is used as RISHARE connecting the ISHARE bus to ground for all the ICs in parallel, RISHARE should be set equal to RISET/NCTRL (where NCNTL is the number of the ISL8120 controllers in parallel or multiphase operations), and the share bus voltage (VISHARE) set by the RISHARE, represents the average current of all channels. RISHARE can also be set by putting one resistor in each IC’ s ISHARE pin and using the same value with RISET (RISHARE = RISET), which results in the total equivalent resistance value as RISET/NCTRL. CURRENT SHARE CONTROL LOOP IN MULTI-MODULE WITH INDEPENDENT VOLTAGE LOOP 3V TO 22V 4.5 PVCC @ (250mA + Iq) 4.0 3.5 PVCC @ (100mA + Iq) 3.0 PVCC @ (140mA + Iq) 2.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 VIN PIN VOLTAGE (V) FIGURE 27. PVCC vs VIN VOLTAGE FN6641.2 February 9, 2015 ISL8120 voltage applied to its corresponding EN/FF pin. See “Voltage Feed-forward” on page 24. P DR = P DR_UP + P DR_LOW R HI1 R LO1 P Qg_Q1 P DR_UP = -------------------------------------- + ---------------------------------------- --------------------R + R R + R 2 HI1 EXT1 LO1 EXT1 Frequency Synchronization and Phase Lock Loop R HI2 R LO2 P Qg_Q2 P DR_LOW = -------------------------------------- + ---------------------------------------- --------------------R + R R + R 2 HI2 EXT2 LO2 EXT2 (EQ. 15) Q G1 PVCC 2 P Qg_Q1 = --------------------------------------- F SW N Q1 V GS1 Q G2 PVCC 2 P Qg_Q2 = --------------------------------------- F SW N Q2 V GS2 The FSYNC pin has two primary capabilities: fixed frequency operation and synchronized frequency operation. By tying a resistor (RFSYNC) to GND from the FSYNC pin, the switching frequency can be set at any frequency between 150kHz and 1.5MHz. The value of RFSYNC can be estimated using Equation 16. The frequency setting curve shown in Figure 30 is also provided to assist in selecting the correct value for RFSYNC. 1,600 SWITCHING FREQUENCY (kHz) R GI2 R EXT2 = R G2 + ------------N Q2 R GI1 R EXT2 = R G1 + ------------N Q1 Where the gate charge (QG1 and QG2) is defined at a particular gate to source voltage (VGS1and VGS2) in the corresponding MOSFET datasheet; IQ_VIN is the driver’s total quiescent current with no load at drive outputs; NQ1 and NQ2 are number of upper and lower MOSFETs, respectively. To keep the IC within its operating temperature range, an external power resistor could be used in series with VIN pin to bring the heat out of the IC, or and external LDO could be used when necessary. PVCC 1,400 1,200 1,000 800 600 400 200 0 20 40 60 80 100 120 140 160 180 200 220 240 260 R_FS (kΩ) FIGURE 30. RFS vs SWITCHING FREQUENCY BOOT D . 4 CGD RHI1 RLO1 R FSYNC k = 4.671 10 Fsw kHz G RG1 UGATE CDS RGI1 CGS Q1 S PHASE FIGURE 28. TYPICAL UPPER-GATE DRIVE TURN-ON PATH PVCC D CGD RHI2 LGATE RLO2 G RG2 CDS RGI2 CGS Q2 S GND FIGURE 29. TYPICAL LOWER-GATE DRIVE TURN-ON PATH Oscillator The Oscillator is a sawtooth waveform, providing for leading edge modulation with 350ns minimum PWM off-time. The oscillator (Sawtooth) waveform has a DC offset of 1.0V. Each channel’s peak-to-peak of the ramp amplitude is set proportional the Submit Document Feedback 33 – 1.04 (EQ. 16) By connecting the FSYNC pin to an external square pulse waveform (such as the CLOCK signal, typically 50% duty cycle from another ISL8120), the ISL8120 will synchronize its switching frequency to the fundamental frequency of the input waveform. The maximum voltage to the FSYNC pin is VCC + 0.3V. The Frequency Synchronization feature will synchronize the leading edge of CLKOUT signal with the falling edge of Channel 1’s PWM clock signal. The CLKOUT is not available until the PLL locks. The locking time is typically 130µs for FSW = 500kHz. EN/FF1 is released for a soft-start cycle until the FSYNC stabilized and the PLL is in locking. The PLL circuits control only EN/FF1, and control Channel 2’s soft-start instead of EN/FF2. Therefore, it is recommended to connect all EN/FF pins together in multiphase configuration. The loss of a synchronization signal for 13 clock cycles causes the IC to be disabled until the PLL returns locking, at which point a soft-start cycle is initiated and normal operation resumes. Holding FSYNC low will disable the IC. Differential Amplifier for Remote Sense The differential remote sense buffers help compensate the droop due to load on the positive and negative rails and maintain the high system accuracy of ±0.6%. They have precision unity gain resistor matching networks, which has a ultra low offset of 1mV. FN6641.2 February 9, 2015 ISL8120 VSENSE- (REMOTE) 10 VOUT (LOCAL) VSENSE+ (REMOTE) CSEN GND (LOCAL) 10 RFB ROS ZFB VSEN- VCC VSEN+ VMON ZCOMP FB PGOOD COMP 400mV GAIN=1 VREF OV/UV COMP ERROR AMP PGOOD FIGURE 31. SIMPLIFIED REMOTE SENSING IMPLEMENTATION The output of the remote sense buffer is connected directly to the internal OV/UV comparator. As a result, a resistor divider should be placed on the input of the buffer for proper regulation, as shown in Figure 31. The VMON pin should be connected to the FB pin by a standard feedback network. The output voltage can be set by using Equation 17: R FB V OUT = V ref 1 + ------------ R OS (EQ. 17) To optimize system accuracy, it is highly recommended to include this impedance into calculation and use resistor with resistance as low as possible for the lower leg (ROS) of the feedback resistor divider. Note that any RC filter at the inputs of the differential amplifier, will contribute as a pole to the overall loop compensation. VCC I = VSEN+ + 1µA 40k 20k VSEN+ 1µA 20k RDIF = -600k VSEN- 20k 20k FIGURE 32. EQUIVALENT DIFFERENTIAL AMPLIFER The differential remote sense buffer has a precision unity gain resistor matching network, which has a ultra low offset of 1mV. This true remote sensing scheme helps compensate the droop due to load on the positive and negative rails and maintain the high system accuracy of ±0.6%. As some applications will not need the differential remote sense, the output of the remote sense buffer can be disabled and be placed in high impedance by pulling VSEN- within 400mV of VCC. Submit Document Feedback 34 In such an event, the VMON pin can be used as an additional monitor of the output voltage with a resistor divider to protect the system against single point of failure, which occurs in the system using the same resistor divider for the UV/OV comparator and the output regulation. The resistor divider ratio should be the same as the one for the output regulation so that the correct voltage information is provided to the OV/UV comparator. Figure 33 shows the differential sense amplifier can be directly used as a monitor without pulling VSEN- high. Internal Reference and System Accuracy The internal reference is set to 0.6V. Including bandgap variation and offset of differential and error amplifiers, it has an accuracy of ±0.6% over commercial temperature range, and 0.9% over industrial temperature range. While the remote sense is not used, its offset (VOS_DA) should be included in the tolerance calculation. Equations 18 and 19 show the worst case of system accuracy calculation. VOS_DA should set to zero when the differential amplifier is in the loop, the differential amplifier’s input impedance (RDIF) is typically -600k with a tolerance of 20% (RDIF%) and can be neglected when ROS is less than 100. To set a precision setpoint, ROS can be scaled by two paralleled resistors. Figure 34 shows the tolerance of various output voltage regulation for 1%, 0.5%, and 0.1% feedback resistor dividers. Note that the farther the output voltage setpoint away from the internal reference voltage, the larger the tolerance; the lower the resistor tolerance (R%), the tighter the regulation. R FB 1 – R% %min = Vref 1 – Ref% – V OS_DA 1 + ---------------------------------------- R OSMAX (EQ. 18) 1 R OSMAX = ----------------------------------------------------------------------------------------------------1 1 ----------------------------------------- + ---------------------------------------------------R OS 1 + R% R DIF 1 + R DIF % FN6641.2 February 9, 2015 ISL8120 VOUT RFB RFB ROS ROS ZCOMP VSEN+ VCC GND VSEN- VMON FB PGOOD COMP 400mV GAIN=1 VREF OV/UV COMP ERROR AMP PGOOD FIGURE 33. DUAL OUTPUT VOLTAGE SENSE FOR SINGLE POINT OF FAILURE PROTECTION R FB 1 – R% %max = Vref 1 – Ref% – V OS_DA 1 + ---------------------------------------- R OSMIN (EQ. 19) 1 R OSMIN = ----------------------------------------------------------------------------------------------1 1 --------------------------------------- + ------------------------------------------------R OS 1 – R % R DIF 1 – R DIF % 2.5 R% = 1% 2.0 OUTPUT REGULATION (%) 1.5 0.5% 1.0 0.1% 0.5 0.0 -0.5 0.1% -1.0 0.5% -1.5 -2.0 -2.5 1% 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT VOLTAGE (V) FIGURE 34. OUTPUT REGULATION WITH DIFFERENT RESISTOR TOLERANCE FOR Ref% = ±0.6% DDR and Dual Mode Operation If the CLKOUT/REFIN is less than 29% of VCC, an external soft-start ramp (0.6V) can be in parallel with the Channel 2’s internal soft-start ramp for DDR/tracking applications (DDR Mode). CLKOUT/REFIN pin. As for the external input signal and internal reference signal (ramp and 0.6V), the one with the lowest voltage will be the one to be used as the reference comparing with FB signal. So in DDR configuration, VTT channel should start-up later after its internal soft-start ramp in which way the VTT will track the voltage on REFIN pin derived from VDDQ. This can be achieved by adding more filtering at EN//FF1 compared with EN/FF2. Since the UV/OV comparator uses the same internal reference 0.6V, to guarantee UV/OV and Pre-charged start-up functions of Channel 2, the target voltage derived from Channel 1 (VDDQ) should be scaled close to 0.6V, and it is suggested to be slightly above (+2%) 0.6V with an external resistor divider, which will have Channel 2 use the internal 0.6V reference after soft-start. Any capacitive load at REFIN pin should not slow down the ramping of this input 150mV lower than the Channel 2’ internal ramp. Otherwise, the UV protection could be fault triggered prior to the end of the soft-start. The start-up of Channel 2 can be delayed to avoid such situation happening, if high capacitive load presents at REFIN pin for noise decoupling. During shutdown, Channel 2 will follow Channel 1 until both channels drops below 87%, at which point both channels enter UV protection zone. Depending on the loading, Channel 1 might drop faster than Channel 2. To solve this race condition, Channel 2 can either power up from Channel 1 or bridge the Channel 1 with a high current Schottky diode. If the system requires to shutdown both channels when either has a fault, tying EN/FF1 and EN/FF2 will do the job. In DDR mode, Channel 1 delays 60° over Channel 2. In Dual mode, depending upon the resistor divider level of REFIN from VCC, the ISL8120 operates as a dual-PWM controller for two independent regulators with a phase shift, as shown in Table 2. The phase shift is latched as VCC raises above POR and cannot be changed on the fly. The output voltage (typical VTT output) of Channel 2 tracks with the input voltage (typical VDDQ*(1+k) from Channel 1) at the Submit Document Feedback 35 FN6641.2 February 9, 2015 ISL8120 TABLE 2. MODE DECODING REFIN RANGE PHASE for CHANNEL 2 WRT CHANNEL 1 REQUIRED REFIN DDR <29% of VCC -60° 0.6V Dual 29% to 45% of VCC 0° 37% VCC Dual 45% to 62% of VCC 90° 53% VCC Dual 62% to VCC 180° VCC VCC VDDQ VSEN2- PHASE-SHIFTED CLOCK ISL8120 STATE MACHINE k*R CLKOUT/REFIN 400mV R VTT k = ------------ – 1 0.6V Internal SS 0.6V FB2 E/A2 FIGURE 35. SIMPLIFIED DDR IMPLEMENTATION Layout Considerations MOSFETs switch very fast and efficiently. The speed at which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device overvoltage stress. Careful component selection, layout, and placement minimizes these voltage spikes. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. There are two sets of critical components in a DC/DC converter using a ISL8120 controller. The power components are the most critical because they switch large amounts of energy. Next, are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. The power components should be placed first, which include the MOSFETs, input and output capacitors, and the inductors. It is important to have a symmetrical layout for each power train, preferably with the controller located equidistant from each. Symmetrical layout allows heat to be dissipated equally across all power trains. Equidistant placement of the controller to the power trains (it controls through the integrated drivers), helps keep the gate drive traces equally short, resulting in equal trace impedances and similar drive capability of all sets of MOSFETs. Submit Document Feedback 36 When placing the MOSFETs, try to keep the source of the upper FETs and the drain of the lower FETs as close as thermally possible. Input high-frequency capacitors, CHF, should be placed close to the drain of the upper FETs and the source of the lower FETs. Input bulk capacitors, CBULK, case size typically limits following the same rule as the high-frequency input capacitors. Place the input bulk capacitors as close to the drain of the upper FETs as possible and minimize the distance to the source of the lower FETs. Locate the output inductors and output capacitors between the MOSFETs and the load. The high-frequency output decoupling capacitors (ceramic) should be placed as close as practicable to the decoupling target, making use of the shortest connection paths to any internal planes, such as vias to GND next or on the capacitor solder pad. The critical small components include the bypass capacitors (CFILTER) for VCC and PVCC, and many of the components surrounding the controller including the feedback network and current sense components. Locate the VCC/PVCC bypass capacitors as close to the ISL8120 as possible. It is especially important to locate the components associated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to EMI pick-up. A multi-layer printed circuit board is recommended. Dedicate one solid layer, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to output inductors short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the phase nodes. Use the remaining printed circuit layers for small signal wiring. ROUTING UGATE, LGATE, AND PHASE TRACES Great attention should be paid to routing the UGATE, LGATE, and PHASE traces since they drive the power train MOSFETs using short, high current pulses. It is important to size them as large and as short as possible to reduce their overall impedance and inductance. They should be sized to carry at least one ampere of current (0.02” to 0.05”). Going between layers with vias should also be avoided, but if so, use two vias for interconnection when possible. Extra care should be given to the LGATE traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibility of shoot-through. It is also important to route each channels UGATE and PHASE traces in as close proximity as possible to reduce their inductances. CURRENT SENSE COMPONENT PLACEMENT AND TRACE ROUTING One of the most critical aspects of the ISL8120 regulator layout is the placement of the inductor DCR current sense components and traces. The R-C current sense components must be placed as close to their respective ISENA and ISENB pins on the ISL8120 as possible. FN6641.2 February 9, 2015 ISL8120 The sense traces that connect the R-C sense components to each side of the output inductors should be routed away from the noisy switching components. These traces should be routed side by side, and they should be very thin traces. It’s important to route these traces as far away from any other noisy traces or planes as possible. These traces should pick up as little noise as possible. These traces should also originate from the geometric center of the inductor pin pads and that location should be the single point of contact the trace makes with its respective net. It is recommended to fill the thermal pad area with vias. A typical via array fills the thermal pad foot print such that their centers are 3x the radius apart from each other. Keep the vias small but not so small that their inside diameter prevents solder wicking through during reflow. Connect all vias to the ground plane. It is important the vias have a low thermal resistance for efficient heat transfer. It is important to have a complete connection of the plated-through hole to each plane. GENERAL POWERPAD DESIGN CONSIDERATIONS The following is an example of how to use vias to remove heat from the IC. FIGURE 36. PCB VIA PATTERN For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 37 FN6641.2 February 9, 2015 ISL8120 Package Outline Drawing L32.5x5B 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 5/10 4X 3.5 5.00 28X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 32 25 1 5.00 24 3 .30 ± 0 . 15 17 (4X) 8 0.15 9 16 0.10 M C A B + 0.07 32X 0.40 ± 0.10 TOP VIEW 4 32X 0.23 - 0.05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 80 TYP ) ( ( 28X 0 . 5 ) SIDE VIEW 3. 30 ) (32X 0 . 23 ) C 0 . 2 REF 5 ( 32X 0 . 60) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. Submit Document Feedback 38 FN6641.2 February 9, 2015