Application Note 1878 Author: Oscar Mansilla ISL75052SEH PSPICE Macro-Model Introduction The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. The ISL75052SEH is a radiation hardened, single output LDO specified for an output current of 1.5A. The device operates from an input voltage range of 4.0V to 13.2V and provides for output voltages of 0.6V to 12.7V. The output is adjustable based on a resistor divider setting. Dropout voltages as low as 75mV (at 0.5A) typical can be realized using the device. This allows the user to improve the system efficiency by lowering VIN to nearly VOUT. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” The SPICE model for the ISL75052SEH was developed to help system designers evaluate the operation of this IC prior or in conjunction with proto-typing a system design. This model accurately simulates typical performance characteristics at room temperature (+25°C) such as frequency analysis, steady state analysis, and transient analysis. Behaviors not supported are the bias current cancellation circuit and some temperature analysis. Functionality has been tested on ORCAD 10.0 and CADENCE ORCAD 16.5. Other SPICE simulators may be used, however, the model may require translation. In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. Project Files The zip file: ISL75052SEH.zip contains the project file ISL75052SEH.opj to be used in ORCAD simulator. The project file has the model definition file (.lib), symbol file (.olb) and various design files (.dsn) to simulate start up, OCP, load transients, etc. The application circuit is shown in Figure 1. Figures 2 through 9 show a comparison of the simulation results versus bench results for various tests. The close agreement between model and actual measurement demonstrate the accuracy of the model, making it a very powerful tool. Reference Documents • ISL75052SEH Data Sheet; FN8456 • ISL75052SEH SMD 5962-13220 License Statement The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable license to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. V1 = 1 V2 = 1 TD = 100u TR = 1u TF = 1u PW = 1 PER = 2 VEN 0 R19 VIN C8 1k 10k R12 ISL75052SRH V1 = 13.2 V2 = 13.2 TD = 1u TR = 500u TF = 100u PW = 1 PER = 2 C1 100u VIN1 C2 100u C3 0.1u U1 0.1u C9 VOUT1 BYP VOUT2 ADJ 0.1u RC1 0.060 RC2 0.060 0 RC3 0.005 0 VIN1 EN VIN2 GND2 VIN3 COMP R16 5.49k EN R13 C10 22k 1n COMP 0 NC1 GND1 NC2 PG OCP VOUT C13 C6 0.1u RC4 0.060 RC5 0.060 RC6 0.005 + - 0 C11 I1 LOAD C5 100u VCCX VCCX R8 C4 100u PG 0.1u TDELAY = 1m TRISE = 10u TFALL = 10u TWIDTH = 1 TPULSE = 1m ISTART = .15 IPULSE = 1.6 RLOAD = 1MEG 2.2k R7 0 2.2n 15.8k R1 4.66k R11 3000 0 0 FIGURE 1. ISL75052SEH PSPICE SCHEMATIC August 2, 2013 AN1878.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1878 Simulation Performance Curves 5.0V TIMEBASE = 1ms/DIV C1 to C4 = 1V/DIV VIN EN 4.0V PGOOD VIN EN VOUT 3.0V VOUT 2.0V PGOOD 1.0V 0V 0ms FIGURE 2. +25°C START-UP WITH ENABLE, VIN = 4V, VOUT = 2.5V, IOUT = 1.5A v(VIN) 2ms V(R12:1) V(VOUT) V(PG) 4ms 6ms 8ms 10ms Time FIGURE 3. SIMULATED +25°C START-UP WITH ENABLE, VIN = 4V, VOUT = 2.5V, IOUT = 1.5A 2.52V TIMEBASE = 500µs/DIV VOUT = 20mV/DIV VOUT = 5mV/DIV 2.50V SEL>> 2.48V v(vout) 2.0A IOUT = 500mA/DIV 1.0A IOUT = 200mA/DIV 0A 0s FIGURE 4. LOAD STEP RESPONSE, +25°C, VIN = 4.0V, VOUT = 2.5V, IOUT = 0.15A TO 1.6A, COUT = 200µF, 30mΩ I(I1:P) 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms Time FIGURE 5. SIMULATED LOAD STEP RESPONSE, +25°C, VIN = 4.0V, VOUT = 2.5V, IOUT = 0.15A TO 1.6A, COUT = 200µF, 30mΩ 2.54V 2.52V TIMEBASE = 500µs/DIV VOUT = 20mV/DIV VOUT = 5mV/DIV 2.50V SEL>> 2.48V v(vout) 2.0A IOUT = 500mA/DIV 1.0A IOUT = 500mA/DIV 0A FIGURE 6. LOAD STEP RESPONSE +25°C, VIN = 4.0V, VOUT = 2.5V, IOUT = 0A TO 1.6A, COUT = 200µF, 30mΩ 2 0s I(I1:P) 1.0ms 2.0ms 3.0ms 4.0ms 5.0ms Time FIGURE 7. SIMULATED LOAD STEP RESPONSE +25°C, VIN = 4.0V, VOUT = 2.5V, IOUT = 0A TO 1.6A, COUT = 200µF, 30mΩ AN1878.0 August 2, 2013 Application Note 1878 Simulation Performance Curves (Continued) 1 60 2 180d 40 120 30 90 20 60 10 30 0 0 -10 PHASE (°) 150 PHASE (°) -30 GAIN (dB) 100d 40 PHASE (°) GAIN (dB) 50 -20 -60 -30 -90 -40 -120 -50 -150 -60 500 80 180 5k 50k 500k 0 0d GAIN (dB) -40 -100d -180 FREQUENCY (Hz) FIGURE 8. GAIN PHASE PLOTS, VIN = 4V, VOUT = 2.5V, IOUT = 1.5A, RCOMP = 22k, CCOMP = 1nF, COUT = 200µF, 30mΩ, PHASE MARGIN = 84.56°, GAIN MARGIN = 18.06dB -80 >> -180d 500Hz 1 1.0KHz db(v(vout)/v(vout2)) 2 10KHz p(v(vout)/v(vout2)) Frequency 100KHz 1.0MHz FIGURE 9. SIMULATED GAIN PHASE PLOTS, VIN = 4V, VOUT = 2.5V, IOUT = 1.5A, RCOMP = 22k, CCOMP = 1nF, COUT = 200µF, 30mΩ, PHASE MARGIN = 84.56°, GAIN MARGIN = 18.06dB Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN1878.0 August 2, 2013