Application Note 1915 Author: Oscar Mansilla ISL70003SEH iSim:PE Model Introduction license. If the Licensee does not accept these terms, permission to use the model is not granted. The ISL70003SEH is a radiation and SEE hardened synchronous buck regulator capable of operating over an input voltage range of 3.0V to 13.2V. The ISL70003SEH uses voltage mode control architecture with feed-forward and switches at a selectable frequency of 500kHz or 300kHz. Loop compensation is externally adjustable to allow for an optimum balance between stability and output dynamic performance. With integrated MOSFETs and class leading radiation performance, this highly efficient single chip power solution is an ideal choice in many space applications. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” The iSim:PE model for the ISL700003SEH was developed to help system designers evaluate the operation of this IC prior to or in conjunction with proto-typing a system design. This model accurately simulates typical performance characteristics such as loop analysis, transient analysis, start-up and steady state analysis at room temperature (+25°C). In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. Reference Documents Schematic File • ISL70003SEH Data Sheet; FN8604 The schematic file: ISL70003SEH.sxsch is the main application schematic to be used in the iSim:PE simulator. The schematic mimics the evaluation board and is designed for 12V input to 3.3V output conversion, see Figure 1. The simulation profile is set up to run an AC and 3A load transient test. Figure 2 through 13 show a comparison of the simulation results for various operating conditions versus actual bench validation data. For more information on iSim:PE visit the iSim online home page. • ISL70003SEH SMD 5962-14203 License Statement The information in this macro-model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable license to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this 22k R2 USE_IC=1 X=5 IC=12 CIN2 L=1.44n RSHUNT=10Meg RESR=29.1m C=1u 100k R16 51k R4 BUFOUT 3k R10 R15 370p 7.15k C15 IC=1 PORVIN DVDD EN AVDD EN BUFOUT BUFINP 10k PGOOD 10n BUFINP PVIN C16 IC=0 BUFINN USE_IC=1 X=4 IC=12 CIN1 L=2.1n RSHUNT=100K RESR=6m C=100u RTCT 12 V1 PGOOD IMON U1 C9 10n VOUT R11 VREFA 10 R1 LX3 C8 IC=5 470n VREFOUTS C1 1n LX4 C10 IC=5 470n LX5 VREFD LX6 C11 IC=5 SYNC ISL70003SEH SYNC 49.9 IC=1.5 C12 USE_IC=1 X=3 IC=3.3 COUT1 L=2.1n RSHUNT=100K RESR=6m C=150u USE_IC=1 X=1 IC=3.3 COUT2 L=1.44n RSHUNT=10Meg RESR=29.1m C=1u ESR=5m IC=3.3 100n COUT3 1x LX8 LX9 SS LX10 100n FB OCSETA R9 VERR 51.1k C5 IC=-430m 12p 6.8n C13 REF C7 220n IC=600m 4.02k R13 NI 4.02k PGND AGND DGND SGND DE NC SEL2 SEL1 FSEL R14 TCLK TDO TSTRIM TDI OCSETB TPGM C6 IC=-430m 3.3u LX7 R12 2.7n D1 LX2 470n DCR=5m L1 IC=1 LX1 RISE=10u DELAY=10u VFINAL=0 VSTART=0 VEN RSRC=1m EN S1 RON=1 ROFF=100Meg 6.8n C14 R6 5.49k R7 25k R8 1n 357 C4 FIGURE 1. ISL70003SEH iSIM:PE APPLICATION SCHEMATIC January 22, 2014 AN1915.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1915 Simulation Performance Curves 12 ENABLE, 5V/DIV x axis = 1ms/DIV 10 INDUCTOR CURRENT, 2A/DIV INDUCTOR CURRENT, 2A/DIV 8 ENABLE, 2V/DIV 6 OUTPUT VOLTAGE, 2V/DIV OUTPUT VOLTAGE, 2V/DIV 4 2 PGOOD, 2V/DIV PGOOD, 10V/DIV 00 FIGURE 2. CHARACTERIZED SOFT-START WITH 6A LOAD 1 2 3 4 5 6 7 8 FIGURE 3. SIMULATED SOFT-START WITH 6A LOAD LXx VOLTAGE, 2V/DIV 10 8 6 4 2 -0 INDUCTOR CURRENT, 200mA/DIV 6.8 LXx VOLTAGE, 5V/DIV 6.6 6.4 6.2 6 5.8 5.6 5.4 OUTPUT VOLTAGE, 10mV/DIV 3.36 INDUCTOR CURRENT, 1A/DIV 3.359 3.358 3.357 OUTPUT VOLTAGE, 20mV/DIV 3.356 0 1 2 3 4 5 6 7 8 9 FIGURE 5. SIMULATED FREQUENCY RESPONSE vs GAIN FIGURE 4. CHARACTERIZED FREQUENCY RESPONSE vs GAIN INDUCTOR CURRENT, 1A/DIV INDUCTOR CURRENT, 2A/DIV 7 6 5 4 3 2 1 -0 Y1 3.55 3.5 3.45 OUTPUT VOLTAGE, 50mV/DIV 3.4 3.35 OUTPUT VOLTAGE, 50mV/DIV 3.3 3.25 FIGURE 6. CHARACTERIZED 6A LOAD TRANSIENT RESPONSE 2 0 1 2 3 4 5 6 7 8 FIGURE 7. SIMULATED 6A LOAD TRANSIENT RESPONSE AN1915.0 January 22, 2014 Application Note 1915 Simulation Performance Curves (Continued) 12 10 8 6 LXx VOLTAGE, 5V/DIV 4 2 LXx VOLTAGE, 2V/DIV -0 Y1 INDUCTOR CURRENT, 5A/DIV PGOOD, 2V/DIV 10 8 OUTPUT VOLTAGE, 2V/DIV 6 OUTPUT VOLTAGE, 2V/DIV 4 2 INDUCTOR CURRENT, 2A/DIV PGOOD, 10V/DIV -0 90 100 110 120 FIGURE 9. SIMULATED OVERCURRENT RESPONSE FIGURE 8. CHARACTERIZED OVERCURRENT RESPONSE 12 10 8 6 LXx VOLTAGE, 2V/DIV 4 2 LXx VOLTAGE, 5V/DIV -0 10 8 INDUCTOR CURRENT, 10A/DIV 6 INDUCTOR CURRENT, 2A/DIV 4 2 -0 OUTPUT VOLTAGE, 2V/DIV 3 OUTPUT VOLTAGE, 0.5V/DIV 2.5 2 1.5 1 SS VOLTAGE, 0.5V/DIV 0.5 SS VOLTAGE, 2V/DIV -00 10 20 GAIN 0 150 60 100 40 50 20 0 -20 -50 -40 -60 -80 10 100 1k 10k 100k 1M 40 200 150 PHASE SIM 100 50 GAIN SIM 0 0 -20 -50 -100 -40 -100 -150 -60 -150 -200 -80 10 PHASE (°) GAIN (dB) 40 80 GAIN (dB) PHASE 200 PHASE (°) 60 30 FIGURE 11. SIMULATED HICCUP RESPONSE IN OCP FIGURE 10. CHARACTERIZED HICCUP RESPONSE IN OCP 80 20 -200 100 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 12. CHARACTERIZED LOOP RESPONSE FIGURE 13. SIMULATED LOOP RESPONSE Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN1915.0 January 22, 2014