Application Note 1710 Author: Oscar Mansilla ISL705xRH and IS706xRH SPICE Model Introduction Project Files The SPICE model for the ISL705XRH and ISL706xRH rad hard supervisory circuits were developed to help system designers evaluate the operation of this IC prior or in conjunction with proto-typing a system design. This model accurately simulates typical performance characteristics at room temperature (+25°C) such as steady state switching, input voltage and output current transients. Behaviors not supported are temperature analysis, process variation, and AC analysis. Functionality has been tested on ORCAD 10.0 and CADENCE ORCAD 16.3. Other SPICE simulators may be used however the model may require translation. The zip file: ISL705xRH_ISL706xRH SPICE FILES.zip contains the project file ISL705ARH.opj to be used in ORCAD simulator. The project file contains two schematics which correlate with the ISL705XRH and ISL706XRH evaluation boards (see Figures 8 and 9). For details on the application schematic refer to the evaluation board user’s guide AN1650 and AN1671. Each schematic has been set up with a time domain simulation profile for quick evaluation of the model. The schematic pages may be accessed through the main directory window in ORCAD (see Figure 1). Reference Documents • ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH Datasheet, FN7662 • ISL705RH Voltage Supervisory Circuit Evaluation Board User’s Guide, AN1650 • ISL706RH Voltage Supervisory Circuit Evaluation Board User’s Guide, AN1671 License Statement The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable license to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macromodel, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macromodel to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. November 9, 2011 AN1710.0 1 FIGURE 1. APPLICATION SCHEMATIC LOCATION Figures 2 through 7 show simulation results of the RESET and PFI transient response. These can be compared to Figure 8 through 13 of the datasheet for model accuracy. Model Parameter List The model has been developed with a single netlist with multiple variables that are automatically modified to meet IC parameters when the part is placed in an ORCAD schematic from the model library. If the user would like to import the netlist to another SPICE simulator the variables must be entered manually. The parameter list spreadsheet maps the variable state to the corresponding version of the IC, so the user can easily modify the netlist and import the model to other SPICE simulators. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright Intersil Americas Inc. 2011. All Rights Reserved. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1710 Simulation Performance Curves VDD VDD RST RST RST RST FIGURE 2. ISL705xRH RESET AND RESET ASSERTION FIGURE 3. ISL705xRH RESET and RESET DEASSERTION VDD VDD RST RST RST RST FIGURE 4. ISL706xRH RESET AND RESET ASSERTION FIGURE 5. ISL706xRH RESET and RESET DEASSERTION PFO PFO PFI PFI FIGURE 6. ISL705xRH PFI TO PFO RESPONSE FIGURE 7. ISL706xRH PFI TO PFO RESPONSE Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 2 AN1710.0 November 9, 2011 3 SECTION 1 (ISL705ARH) SECTION 2 (ISL705BRH) VDD SECTION 3 (ISL705CRH) VDD C1 0.1u 0 ISL705ARH MR R3 383k 0 12V_PFI U1 WDO VDD RST GND WDI PFI PFO WDO RST WDI R6 165k 12V_PFO 0 5V_OV_PFI 0 V3 VDD RST GND WDI PFI PFO WDO_B RST_B R12 100k INVERTER R11 MR VDD WDI_B R9 100k Q1 0 5V_OV_PFO MPS2222 R10 154k -5V V1 = 0 V2 = -5 TD = 1u TR = 1u TF = 5m PW = 1990m PER = 2000m ISL705CRH MR_C 0 0 12V V1 = 0 V2 = 12 TD = 10u TR = 1u TF = 5m PW = 1990m PER = 2000m C3 0.1u U2 WDO U3 WDO RST_OD GND WDI PFI PFO R8 5.1k WDO_C RST_C R14 100k WDI_C R13 Q2 PFO_C 1k MPS2222 -5V 0 VDD MR 1k R7 49.9k V1 MR_B 0 R4 49.9k V1 = 0 V2 = 5 TD = 1u TR = 1u TF = 5m PW = 1990m PER = 2000m ISL705BRH V4 0 FIGURE 8. ISL705xRH SIMULATION APPLICATION SCHEMATIC 0 Application Note 1710 12V MR VDD C2 0.1u AN1710.0 November 9, 2011 4 SECTION 1 (ISL706ARH) SECTION 2 (ISL706BRH) VDD C1 0.1u 0 ISL706ARH MR 5V R3 383k WDO VDD RST PFI C2 0.1u U4 MR GND 0 5V_PFI VDD WDI PFO WDO 0 RST WDI 5V_PFO R6 165k V1 V3 WDI PFO RST_B R12 100k INVERTER R11 R9 100k Q1 0 3.3V_OV_PFO MPS2222 R10 187k -5V V1 = 0 V2 = -5 TD = 1u TR = 1u TF = 5m PW = 1990m PER = 2000m MR VDD WDI_B 0 5V V1 = 0 V2 = 5 TD = 1u TR = 1u TF = 5m PW = 1990m PER = 2000m RST 0 ISL706CRH MR_C U6 WDO RST_OD GND WDI PFI PFO WDO_C R8 3.01k RST_C R14 100k WDI_C R13 Q2 PFO_C 1K MPS2222 -5V 0 VDD VDD WDO_B 1k R7 34.8k 0 WDO PFI C3 0.1u U5 MR GND 0 3.3V_OV_PFI R4 95.3k V1 = 0 V2 = 3.3 TD = 1u TR = 1u TF = 5m PW = 1990m PER = 2000m ISL706BRH MR_B V4 0 AN1710.0 November 9, 2011 FIGURE 9. ISL706xRH SIMULATION APPLICATION SCHEMATIC 0 Application Note 1710 VDD SECTION 3 (ISL706CRH)