Application Note 1867 Author: Kiran Bernard ISL70444SEH SPICE Macro-Model Introduction License Statement The ISL70444SEH features four low-power amplifiers optimized to provide maximum dynamic range. These op amps feature a unique combination of rail-to-rail operation on the input and output as well as a slew enhanced front-end that provides ultra fast slew rates. They also offer low power, low offset voltage, and low temperature drift, making it ideal for applications requiring both high DC accuracy and AC performance. Manufactured in Intersil’s PR40 SOI Process, the ISL70444SEH is immune to latch-up. The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”, a nonexclusive, nontransferable license to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. The SPICE model for the ISL70444SEH Rad Hard Quad Op Amp, was developed to help system designers evaluate the operation of this IC, prior or in conjunction with proto-typing a system design. This model accurately simulates typical performance characteristics at room temperature (+25°C), such as frequency analysis, noise analysis, and slew rate analysis. Behaviors not supported are the bias current cancellation circuit and some temperature analysis. Functionality has been tested on ORCAD 10.0 and CADENCE ORCAD 16.5. Other SPICE simulators may be used, however, the model may require translation. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. Reference Documents • ISL70444SEH Data Sheet; FN8411 • ISL70444SEH SMD 5962-13214 Project Files The zip file: ISL70444SEH.zip contains the project file modelcreator.opj to be used in ORCAD simulator. The project file has the model definition file (.lib), symbol file (.olb) and the schematic page as shown in Figure 1. The simulation profile is set up for AC analysis and sweeps parameter RF for various gain configurations. Figures 2 through 9 show a comparison of the simulation results versus bench results for various tests and it can be seen that the model approximates the IC very well. VDD + - INP U1 + V+ VDD {VDD} VSS {VDD} + - 0 - R2 100 INM - OUT RL {RL} ISL70444SEH R1 0 OUT V- 0.5VAC 0VDC + V1 AC LOOP AC ANALYSIS DB(V(OUT)/V(IN)) P(V(OUT)/V(IN)) 0 {RF} VEE C1 {CL} 0 PARAMETERS: VDD = 18.0 RL = 10k CL = 10p RF = 100k FIGURE 1. BASIC NON-INVERTING GAIN CONFIGURATION IN ORCAD SPICE FOR AC ANALYSIS July 3, 2013 AN1867.0 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1867 Simulation Performance Curves 70 70 60 60 50 40 40 20 10 G = 10 0 -10 20 0 -20 -20 -30 -30 -40 -40 10k 100k 1M G = 10 10 G=1 -10 G=1 1k G = 100 30 G = 100 GAIN (dB) GAIN (dB) 30 -50 100 G = 1000 50 G = 1000 10M -50 100 100M 1k 10k FREQUENCY (Hz) 100k 1M 10 10 68pF 68pF 0 0 27pF 47pF -10 47pF -20 GAIN (dB) GAIN (dB) -10 12pF 27pF -20 12pF -30 -30 -40 -40 -50 100 -50 1k 10k 100k 1M 10M 100M 1 10 100 FIGURE 4. FREQUENCY RESPONSE vs CL 0.03 0.03 0.02 0.02 VOLTAGE (V) 0.04 0.01 0.00 -0.01 -0.03 1.0 1.2 1.4 1.6 TIME (µs) FIGURE 6. SMALL SIGNAL RESPONSE 2 10M 100M -0.01 -0.03 0.8 1M 0.00 -0.02 0.6 100k 0.01 -0.02 0.4 10k FIGURE 5. SIMULATED FREQUENCY RESPONSE vs CL 0.04 0.2 1k FREQUENCY (Hz) FREQUENCY (Hz) VOLTAGE (V) 100M FIGURE 3. SIMULATED FREQUENCY RESPONSE vs GAIN, VS = ±18V FIGURE 2. FREQUENCY RESPONSE vs GAIN, VS = ±18V -0.04 0.0 10M FREQUENCY (Hz) 1.8 2.0 -0.04 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TIME (µs) FIGURE 7. SIMULATED SMALL SIGNAL RESPONSE AN1867.0 July 3, 2013 Application Note 1867 4 4 3 3 2 2 VOLTAGE (V) VOLTAGE (V) Simulation Performance Curves (Continued) 1 0 -1 1 0 -1 -2 -2 -3 -3 -4 0.2 0.4 0.6 0.8 1.0 1.2 TIME (µs) 1.4 1.6 FIGURE 8. LARGE SIGNAL RESPONSE 1.8 2.0 -4 0.0 0.2 0.4 0.6 0.8 1.0 1.2 TIME (µs) 1.4 1.6 1.8 FIGURE 9. SIMULATED LARGE SIGNAL RESPONSE Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN1867.0 July 3, 2013