Application Note 1771 Author: Manjing Xie ISL8130EVAL3Z - Sepic Converter Introduction Features ISL8130EVAL3Z is a sepic converter, which features the universal PWM controller, ISL8130. The evaluation board delivers 10V output at 2A. All the necessary components are within the 1.78” x 1.24” PCB area. • Operates From: - 4.5V to 5.5V Input for 5V Input - 5.5V to 16V Input The ISL8130 is designed to drive N-Channel MOSFETs in a synchronous rectified buck topology for up to 25A instant MOSFET current and can be configured for boost, buck/boost and sepic converters as well. The ISL8130 integrates control, output adjustment, monitoring and protection functions into a single package. The ISL8130 provides simple, voltage mode control with fast transient response. This application note describes how to use the ISL8130 to generate VOUT from power supply of voltage either higher or lower than the VOUT. Evaluation Board Specifications • Resistor-Selectable Switching Frequency from 100kHz to 1.4MHz • Voltage Margining and External Reference Tracking Modes • Kelvin Current Sensing - Upper MOSFET rDS(ON) for Current Sensing for Buck and Buck/Boost Converter - Precision Resistor/Inductor DCR for Boost and Sepic Converter • Extensive Protection Functions: - Overvoltage, Overcurrent, Undervoltage • Power Good Indicator TABLE 1. EVALUATION BOARD ELECTRICAL SPECIFICATIONS SPEC DESCRIPTION MIN TYP MAX UNIT 5.6 10 16 V VIN Board Input Range IOC Input Current VOUT IOUT = 0A 9.5 IOUT VIN = 5.6V 2 5 A 10 10.5 V A VIN = 5.6V, IOUT = 2A 88.6 % VIN = 8.4V, IOUT = 2A 90.3 % Recommended Equipment The following equipment is recommended for evaluation: • 0V to 20V power supply with 10A source current capability • Electronic load capable of sinking 2A @ 20V • Digital Multi meters (DMMs) • 100MHz Quad-Trace Oscilloscope FIGURE 1. ISL8130EVAL3Z TOP VIEW TABLE 2. RECOMMENDED COMPONENT SELECTION FOR QUICK EVALUATION VOUT (V) R4 (k) VIN (V) IOUT (A) FSW(kHz)/R5(k) MOSFET FORWARD DIODE INDUCTOR (L, ISAT MEASURED IN PARALLEL) 7 9.53 5.6 to 14 2 500kHz/28.7k BSO051N03 MS SL43 4.7µH, 6A 10 6.34 5.6 to 16 2 500kHz/28.7k BSC059N04 LS SL42 4.7µH, 7A 12 5.23 5.6 to 14 2 500kHz/28.7k BSC057N03 LS SL42 4.7µH, 9A NOTES: 1. Please select the output capacitor with a voltage rating higher than the output. 2. Please contact Intersil Sales for assistance. August 7, 2012 AN1771.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Copyright Intersil Americas Inc. 2012. All Rights Reserved. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. Application Note 1771 FIGURE 2. ISL8130EVAL3Z TEST SET-UP Quick Test Setup Probe Set-up 1. Ensure that the Evaluation board is correctly connected to the power supply and the electronic load prior to applying any power. Please refer to Figure 2 for proper set-up. 2. Leave JP3 in the open position. 3. Turn on the power supply; VIN< 16V. OUTPUT CAP OUTPUT OUTPUT CAP CAP OR ORMOSFET MOSFET 4. Adjust input voltage VIN within the specified range and observe output voltage. The output voltage variation should be within 5%. 5. Adjust load current within 2A. The output voltage variation should be within 5%. 6. Use oscilloscope to observe output ripple voltage and phase node ringing. For accurate measurement, please refer to Figure 3 for proper probe set-up. FIGURE 3. OSCILLOSCOPE PROBE SET-UP VOUT Setting The output voltage is set by the resistor divider, R4 and R1. 7. Optimization. Please refer to Table 2 on page 1 for optimization recommendation. R4 + R1 V OUT = -------------------- 0.6V R4 8. For 5V input applications, please tie the VCC5V to VIN and do not allow VIN to go above 5.5V. Resistor R11 is a resistor jumper for loop gain measurement. It is recommended to set R11 = 50 for loop gain measurement. NOTE: Test points: VIN+, VIN-, VO+ and VO- are for voltage measurement only. Do not allow high current through these test points. (EQ. 1) Component Selection Component Voltage Stress The controller, ISL8130, the input capacitors and the flying capacitors, C18 and C19, see the input voltage. MOSFET and forward diode see the voltage stress of VIN + VOUT. Duty Cycle Calculation The duty cycle of the sepic converter can be estimated using Equation 2. V OUT + V F D = ---------------------------------------V IN + V OUT + V F (EQ. 2) Where: VF is the forward voltage of the diode, D1. 2 AN1771.1 August 7, 2012 Application Note 1771 Given: The OC threshold should be higher than the peak input winding current at maximum load current. The maximum peak inductor usually occurs at VINmin and can be calculated by Equation 9. VIN = 8.4V, VOUT = 10V, VF = 0.5V We have nominal duty cycle of 44.4%. Maximum duty cycle and minimum duty cycle can be estimated by Equation 3 and Equation 4 respectively. V OUT + V F D max = -------------------------------------------------V INmin + V OUT + V F (EQ. 3) V OUT + V F D min = --------------------------------------------------V INmax + V OUT + V F (EQ. 4) A coupled inductor with 1:1 turns ratio is recommended for sepic converter. Such a coupled inductor is specified in two ratings; the parallel ratings and the series ratings. In this application note, inductor parameters refers to the parallel rating unless otherwise noted. It is recommended to select inductor so that the ripple current to DC current ratio is between 30% to 50%. For low-core-loss magnetic material, higher ripple ratio would ease the compensation design and help to reduce the size of the inductor. Please refer to Equation 5 for recommended inductor value: (EQ. 5) Where D is the duty cycle, iR is the inductor ripple ratio, Iomax is the maximum load current. With Iomax = 2A, FSW = 500kHz, iR= 40%. The recommended inductance is 5.18H. The DC magnetizing current of the coupled inductor can be estimated by: I Omax I INDmax = -----------------------1 – D max (EQ. 9) Refer to Equation 10 for RCS calculation. R SEN I OCSET min R CS ---------------------------------------------------I INPK (EQ. 10) Where: IOCSET is the OCSET pin sinking current for overcurrent detection. The IOCSET(min) = 80A. The maximum overcurrent threshold can be calculated by Equation 11. Coupled Inductor Selection V IN L P = ------------------------------------------------- D 1 – D i R I Omax F SW V OUT + V F 1 V OUT + V F 1 – D max I INPK = I Omax ------------------------- + --- ----------------------------------------------------------------V INmin L P F SW 4 R SEN I OCSET max I OCmax = ----------------------------------------------------R CS (EQ. 11) Where IOCSET(max) = 120A. When input winding current reaches the OC threshold, the inductor peak magnetizing current can be estimated by Equation 12. I OCmax 1 V OUT + V F 1 – Dmin 1 – 2 Dmin I OCMAG = ------------------- – --- ---------------------------------------------------------------- ---------------------------------4 L P F SW D min Dmin (EQ. 12) The RCS should be rated for the power loss at the maximum OC trip point. For most accurate current sensing setting, please use Kelvin connection for OCSET and ISEN pins. Please refer to Figure 4 for reference. (EQ. 6) The peak magnetizing current is: 1 V OUT + V F 1 – D max I INDPK = I INDmax + --- ----------------------------------------------------------------L F 2 P (EQ. 7) SW The inductor should be of saturation current higher than that calculated by Equation 7. DRC127-4R7 is selected with actual inductance of 4.7H. It is recommended to select inductor with saturation current higher than the maximum overcurrent threshold. Please refer to “Current Sensing” on page 3 for details. Current Sensing FIGURE 4. ISL8130 CURRENT SENSING LAYOUT EXAMPLE For accurate overcurrent detection, it is recommended to set the voltage across the current sensing resistor, RCS higher than 50mV. Taking variation into consideration, when precision current sensing resistor is used, RSEN = 665. The DC current of the output winding can be estimated by: V OUT + V F I INWIND = I Omax ------------------------V (EQ. 8) INmin 3 Output Capacitors It is recommended to use a combination of aluminum capacitors with high capacitance and low ESR ceramic capacitors at the output for optimum ripple and load transient performance. The low ESL and ESR ceramic capacitors should be placed close to the MOSFET and diode. The loop formed by the MOSFET, the flying capacitors, C18 and C19, the forward diode and the output ceramic capacitors should be minimized as short as possible. AN1771.1 August 7, 2012 Application Note 1771 When selecting the output capacitors, there are two important requirements: the ripple current and the stability. The output RMS current worst case occurs at VINmin and maximum load. See Equation 13 for output ripple current calculation: 1 I ORMS = I OUT -----------------------1 – D max (EQ. 13) Given: Flying Capacitors High ripple current rated ceramic capacitors are preferred for the flying capacitors. The flying capacitor ripple current is at maximum when VIN = VINmin and can be estimated by Equation 17: V OUT + V F I FLYRMS = I OUT ------------------------V INmin (EQ. 17) Given: VOUT = 10V, IOUT = 2A, VINmin = 5.6V VOUT = 10V, IOUT = 2A, VINmin = 5.6V Dmax = 65.7% We have: We have: IFLYRMS = 2.74A IORMS = 3.417A For applications with FSW < 1MHz, it is still rule of thumb that the aluminum electrolytic capacitors take the ripple current. Please select electrolytic capacitors with ripple current greater than the maximum IORMS, as calculated by Equation 13. The other important factor is stability. The right-half-plane zero, fRHP of a sepic converter imposes a big challenge for stability. It is recommended to set cross over frequency below the fRHP and above the boost converter natural resonant frequency, fN. It is recommended to use sufficient output capacitors so that the fN is much lower than fRHP. Equation 14 is provided for total output capacitance estimation. I Omax 2 C out ------------------ L P 400 V INmin Please select flying capacitor with ripple current higher than IFLYRMS. The flying capacitor would also resonate with the leakage inductor of the coupled inductor. It is recommended to use sufficient CFLY so that the resonating frequency be lower than half of the switching frequency. The leakage inductance can be measured in the setup shown in Figure 5. (EQ. 14) For right-half-plane zero calculation, fRHP: V in 1 – D f RHP = -----------------------------------2 I OUT L P (EQ. 15) For sepic converter natural resonant frequency, fN: 1–D f N = -----------------------------------------2 C OUT L P FIGURE 5. LEAKAGE INDUCTANCE MEASUREMENT SETUP (EQ. 16) Equation 18 gives the recommended CFLY: 2 1 1 C FLY -------------------- ----- F LS SW (EQ. 18) Given LS = 0.1H and FSW = 500kHz, the recommended CFLY should be greater than 4.4F. When ceramic capacitors are used, attention should be paid to the DC degrading characteristic. Please contact capacitor vendor for more details. 4 AN1771.1 August 7, 2012 Application Note 1771 Typical Performance Curves 92 90 86 VOUT REGULATION (V) VIN = 5.6V 88 EFFICIENCY (%) 10.4 VIN = 8.4V VIN = 16V 84 82 80 10.3 10.1 10 9.8 76 9.7 0 0.4 0.8 1.2 LOAD CURRENT(A) 1.6 2.0 9.6 VIN = 16V VIN = 8.4V 9.9 78 74 VIN = 5.6V 10.2 0 0.4 0.8 1.2 1.6 2.0 LOAD CURRENT(A) FIGURE 6. EFFICIENCY vs LOAD CURRENT FIGURE 7. VOUT LOAD REGULATION VO(AC) AT 100mV/DIV TIME AT 2µs/DIV FIGURE 8. OUTPUT RIPPLE (V IN = 5.6V, LOAD = 2A, 20MHz BW) VO(AC) AT 100mV/DIV TIME AT 2µs/DIV FIGURE 9. OUTPUT RIPPLE (V IN = 8.4V, LOAD = 2.A, 20MHz BW) VIN AT 5V/DIV VO AT 5V/DIV VO(AC) AT 500mV/DIV VEN/SS AT 2V/DIV PHASE AT 10V/DIV TIME AT 20ms/DIV FIGURE 10. SOFT-START (V IN = 5.6V, C SS - 0.47µF) 5 ISTEP AT 1A/DIV TIME AT 1msec/DIV FIGURE 11. LOAD TRANSIENT (VIN = 5.6V, LOADSTEP FROM 0.5A to 1.5A) AN1771.1 August 7, 2012 Application Note 1771 Typical Performance Curves (Continued) VIN AT 10V/DIV VIN AT 10V/DIV VO AT 5V/DIV VO AT 5V/DIV VEN/SS AT 2V/DIV VEN/SS AT 2V/DIV PHASE AT 20V/DIV PHASE AT 20V/DIV TIME AT 50ms/DIV FIGURE 12. OVERCURRENT PROTECTION (V IN = 16V, I LOAD = 6.6A) 6 TIME AT 50ms/DIV FIGURE 13. OVERCURRENT PROTECTION (V IN = 5.6V, ILOAD = 3.1A) AN1771.1 August 7, 2012 ISL8130EVAL3Z Schematic VIN+ VIN: 5.6V to 16V 1 VCC5 C6 1 VIN 20 1 1 CDEL 1 2 1 2 1 C11 0.1uF 10uF C17 1 1 2 1 2 25V 1 2 1 Q1 VOUT C15 DNP C20 1.0uF C23 DNP BSC059N04L PGND R22 20k C26 DNP VO1 C24 DNP 2 R17 3.3 GND 1 VCC5 1 C10 0.47uF 2 C25 DNP C27 DNP 1 1 R1 100K R3 2.2K 2 2 2 2 1 2 1 16SEPC180MX C14 10uF C31 180uF 2 C13 0.1uF 1 JP3 1 1 2 4 2 U1 C22 DNP C30 DNP 5 4 PVCC 1 1 2 SSC54 (or SL42) 3 VOUT VOUT 2 PGND PGOOD 1 5 LGATE ENSS D1 1 R2 7.5K COMP PGOOD 2 ENSS C1 10nF PVCC 2 CATHODE ANODE 2 19 PHASE FB 2 1 50V 1 C2 150pF COMP 18 RT 0.1u 2 2 1 17 1 6 UGATE UGATE VO+ 1 VOUT =10V/2A 1 DNP R9 2 2 VCC5 1 FB BOOT SGND PGOOD 1 GND 1 2 3 R5 28.7k VIN R14 3.3 SGND VIN1 GND 2 CS 7 C7 DNP 25V C18 2 RT 16 8 ISEN PGOOD 1 PGOOD GND 2 10uF VCC5 5.6V to 16V C29 100uF Application Note 1771 1 REFIN VCC5 C9 DNP 3 1 15 2 9 1 VIN1 14 NC PH11 10 OCSET 2 13 VCC5 1 REFOUT 2 C16 1uF 2 * C19 1 12 1 4 isl8130 2 DRQ125-4R7-R * CDEL R18 T1 2 REFOUT 7 C4 4.7uF 1 C8 10uF CS 2 1 1 11 3.3 VIN 1 RCS 5m 619 C12 2.2uF 2 2 1 R8 1 2 R7 100K 2 DNP 2 2 VIN 2 N16246185 R11 1 0 2 C3 2 2 1 2 1000pF 1 R4 6.34K Disclaimer: THIS EVALUATION BOARD AND MATERIALS ARE PROVIDED ‘AS-IS’ FOR EVALUATION PURPOSES ONLY. INTERSIL CORPORATION AND ITS SUBSIDIARIES (‘INTERSIL’) DISCLAIM ALL WARRANTIES, INCLUDING WITHOUT LIMITATION FITNESS FOR A PARTICULAR PURPOSE AND MERCHANTABILITY. Intersil provides the evaluation platform and design proposals to help our customers to develop products. However, factors beyond Intersil’s control, including without limitation component variations, temperature changes and PCB layout, could significantly affect Intersil product performance. It remains the customers' responsibility to verify the actual circuit performance. Intersil Corporation 1001 Murphy Ranch Road Milpitas, CA 95035 Size B Date: Title Rev A ISL8130EVAL3Z SEPIC Monday , July 02, 2012 Sheet 1 of 1 AN1771.1 August 7, 2012 Application Note 1771 Bill of Materials ITEM QTY REFERENCE VALUE DESCRIPTION PART # VENDOR 1 1 C1 10nF Ceramic CAP, NP0 or C0G, 50V, sm0603 Generic Generic 2 1 C2 150pF Ceramic CAP, NP0 or C0G, 50V, sm0603 Generic Generic 3 1 C3 1000pF Ceramic CAP, NP0 or C0G, 50V, sm0603 Generic Generic 4 1 C4 4.7µF Ceramic CAP, X5R, 10V, sm0603 Generic Generic 5 4 C14, C19, C22, C8 10µF Ceramic CAP, X5R, 25V, sm1206 Generic Generic 6 1 C10 0.47µF Ceramic CAP, X5R, 16V, sm0603 Generic Generic 7 2 C11, C13 0.1µF Ceramic CAP, X5R, 16V, sm0603 Generic Generic 8 1 C12 2.2µF Ceramic CAP, X5R, 16V, sm0603 Generic Generic 9 2 C16, C20 1µF Ceramic CAP, X5R, 16V, sm0603 Generic Generic 10 1 C17 10µF Ceramic CAP, X5R, 10V, sm0805 Generic Generic 11 1 C18 0.1µF Ceramic CAP, X5R, 50V, sm0805 Generic Generic 12 1 C29 100µF Alum Cap, 35V, Ripple Current > 300mA EEU-FC1V101 Panasonics 13 1 C31 150µF ALUM CAP, 25V PLV1E151MDL1TD Nichicon 14 1 D1 Schottky Diode, 40V, DO-214AB SSC54 Vishay 15 1 Q1 Single Channel NFET, 40V BSC059N04L Infineon 16 1 RCS 10m Precision RES, SM2010 PMR50HZPFU10L0 ROHM 17 1 R1 100k Resistor, sm0603, 1% Generic Generic 18 1 R2 7.5k Resistor, sm0603, 1% Generic Generic 19 1 R3 2.2k Resistor, sm0603, 10% Generic Generic 20 1 R4 6.34k Resistor, sm0603, 1% Generic Generic 21 1 R5 28.7k Resistor, sm0603, 1% Generic Generic 22 1 R7 100k Resistor, sm0603, 10% Generic Generic 23 1 R8 665 Resistor, sm0603, 1% Generic Generic 24 1 R11 0 Resistor, sm0603, 10% Generic Generic 25 3 R14, R17, R18 3.3 Resistor, sm0603, 10% Generic Generic 26 1 R22 20k Resistor, sm0603, 1% Generic Generic 27 1 T1 4.7µH 1:1 Coupled Inductor DRQ125-4R7-R Cooper 28 1 U1 PWM Controller, 20L QSOP ISL8130IAZ Intersil EVALUTION BOARD HARDWARE 29 1 JP3 30 2 VOUT, VIN 31 2 PGND, GND 32 6 VIN+, VO+, VO-, VIN-, SGND, PGOOD jumper_2pin Generic Generic Banana Jack (Red) 111-0703-002 Emerson Banana Jack (Black) 111-0703-001 Emerson Test Point 1514-2 Keystone OPTIONAL COMPONENTS 33 8 C6, C7, C9, C15, C23, C24, C25, C26, C27, C30 8 DNP AN1771.1 August 7, 2012 Application Note 1771 ISL8130EVAL3Z PCB Layout FIGURE 14. TOP SILKSCREEN FIGURE 15. TOP LAYER FIGURE 16. BOTTOM SILKSCREEN FIGURE 17. BOTTOM LAYER Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 9 AN1771.1 August 7, 2012