EL4340EVAL1 Evaluation Board User’s Guide ® Application Note March 28, 2005 AN1182.0 Introduction High Frequency Layout Considerations The EL4340EVAL1 evaluation board contains all the circuitry needed to characterize critical performance parameters of the EL4340 triple 2:1 MUX-amplifier, over a variety of applications. At frequencies of 500MHz and higher, circuit board layout may limit performance. The following layout guidelines are implemented on the evaluation board; The EL4340 contains 3 separate 2 input multiplexers, each followed by a unity gain buffer controlled by a common set of logic inputs (Figure 1, Table 1). Control features include a high speed (20ns) HIZ output control for individual selection of MUX amps that share a common video output line. A control logic latch (LE) enables multiple devices to share a common input control logic bus. The ENABLE control can be used to save power by powering the device down. The evaluation board circuit and layout is optimized for either 50Ω or 75Ω terminations, and implements a basic R-G-B video 2 input MUX-amp. The board is supplied with 75Ω input signal terminations and a 75Ω back-termination resistor on each of the 3 outputs, making it suitable for driving video cable. The user has the option of replacing the 75Ω resistors with 50Ω resistors for other applications. The control lines contain 50Ω resistors to match the 50Ω output impedance of high speed pulse generators. Control line termination resistors are recommended for rise and fall times under 10ns to minimize unwanted transients. If DC is used for the control logic, the resistors may be removed; or the applied DC voltage can reduced to 2.5V to reduce the dissipation in the termination resistor. The layout contains component options to include an output series resistor (RS) followed by a parallel resistor (RL) capacitor (CL) network to ground. This option allows the user to select several different output configurations. Examples are shown in Figures 2A, 2B, and 2C. The evaluation board is supplied with the 75Ω back termination resistors shown in Figure 2C. Amplifier Performance and Output Configurations • No series connected vias are used in signal I/O lines, as they can add unwanted inductance, • Signal trace lengths are minimized to reduce transmission line effects and the need for strip-line tuning of the signal traces. • High frequency decoupling caps are places as close to the device power supply pin as possible - without series vias between the capacitor and the device pin. Power Sequencing Proper power supply sequencing is -V first, then +V. In addition, the +V and -V supply pin voltage rate-of-rise must be limited to ±1V/µs or less. The evaluation board contains parallel-connected low VON Shottky diodes on each supply terminal to minimize the risk of latch up due to incorrect sequencing. In addition, extra 10µF decoupling capacitors are added to each supply to aid in reducing the applied voltage rate-of-rise. Reference Documents 1. EL4340 Data Sheet, FN7421.0 S0 EN0 DL Q C DECODE EN1 DL Q C IN0(A,B,C) IN1(A,B,C) OUT AMPLIFIER BIAS LE The EL4340 output amplifiers are designed for maximum gain-bandwidth performance when loaded with ~500Ω (RL) in parallel with ~5pF (CL) to ground, directly at the output pin (Figure 2A). They are ideally suited for driving high impedance high speed selectable-gain buffers when gain compensation is needed. In these applications, output trace capacitance to 5pF actually optimizes AC performance. For trace capacitance below 5pF, an additional capacitor between the output pin to ground may be added to achieve the 5pF optimum. GBW decreases slightly at the lower output load impedances typical of back-terminated cable driving applications. 1 • Signal I/O lines are the same lengths and widths to match propagation delay and trace parasitics, HIZ ENABLE A logic high on LE will latch the last S0 state. This logic state is preserved when cycling HIZ or ENABLE functions. FIGURE 1. EL4340 FUNCTIONAL BLOCK DIAGRAM (1 OF 3 CHANNELS) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Application Note 1182 TABLE 1. LOGIC TABLE EL4340 VIN 50Ω OR 75Ω S0 HIZ ENABLE LENABLE OUTA,B,C 0 0 0 0 IN0A,B,C 1 0 0 0 IN1A,B,C - 1 0 - Hi Z - - 1 - Power down - 0 0 1 Last S0 selection TEST EQUIPMENT EL4340 RS, 0Ω RS VIN *Cb2 ~3pF *Cb1 ~0.5pF 50Ω OR 75Ω CL 1.5pF RL 500Ω * Cb1, Cb2 are approximate PCB trace capacitances. 475Ω RL 50Ω OR 75Ω 50Ω OR 75Ω * Cb1 is approximate PCB trace capacitance. FIGURE 2A. TEST CIRCUIT WITH OPTIMAL OUTPUT LOAD FIGURE 2B. TEST CIRCUIT FOR 50Ω OR 75Ω TERMINATIONS EL4340 RS VIN 50Ω OR 75Ω ^Cb1 ~0.5pF Cb1 ~0.5pF 50Ω OR 75Ω TEST EQUIPMENT 50Ω OR 75Ω * Cb1 is approximate PCB trace capacitance. FIGURE 2C. BACK-TERMINATED TEST CIRCUIT FOR CABLE APPLICATION EL4340EVAL1 Top View 2 AN1182.0 March 28, 2005 Application Note 1182 EL4340EVAL1 Schematic Diagram U1 1 IN0A NIC 24 JLEBAR R9 75Ω 2 GND A 23 3 IN0B R8 75Ω 22 4 NIC 21 5 GND B 20 LEBAR JENABLE R1 - 50Ω ENABLE JHIZ R14 - 50Ω HIZ R12 - 50Ω OUTA R15 - 75Ω 6 IN0C R7 75Ω V+ 19 7 NIC OUTB 18 R16 - 75Ω 8 IN1A OUTC 17 R2 75Ω 9 NIC V- 16 10 IN1B R10 75Ω R22 R21 R20 C11 NIC 15 11 GND C 14 12 IN1C C10 C9 R17 - 75Ω SO D1 R19 50Ω NIC 13 R11 75Ω C7 C2 C1 C3 10µF 0.1µF 10nF 1nF + C6 10µF D2 GND. V- C5 0.1µF JSO C4 10nF C8 1nF V+ EL4340EVAL1 Components Parts List DEVICE # DESCRIPTION COMMENTS C7, C8 CAP, SMD, 0603, 1000pF, 25V, 10%, X7R Power Supply Decoupling C1, C4 CAP, SMD, 0603, 0.01µF, 25V, 10%, X7R Power Supply Decoupling C2, C5 CAP, SMD, 0603, 0.1µF, 25V, 10%, X7R Power Supply Decoupling C3, C6 CAP, SMD, 0805, 10µF, 6.3V, 10%, X5R Power Supply Decoupling D1, D2 Diode-Shottky, 2 Pin, 45V, 7.5A MBR0550T (Motorola) Reverse Polarity Protection Resistor, SMD, 0603, 75Ω, 1/10W, 1%, Signal Input/output Termination Resistor, SMD, 0603, 49.9Ω, 1/16W, 1%, Logic Input Termination C9, C10, C11 Resistor, SMD, 0603 Optional, not populated R20, R21, R22 Resistor, SMD, 0603 Optional, not populated R2, R7-R11, R15-R17 R1, R12, R14, R19 U1 EL4340IU -500MHz Multiplexing Amplifier, 24P, QSOP Device Under Test Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 3 AN1182.0 March 28, 2005