MachXO2 sysIO Usage Guide April 2015 Technical Note TN1202 Introduction The MachXO2™ PLD family sysIO™ buffers are designed to meet the needs of flexible I/O standards in today’s fast-paced design world. The supported I/O standards range from single-ended I/O standards to differential I/O standards so that users can easily interface their designs to standard buses, memory devices, video applications and emerging standards. This technical note provides a description of the supported I/O standards and the banking scheme for the MachXO2 PLD family. The sysIO architecture and the software usage are also discussed to provide a better understanding of the I/O functionality and placement rules. sysIO Buffer Overview The basic building block of the MachXO2 sysIO is the Programmable I/O Cell (PIC) block. There are four types of PIC blocks in the MachXO2 device architecture. These include the basic PIC block, the memory PIC block for DDR memory support, the receiving PIC block with gearing, and the transmitting PIC block with gearing. The PIC blocks with gearing are used for video and high-speed applications. The PIC blocks with gearing have a built-in control module for word alignment. The memory PIC block has additional logic to manage DQS strobe signals and clock phase shift. The details of the memory PIC block and the gearing PIC block can be found in TN1203, MachXO2 High-Speed Source Synchronous and Memory Interfaces. A common feature of all four types of PIC blocks is that each PIC block consists of four programmable I/Os (PIOs). Each PIO includes a sysIO buffer and an I/O logic block. A simplified sysIO block diagram is shown in Figure 1. The I/O logic block consists of an input block, an output block, and a tri-state block. These blocks have registers, input delay cells, and the necessary control logic to support various operational modes. The sysIO buffer determines the compliance to the supported I/O standards. It also supports features like hysteresis to meet common design needs. The I/O logic block and the sysIO buffer are designed with a minimal use of die area; providing easy bus interfacing, and pin out efficiency. Two adjacent PIOs can form a pair of complementary output drivers. In addition, PIOA and PIOB of the PIC block form the primary pair of the buffer, while PIOC and PIOD form the alternate pair of the buffer. The primary pairs have additional capability that is not available on the alternate pair. The sysIO buffers of the PIC block are equivalent when implemented as the single-ended I/O standards. Figure 1. PIC Block Diagram Primary PIO Pair Alternate PIO Pair PAD A (T) PAD B (C) PAD C (T) PAD D (C) sysIO Buffer A sysIO Buffer B sysIO Buffer C sysIO Buffer D IOLogic A IOLogic B IOLogic C IOLogic D © 2015 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 tn1202_2.0 MachXO2 sysIO Usage Guide Supported sysIO Standards The Lattice MachXO2 sysIO buffer supports both single-ended and differential standards. The single-ended standard can be further divided into internally ratioed standards such as LVCMOS, and externally referenced standards such as SSTL. The internally ratioed standards support individually configurable drive strength and bus maintenance circuits (weak pull-up, weak pull-down, or bus keeper). There are two types of ratioed input buffers. One is connected to VCCIO and the other is connected to VCC (1.2 V). Each sysIO buffer supports both buffers in parallel, and therefore provides an option to program any input buffer to be a 1.2 V ratioed input buffer regardless of the VCCIO voltage. All banks of the MachXO2 devices support true differential inputs, and emulated differential outputs using external resistors and the complementary LVCMOS outputs. The true-LVDS differential outputs and LVDS input termination are supported in specific banks as described in the sysIO Banking Scheme section of this document. Table 1. Supported Input Standards VREF (Nominal) VCCIO1 (Nominal) LVTTL33 — — LVCMOS33 — — LVCMOS25 — — LVCMOS18 — — LVCMOS15 — — LVCMOS12 — — 1.25 — Input Standard Single-Ended Interfaces SSTL25 Class I, II SSTL18 Class I, II 0.9 — HSTL18 Class I, II 0.9 — - 3.3 LVDS25 — — LVPECL33 — — MLVDS25 — — BLVDS25 — — RSDS25 — — SSTL25 Differential — — SSTL18D Differential — — HSTL18D Differential — — PCI33 Differential Interfaces LVTTL / LVCMOS Differential — — MIPI2 — — 1. If not specified, refer to mixed voltage support in the VCCIO Requirement section. 2. This interface can be emulated with external resistors. 2 MachXO2 sysIO Usage Guide Table 2. Supported Output Standards Output Standards Drive (mA) VCCIO (Nominal) LVTTL33 4, 8, 12, 16, 24 3.3 LVCMOS33 4, 8, 12, 16, 24 3.3 LVCMOS25 4, 8, 12, 16 2.5 LVCMOS18 4, 8, 12 1.8 LVCMOS15 4, 8 1.5 LVCMOS12 Single-Ended Interfaces 2, 6 1.2 SSTL25 Class I 8 2.5 SSTL18 Class I 8 1.8 HSTL18 Class I 8 1.8 PCI33 24 3.3 Differential Interfaces LVDS25 3.5, 2.5, 2.0, 1.25 2.5, 3,3 LVPECL33 16 3.3 MLVDS25 16 2.5 BLVDS25 16 2.5 RSDS25 8 2.5 SSTL25 Differential 8 2.5 SSTL18D Differential 8 1.8 HSTL18D Differential 8 1.8 LVTTL33 Differential 4, 8, 12, 16, 24 3.3 LVCMOS33 Differential 4, 8, 12, 16, 24 3.3 LVCMOS25 Differential 4, 8, 12, 16 2.5 LVCMOS18 Differential 4, 8, 12 1.8 LVCMOS15 Differential 4, 8 1.5 LVCMOS12 Differential 2, 6 1.2 2 2.5 1 MIPI 1. This interface can be emulated with external resistors. sysIO Banking Scheme The MachXO2 family has a non-homogeneous I/O banking structure. MachXO2-256, MachXO2-640/U and MachXO2-1200 have four I/O banks each with one I/O bank per side. MachXO2-1200U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 devices have six I/O banks each, with one I/O bank on each of the top, bottom and right sides, and three banks on the left side. The MachXO-640U, MachXO-1200/U and higher density devices support true LVDS differential outputs through the primary pairs on the top bank (bank 0). These devices also support 100 ohm differential input termination on every I/O pair on the bottom I/O bank. There is also a programmable PCI clamp available on the bottom I/O bank for these devices. For the “R1” version of the MachXO2 devices, the 100 ohm differential input termination is approximately 200 ohms. The “R1” versions of the MachXO2 devices have an “R1” suffix at the end of the part number (e.g., LCMXO2-1200ZE-1TG144CR1). For more details on the R1 to Standard migration refer to AN8086, Designing for Migration from MachXO2-1200-R1 to Standard (Non-R1) Devices. MachXO2-256 and MachXO2-640 do not support true LVDS differential outputs, differential input termination, and PCI clamps in any banks (MachXO2-640U I/O architecture is similar to the larger devices and supports the aforementioned features). Each of the I/O pins on all MachXO2 PLDs has a clamp feature which can be disabled or 3 MachXO2 sysIO Usage Guide enabled. This clamp is similar to the PCI clamp but it is not PCI compliant except in the bottom bank of the MachXO2-640U, MachXO2-1200/U and higher density devices. The arrangements of the I/O banks are shown in Figures 2, 3, and 4. DDR memory support in bank 1 is not available for devices in wafer level chip scale packages (WLCSP). Figure 2. MachXO2-256 and MachXO2-640 I/O Banking Arrangement Base I/O Buffer Base I/O Buffer Bank 1 Bank 3 Base I/O Buffer Bank 0 Array sizes: 256, 640 Bank 2 Base I/O Buffer Figure 3. MachXO2-640U and MachXO2-1200 I/O Banking Arrangement Base I/O Buffer Plus: 1 pair of LVDS differential outputs for every four PIO (3.5 mA, 2.5 mA, 2.0 mA, 1.25 mA) Bank 2 Base I/O Buffer Plus: 100 ohm differential input termination on every pair plus PCI clamp 4 DDR memory support (not available on WLCSP packages) Base I/O Buffer Array size: 640U, 1200 Bank 1 Bank 3 Base I/O Buffer Bank 0 MachXO2 sysIO Usage Guide Figure 4. MachXO2-1200U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 I/O Banking Arrangement Base I/O Buffer Plus: 1 pair of LVDS differential outputs for every four PIO (3.5 mA, 2.5 mA, 2.0 mA, 1.25 mA) Base I/O Buffer DDR memory support (not available on WLCSP packages) Bank 1 Bank 4 Array sizes: 1200U, 2000/U, 4000, 7000 Bank 3 Base I/O Buffer Bank 5 Bank 0 Bank 2 Base I/O Buffer Plus: 100 ohm differential input termination on every pair plus PCI clamp sysIO Standards Supported by I/O Banks All banks can support multiple I/O standards under the VCCIO rules discussed above. Tables 3 and 4 summarize the I/O standards supported on various sides of the MachXO2 device. Table 3. Single-Ended I/O Standards Supported on Various Sides Standard Top Bottom 1 Left Right PCI33 — Yes — — LVTTL33 Yes Yes Yes Yes LVCMOS33 Yes Yes Yes Yes LVCMOS25 Yes Yes Yes Yes LVCMOS18 Yes Yes Yes Yes LVCMOS15 Yes Yes Yes Yes LVCMOS12 Yes Yes Yes Yes SSTL252 Yes Yes Yes Yes SSTL182 Yes Yes Yes Yes HSTL182 Yes Yes Yes Yes 1. PCI33 is supported at the bottom bank of MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 devices. 2. SSTL Class II and HSTL Class II are supported as input only. 5 MachXO2 sysIO Usage Guide Table 4. Differential I/O Standards Supported on Various Sides Standard Top Bottom 1 Left Right LVDS output Yes — — — LVPECL33E2 Yes Yes Yes Yes MLVDS25E2 Yes Yes Yes Yes BLVDS25E2 Yes Yes Yes Yes RSDS25E Yes Yes Yes Yes LVDS25E2 Yes Yes Yes Yes SSTL25D output Yes Yes Yes Yes SSTL18D output Yes Yes Yes Yes HSTL18D output Yes Yes Yes Yes LVTTL33D output Yes Yes Yes Yes LVCMOS33D output Yes Yes Yes Yes LVCMOS25D output Yes Yes Yes Yes LVCMOS18D output Yes Yes Yes Yes LVCMOS15D output Yes Yes Yes Yes LVCMOS12D output Yes Yes Yes Yes LVDS input Yes Yes Yes Yes 2 LVPECL33 input Yes Yes Yes Yes MLVDS25 input Yes Yes Yes Yes BLVDS25 input Yes Yes Yes Yes RSDS25 input Yes Yes Yes Yes SSTL25D input Yes Yes Yes Yes SSTL18D input Yes Yes Yes Yes HSTL18D input Yes Yes Yes Yes LVTTL33D input Yes Yes Yes Yes LVCMOS33D input Yes Yes Yes Yes LVCMOS25D input Yes Yes Yes Yes LVCMOS18D input Yes Yes Yes Yes LVCMOS15D input Yes Yes Yes Yes LVCMOS12D input Yes Yes Yes Yes MIPI Yes Yes Yes Yes 1. True LVDS output is supported at the top bank of MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO24000, and MachXO2-7000 devices. 2. Emulated output standards are denoted with a trailing “E” in the name of the standard. Power Supply Requirements The MachXO2 device family has a simplified power supply scheme for sysIO buffers. The core power VCC and the bank power VCCIO are the two main power supplies. A MachXO2 device can be powered and operated with a single power supply by connecting VCC and VCCIO to nominal voltages of 1.2 V. The JTAG programming pins are powered by VCCIO in bank 0 where the JTAG pins reside. All the user sysIOs have a weak pull-down after power-up is complete and before the device configuration is done. 6 MachXO2 sysIO Usage Guide VCCIO Requirement for I/O Standards Each I/O bank of a MachXO2 device has a separate VCCIO supply pin that can be connected to 1.2 V, 1.5 V, 1.8 V, 2.5 V or 3.3 V. This voltage is used to power the output I/O standard and source the drive strength for the output. In addition to this, VCCIO also powers the ratioed input buffers such as LVTTL, LVCMOS and PCI. This ensures that the threshold of the input buffers tracking the VCCIO voltage level. For LVCMOS I/O types, mixed input voltage support is allowed in each I/O bank as long as the VCCIO requirement for the input or output I/O standard is the same, or when all inputs in the bank are within the over-drive or underdrive range as specified in Tables 5 and 6. Two other options exist to further increase the input receiver flexibility. One is to configure an I/O to be a 1.2 V ratioed input buffer, regardless of the bank VCCIO voltage. This is possible because the MachXO2 sysIO buffer has two ratioed input buffers connected to VCCIO and VCC in parallel. The other option is to use the input reference voltage pin to set the input threshold for LVCMOS standards that are not covered by the VCCIO of the bank. Table 5. VCCIO for Same Bank LVCMOS/LVTTL Input/Output Requirements1 I/O Type Bank Restrictions LVCMOS12 Outputs require VCCIO = 1.2 V Inputs available in all VCCIO levels LVCMOS15 Outputs require VCCIO = 1.5 V Inputs available in all VCCIO levels. LVCMOS15R33 2, 3 2, 3 Inputs only, require VCCIO = 3.3 V and VREF = 0.75 V LVCMOS15R25 Inputs only, require VCCIO = 2.5 V and VREF = 0.75 V LVCMOS18 Outputs require VCCIO= 1.8 V Inputs require VCCIO = 1.5 V, 1.8 V, 2.5 V, or 3.3 V LVCMOS18R33 2, 3 2, 3 Inputs only, require VCCIO = 3.3 V and VREF = 0.9 V LVCMOS18R25 Inputs only, require VCCIO = 2.5 V and VREF = 0.9 V LVCMOS25 Outputs require VCCIO = 2.5 V Inputs require VCCIO = 1.5 V, 1.8 V, 2.5 V, or 3.3 V. LVCMOS25R332, 3 Inputs only, require VCCIO = 3.3 V and VREF = 1.25 V LVCMOS33 Outputs require VCCIO = 3.3 V Inputs require VCCIO = 1.5 V, 1.8 V, 2.5 V, or 3.3 V LVTTL33 Outputs require VCCIO = 3.3 V Inputs require VCCIO = 1.5 V, 1.8 V, 2.5 V, or 3.3 V PCI33 Inputs and outputs both require VCCIO= 3.3 V 1. Certain I/O type and bank VCCIO combinations may cause higher DC current. For more details refer to Table 6. Use Power Calculator to get power estimation for I/O types. 2. The HYSTERESIS option and BUS KEEPER option are not available for these I/O types. 3. Since only one VREF signal can be supported in each I/O bank, only one of these I/O standards can be used in each I/O bank. 7 MachXO2 sysIO Usage Guide Table 6. Mixed Voltage Support for LVCMOS and LVTTL I/O Types Inputs VCCIO 1.2 V 1.5 V 1.2 V YES 6 YES 1.5 V YES1 YES 1.8 V 1 5 2.5 V 3.3 V YES 1 YES 1 YES YES 2, 5, 7 YES 2, 5, 7 YES 1.8 V Outputs 2.5 V 3.3 V 1.2 V 1.5 V 1.8 V 2.5 V 3.3 V YES YES6 YES6 YES6 YES 6 6 YES 3, 5, 7 YES 3, 5, 7 YES YES 4, 5, 7 YES YES YES YES 6 YES YES YES YES 1. Leakage will occur if bus hold or weak pull-up is turned on. 2. This input standard can be supported using the ratioed input buffer in under-drive conditions or using the I/O types LVCMOS15R25 or LVCMOS15R33 with the referenced input buffer. 3. This input standard can be supported using the ratioed input buffer in under-drive conditions or using the I/O type LVCMOS18R25 or LVCMOS18R33 with the referenced input buffer. 4. This input standard can be supported using the ratioed input buffer in under-drive conditions or using the I/O type LVCMOS25R33 with the referenced input buffer. 5. Under-drive condition when using the ratioed input buffer and the input standard voltage is below Vccio a.Under-drive causes higher DC current when the IO is at logic high. It is recommended to use Power Calculator to estimate the power consumption under such condition. b.Hysteresis is not supported. In the Diamond software, HYSTERESIS must be set to NA. c.CLAMP is not supported. In the Diamond software, CLAMP must be set to OFF. d.IO termination is not supported. In the Diamond software, PULLMODE must be set to NONE. 6. Over-drive condition when using the ratioed input buffer and the input standard voltage is above Vccio a.Hysteresis is not supported. In the Diamond software, HYSTERESIS must be set to NA. b.CLAMP is not supported. In the Diamond software, CLAMP must be set to OFF. c.IO termination is not supported. In the Diamond software, PULLMODE must be set to NONE. 7. Ratioed input buffer in under-drive conditions is preferred over referenced input buffer due to lower power requirement for the ratioed input buffer. 8. When using the ratioed input buffers in under-drive or over-drive conditions, the HYSTERESIS setting shall be NA, the CLAMP setting shall be OFF, and the UP and KEEPER PULLMODE settings are not supported. For differential input standards, certain mixed voltage support is allowed in the architecture as shown in Table 7. Table 7. Mixed Voltage Support for Differential Input Standards Differential Inputs VCCIO LVDS, LVPECL33, MLVDS25, BLVDS25, RSDS25 SSTL25D SSTD18D, HSTL18D LVTTL33D, LVCMOS33D LVCMOS25D, LVCMOS15D, LVCMOS12D LVCMOS18D 1.2 V 1.5 V 1.8 V YES 2.5 V YES YES YES 3.3 V YES YES YES YES YES YES YES YES YES Input Reference Voltage Each I/O bank supports one reference voltage (VREF). Any I/O in the bank can be configured as the input reference voltage pin. This pin is a regular I/O if it is not used as reference voltage input. To support SSTL and HSTL inputs, the reference voltage is set to half of the VCCIO level. The input reference voltage can also be generated internally from the VREF generator. Again, there is one VREF generator per bank and its programmable settings include OFF, 45% of VCCIO, 50% of VCCIO, and 55% of VCCIO. Programming of the internal VREF generator and the external VREF pin cannot be set at the same time for a particular bank because there is only one VREF bus per bank. 8 MachXO2 sysIO Usage Guide sysIO Buffer Configuration MachXO2 devices have three types of general-purpose sysIO buffer pairs to support a variety of single-ended and differential standards. Each sysIO buffer pair is made of two PIO buffers. PIO A and B pads form the primary pair, and PIO C and D pads form the alternate pair. Pads A and C of the pair are considered the “true” pad, while pads B and D are considered the “comp” pad. The “true” pad is associated with the positive side of the differential signal, while the “comp” pad is associated with the negative side of the differential signal. All the PIOs support programmable clamp and bus maintenance circuitry to allow a weak pull-up, or a weak pulldown, or a weak bus keeper. The base sysIO buffer pair is used on all sides of the smaller devices, and on the left and right sides of MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 devices. The LVDS sysIO buffer pairs have additional LVDS output drivers in the primary PIO pairs. They are used on the top bank of the MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000, and MachXO27000 devices. The bottom sysIO buffer pairs have additional 100ohm termination resistors between the “true” and “comp” pads. The bottom sysIO buffer pairs also support PCI clamp. They are supported on the bottom I/O bank of the MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 devices. LVCMOS Buffer Configurations The LVCMOS buffers are built on the base sysIO buffer pairs. These LVCMOS buffers can be configured in a variety of modes to support common circuit design needs. Bus Maintenance circuit Each pad has a weak pull-up, weak pull-down, and weak bus-keeper capability. These are selected with ON and OFF programmability. The pull-up and pull-down settings offer a fixed characteristic, which is useful in creating wired logic such as wired ORs. The bus-keeper option latches the signal in the last driven state, holding it at a valid level with minimal power dissipation. Input leakage can be minimized by turning off the bus maintenance circuitry. However, it is important to ensure that inputs are driven to a known state to avoid unnecessary power dissipation in the input buffer. The bus maintenance circuit is available for single-ended ratioed I/O standards. Programmable Drive Strength All single-ended drivers have programmable drive strength. This option can be set for each I/O independently. The drive strengths available for each I/O standard can be found in Table9. The MachXO2 programmable drive architecture is guaranteed with minimum drive strength for each drive setting. The V/I curves in the data sheet provide details of output driving capability versus the output load. This information, together with the current per bank and the package thermal limit current, should be taken into consideration when selecting the drive strength. Input Hysteresis VIH is the trip point for a low-to-high transition and VIL is the trip point for a high-to-low transition, hysteresis voltage is the difference between VIH and VIL. Hysteresis is used to prevent several quick successive changes if the input signal contains some noise, for example. The noise could mean that you cross the trip point more than just once, which causes a glitch in the system. All ratioed input receivers, except LVCMOS12, support input hysteresis. The input hysteresis for the LVCMOS33, LVCMOS25, LVCMOS18 and LVCMOS15 have two settings for flexibility. The ratioed input receivers have no input hysteresis when they are operated in under-drive or over-drive input conditions as shown in Tables 5 and 6. Programmable Slew Rate The single-ended output buffer for each device I/O pin has programmable output slew rate control that can be configured for either low noise (SLEWRATE=SLOW) or high speed (SLEWRATE=FAST) performance. Each I/O pin has an individual slew rate control. This slew rate control affects both the rising edge and the falling edges. The rise and fall ramp rates for each I/O standard can be found in the in the device IBIS file for a given I/O configuration. Tri-state and Open Drain Control Each single-ended output driver has a separate tri-state control in addition to the global tri-state control for the device. The single-ended output drivers also support open drain operation on each I/O independently. The open drain output is typically pulled up externally and only the sink current specification is maintained. 9 MachXO2 sysIO Usage Guide PCI Support with PCI Clamp The bottom sysIO buffer pair supports an optional PCI clamp diode that may be programmed individually. This is only supported at the bottom edge of MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO24000, and MachXO2-7000 devices. The PCI clamp supports a larger clamping current than the programmable clamp available on all other sides of the devices. Complementary Outputs Each sysIO buffer pair has built-in complementary circuit that can optionally be driven by the complement of the data that drives the single-ended driver associated with the true pad. This allows a pair of single-ended drivers to be used to drive complementary outputs with the lowest possible skew between the signals. Differential Buffer Configurations The base sysIO buffer pair supports differential input standards. Its complementary outputs support SSTL and HSTL differential output standards. The top and bottom edges of MachXO2-640U, MachXO2-1200/U and higher density devices support some additional functions over those supported by the base sysIO buffer pairs. Differential Receivers All the sysIO buffer pairs support differential input on all edges of the device. When a sysIO buffer pair is configured as differential receiver, the input hysteresis and the bus maintenance capabilities will be disabled for the buffer. On-Chip Input Termination The MachXO2 device supports on-chip 100 ohm (nominal) input differential termination on the bottom edge of MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 devices. The termination is available on all input PIO pairs of the bottom edge and is programmable. Emulated Differential Outputs All sysIO buffer pairs support complementary outputs as described above. This feature can be used to drive complementary SSTL or HSTL signals as required for differential SSTL and HSTL standards. It can also be used together with off-chip resistor networks for emulating the differential output standards such as LVPECL, MLVDS, BLVDS, MIPI and RSDS differential standards. When a sysIO buffer pair is configured as differential transmitter, the bus maintenance and open drain capabilities will be disabled. All single-ended sysIO buffers pairs in the MachXO2 family can support emulated differential output standards. True Differential Output And Output Drive MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 devices support true differential output drivers on the top edge of these devices. These true differential outputs are only available on the primary PIO pairs. The output driver has a fixed common mode of 1.2 V and a programmable drive current of 1.25 mA, 2.5 mA, 2.0 mA or 3.5 mA. Only one true LVDS differential drive setting is available at a time. All true LVDS differential drivers on the top edge must be programmed to have the same drive strength. The bank VCCIO for true differential output can be 2.5 V or 3.3 V. Software sysIO Attributes The sysIO attributes or primitives must be used in the Lattice development software to control the functions and capabilities of the sysIO buffers. sysIO attributes or primitives can be specified in the HDL source code, in the Lattice Diamond™ Spreadsheet View GUI, or in the ASCII preference file (.lpf) file directly. Appendices A, B and C list examples of using such attributes in different environments. This section describes each of these attributes in detail. HDL Attributes All the attributes discussed in this section, except two, can be used in the HDL source code to direct the sysIO buffer functionality. IO_TYPE 10 MachXO2 sysIO Usage Guide This attribute is used to set the sysIO standard for an I/O. The VCCIO required to set these I/O standards are embedded in the attribute names. The BANK VCCIO attribute is used to specify allowed VCCIO combinations for each I/O type. Table shows the valid I/O types for the MachXO2 family. 11 MachXO2 sysIO Usage Guide Table 8. Supported I/O Types sysIO Signaling Standard IO_TYPE LVDS 2.5 V LVDS25 1 Emulated LVDS 2.5 V LVDS25E RSDS RSDS25 Emulated RSDS1 RSDS25E Bus LVDS 2.5 V BLVDS25 Emulated Bus LVDS 2.5 V1 BLVDS25E MLVDS 2.5 V MLVDS25 Emulated MLVDS 2.5 V1 MLVDS25E LVPECL 3.3 V LVPECL33 1 Emulated LVPECL 3.3 V LVPECL33E SSTL 25 Class I SSTL25_I SSTL 25 Class II2 SSTL25_II SSTL 25 Class I differential3 SSTL25D_I SSTL 25 Class II differential2, 3 SSTL25D_II SSTL 18 Class I SSTL18_I SSTL 18 Class II2 SSTL18_II SSTL 18 Class I differential3 SSTL 18 Class II differential SSTL18D_I 2, 3 SSTL18D_II HSTL 18 Class I HSTL18_I HSTL 18 Class II2 HSTL18_II HSTL 18 Class I differential3 HSTL18D_I HSTL 18 Class II differential2,3 HSTL18D_II PCI 3.3 V PCI33 LVTTL 3.3 V LVTTL33 LVTTL 3.3 V differential3 LVTTL33D LVCMOS 3.3 V LVCMOS33 LVCMOS 3.3 V differential3 LVCMOS33D LVCMOS 2.5 V (default) LVCMOS 2.5 V differential LVCMOS25 3 LVCMOS25D LVCMOS 2.5 V in a 3.3 V VCCIO bank4 LVCMOS25R33 LVCMOS 1.8 V LVCMOS18 LVCMOS 1.8 V differential3 LVCMOS18D LVCMOS 1.8 V in 3.3 V VCCIO bank4 LVCMOS18R33 4 LVCMOS18R25 LVCMOS 1.8 V in 2.5 V VCCIO bank LVCMOS 1.5 V LVCMOS15 LVCMOS 1.5 V differential3 LVCMOS15D LVCMOS 1.5 V in 3.3 V VCCIO bank4 LVCMOS15R33 LVCMOS 1.5 V in 2.5 V VCCIO bank4 LVCMOS15R25 LVCMOS 1.2 V LVCMOS12 LVCMOS 1.2 V differential3 LVCMOS12D MIPI MIPI 1. These differential output standards are emulated by using a complementary LVCMOS driver pair together with an external resistor pack. 2. Only input mode is supported. Output or bidirectional modes are not supported for these I/O types. 3. These differential standards are implemented by using a complementary LVCMOS driver pair. 4. These are input only and require VREF to be set to certain value to allow the specified I/O types to be used. 12 MachXO2 sysIO Usage Guide DRIVE The DRIVE strength attribute is available for the output and bidirectional I/O standards. The default drive value depends on the I/O standard used. Table 9 shows the supported drive strength for the single-ended I/O types under designated VCCIO conditions. Table 9. Output Drive Capability for Ratioed sysIO Standards I/O Type Drive Strength (mA) LVCMOS12 2 YES 4 6 LVCMOS15 LVCMOS18 LVCMOS25 LVCMOS33 LVTTL33 YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES YES 81 12 16 24 1. Hardware Default (Erased) setting DIFFDRIVE The DIFFDRIVE strength attribute is available for the true LVDS output standard. All true LVDS differential drivers on the top edge must be programmed to have the same drive strength. The DIFFDRIVE value will be listed in the DRIVE column of Design Planner since this value is only valid for LVDS25 outputs. Values: 1.25, 2.0, 2.5, 3.5, NA Software Default: 3.5 Hardware Default (Erased): NA PULLMODE The PULLMODE option can be enabled or disabled independently for each I/O. When the user selects OPENDRAIN=ON, the PULLMODE for the output standard is default to NONE. If using LVCMOS I/O type in an under-drive or over-drive mode, the UP and KEEPER settings are not supported The FAILSAFE option is available for MLVDS25E bi-directional mode only. Values: UP, DOWN, NONE, KEEPER, FAILSAFE Software Default: DOWN for LVTTL, LVCMOS, and PCI; all others NONE Hardware Default (Erased): Down CLAMP The CLAMP option can be enabled or disabled independently for each I/O. The available settings on the bottom edge of MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 devices is PCI or OFF. All other I/O have ON or OFF settings for this attribute. Values: OFF, ON, PCI Software Default: OFF Hardware Default (Erased): OFF 13 MachXO2 sysIO Usage Guide HYSTERESIS The ratioed input buffers have two input hysteresis settings. The HYSTERESIS option can be used to change the amount of hysteresis for the LVTTL and LVCMOS input and bidirectional I/O standards, except for the LVCMOS12 inputs. The LVCMOS12 inputs do not support HYSTERESIS. The LVCMOS25R33, LVCMOS18R25, LVCMOS18R33, LVCMOS15R25, and LVCMOS15R33 input types do not support HYSTERESIS. The HYSTERESIS option for each of the input pins can be set independently when it is supported for the I/O type. Values: SMALL, LARGE, NA Software Default: SMALL Hardware Default (Erased): with very small hysteresis (0~60 mV) VREF The VREF option is enabled for single-ended SSTL and HSTL inputs and the referenced LVMCOS input buffers. The referenced LVMCOS input buffers are specified by choosing the I/O type as LVCMOS25R33, LVCMOS18R25, LVCMOS18R33, LVCMOS15R25, or LVCMOS15R33. The default value of NA will apply for all I/O types that do not use a VREF signal. The VREF will default to external VREF pin for the single-ended SSTL/HSTL inputs, LVCMOS25R33, LVCMOS18R25, LVCMOS18R33, LVCMOS15R25, or LVCMOS15R33 inputs. The user may enter a VREF_NAME value in the “VREF Location(s)” pop-up window of the Spreadsheet View of the Diamond software. In doing so, the software will present the VREF_NAME as an available value in additional to the I45, I50 and I55 values in the VREF column of the Port Assignments tab of the Diamond Spreadsheet View. A pin location specified by the VREF_NAME value will be used as the VREF driver for that I/O bank. VREF_NAME is only necessary if the user wants to specify a pin to be used as an external VREF pin. Otherwise, the software will automatically assign a pin for the VREF signal. There is only one VREF pin or internal VREF driver per I/O bank. Only one of the VREF driver settings chosen from I45, I50, I55 or VREF1_LOAD can be used in each I/O bank. This attribute can be set in the software GUI or in the ASCII preference file. Values: OFF, I45, I50, Values: OFF, I45, I50, I55, VREF_NAME Software Default: NA Hardware Default (Erased): OFF OPENDRAIN The OPENDRAIN option is available for all LVTTL and LVCMOS output and bidirectional I/O standards. Each sysIO can be assigned independently to be open drain. When the OPENDRAIN attribute is used, the PULLMODE must be NONE and the CLAMP must be OFF. Values: OFF, ON Software Default: OFF Hardware Default (Erased): OFF SLEWRATE Each I/O pin has an individual slew rate control. This allows the designer to specify slew rate control on a pin-by-pin basis for outputs and bidirectional I/O pins. This is not a valid attribute for inputs or true differential outputs. Values: FAST, SLOW, NA Software Default: SLOW Hardware Default (Erased): SLOW 14 MachXO2 sysIO Usage Guide DIFFRESISTOR The bottom side I/O pins support on-chip differential input termination resistors on the MachXO2-640U, MachXO21200/U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 devices. The termination resistor is available for both the primary pair and the alternate pair of a sysIO. The values supported are zero (OFF) or 100 ohms. Values: OFF, 100 Software Default: OFF Hardware Default (Erased): OFF DIN/DOUT The DIN/DOUT option is available for each I/O and can be configured independently. An input register is used for the input if the DIN attribute is assigned. Similarly, the software assigns an output register when the DOUT attribute is specified. By default, the software automatically assigns DIN or DOUT to input or output registers if possible. LOC This attribute specifies the site location for the component after the mapping process. When attached to multiple components, it indicates that these blocks are to be mapped together in the specified site. It specifies the PIC site for the pad when it is assigned to a pad. The LOC attribute can be attached to components that will end up on an I/O cell, clocks, and internal flip-flops, but it should not be attached to combinational logic that will end up on a logic cell; doing so could fail to generate a locate preference. The LOC attribute overrides register ordering. Bank VCCIO This attribute is necessary to verify the valid I/O types for a bank, to determine which input buffer to use, and to set the correct drive strength for the applicable I/O types. Since the I/O bank information is not required at the HDL level, this attribute is available through either the Diamond software’s Spreadsheet View or in the ASCII preference file. Values: AUTO, 3.3, 2.5, 1.8, 1.5, 1.2. Software Default: AUTO. sysIO Primitives There are many sysIO primitives in the software library. A few are selected to be discussed in this section because some sysIO capabilities can only be utilized through instantiating the primitives in the HDL source code. Tri-State All (TSALL) The MachXO2 device supports the TSALL function that is used to enable or disable the tristate control to all the output buffers. The user can choose to assign any general purpose I/O pin to control the TSALL function since there is no dedicated TSALL pin. The TSALL primitive must be instantiated in the source code in order to enable the TSALL function. The input of the primitive can be assigned to an input pin or to an internal signal. A value of TSALL=1 will tri-state all outputs but the outputs will be under individual OE control when TSALL=0. Figure 5. TSALL Primitive TSALL TSALL Fixed Data Delay (DELAYE) This primitive supports up to 32 steps of static delay for all sysIO buffers in all banks of a MachXO2 device. Refer to DS1035, MachXO2 Family Data Sheet for delay step values. Although users can choose USER_DEFINED mode to set input delay, this primitive is primarily used by pre-defined source synchronous interfaces as described in TN1203, MachXO2 High-Speed Source Synchronous and Memory Interfaces. 15 MachXO2 sysIO Usage Guide Figure 6. DELAYE Primitive and Associated Attributes A Attribute DELAYE Description Z Value DEL_MODE Fixed delay value depending on interface or user-defined delay values SCLK_ZEROHOLD ECLK_ALIGNED ECLK_CENTERED SCLK_ALIGNED SCLK_CENTERED USER_DEFINED DEL_VALUE User-defined value DELAY0…DELAY31 Software Default USER_DEFINED DELAY0 Dynamic Data Delay (DELAYD) This primitive supports dynamic delay for the sysIO buffers in the bottom bank (Bank 2) of MachXO2-640U, MachXO2-1200/U and larger devices. The 5-bit inputs can be controlled by user logic to modify the delay during the device operation. Figure 7. DELAYD Primitive A Z DEL4 DEL3 DEL2 DELAYD DEL1 DEL0 Design Consideration and Usage This section summarizes the MachXO2 designs rules and considerations that have been discussed in detail in previous sections. Table 6 lists the miscellaneous I/O features on each side of a MachXO2 device. sysIO Buffer Features Common to All MachXO2 Devices 1. All banks support true differential inputs. 2. All banks support emulated differential outputs using external resistors and complementary LVCMOS outputs. Emulated differential output buffers are supported on both primary and alternate pairs. 3. All banks have programmable I/O clamps but they are not PCI compliant clamps. 4. All banks support weak pull-up, pull-down, and bus-keeper (bus hold latch) settings on each I/O independently. 5. VCCIO voltage levels, together with the selected I/O types, determine the characteristics of an I/O, such as the pull mode, hysteresis, clamp behavior, and drive strength, supported in a bank. Multiple input standards can be supported in a bank through under-drive or over-drive conditions. Only one alternative input standard can be supported through the bank VREF setting (for example, LVCMOS25R33 requires VREF to be 1.25 V in a 3.3 V VCCIO bank). Each bank also supports 1.2 V inputs regardless of the VCCIO setting of the bank. 6. Each bank supports one VCCIO signal. 7. Each bank supports one VREF signal, whether it is from an external pin or from the internal VREF generator. sysIO Buffer Rules Specific to MachXO2-256 and MachXO2-640 1. Does not support true differential output buffers. 2. Does not support internal 100 ohm differential input terminations. 3. Does not support PCI clamps. 16 MachXO2 sysIO Usage Guide sysIO Buffer Rules Specific to MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 1. Only Bank 0 (top side) supports true differential output buffers with programmable drive strengths. Only the primary pair supports true differential output buffers. 2. Only Bank 2 (bottom side) supports internal 100 ohm differential input terminations. 3. Only Bank 2 (bottom side) supports PCI compliant clamps. Table 10. Miscellaneous I/O Features on Each Device Edge Feature Top Bottom 1 Left Right 100 Ohm Differential Resister — Yes — — Hot Socket Yes Yes Yes Yes Clamp3 Yes Yes Yes Yes PCI Compliant Clamp — Yes1 — — Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Weak Pull-up 3 Weak Pull-down2 Bus Keeper 3 Input Hysteresis3 Slew Rate Control Yes Yes Yes Yes Open Drain Yes Yes Yes Yes 1. Supported by MachXO2-640U, MachXO2-1200/U, MachXO2-2000/U, MachXO2-4000, and MachXO2-7000 devices. 2. Software default setting 3. I/O characteristic under special conditions a.HYSTERESIS option is not available for LVCMOS12. b.HYSTERESIS option and BUS KEEPER option are not available for referenced input standards. c.When using the ratioed input buffers in under-drive or over-drive conditions, the HYSTERESIS setting shall be NA, the CLAMP setting shall be OFF, and the UP and KEEPER PULLMODE settings are not supported. d.HYSTERESIS and the bus maintenance capabilities are disabled for differential receivers. Technical Support Assistance Submit a technical support case via www.latticesemi.com/techsupport. 17 MachXO2 sysIO Usage Guide Revision History Date Version April 2015 2.0 Change Summary Updated the following sections to add MIPI information: — Supported sysIO Standards. Updated Table 1, Supported Input Standards and Table 2, Supported Output Standards. — sysIO Standards Supported by I/O Banks. Updated Table 4, Differential I/O Standards Supported on Various Sides — Software sysIO Attributes. Updated Table 8, Supported I/O Types. Updated Input Hysteresis section. Added information. Updated Emulated Differential Outputs section. Added MIPI to examples of output standards. Updated Technical Support Assistance section. August 2014 1.9 Updated Table 10-6, Mixed Voltage Support for LVCMOS and LVTTL I/O Types. Revised data on VCCIO 1.2 V. July 2014 1.8 Updated the HDL Attributes section. Indicated Software Default and Hardware Default (Erased) settings. Updated Table 10-9, Output Drive Capability for Ratioed sysIO Standards. Added note. October 2013 01.7 Changed I/O_TYPE to IO_TYPE. August 2013 01.6 Updated Mixed Voltage Support for LVCMOS and LVTTL I/O Types table. March 2013 01.5 Updated Technical Support Assistance information. Updated footnotes in the Mixed Voltage Support for LVCMOS and LVTTL I/O Types table. Added information on LVCMOS Buffer Configurations - Programmable Slew Rate. February 2012 01.4 Updated document with new corporate logo. July 2011 01.3 Updated sysIO Banking Scheme text section with information on migrating from MachXO2-1200-R1 to Standard (non-R1) devices. April 2011 01.2 Updated for Lattice Diamond design software. January 2011 01.1 Updated for ultra-high I/O (“U”) devices. November 2010 01.0 Initial release. Document status changed from Preliminary to Final. 18 MachXO2 sysIO Usage Guide Appendix A. sysIO HDL Attributes The sysIO attributes can be used directly in the HDL source codes. This section provides a list of sysIO attributes supported by the MachXO2 PLD family. The correct syntax and examples for the Synplify® synthesis tool are provided here for reference. Attributes in VHDL Language Syntax Table 11. VHDL Attribute Syntax Attribute Syntax IO_TYPE attribute IO_TYPE: string; attribute IO_TYPE of Pinname: signal is “IO_TYPE Value”; DRIVE attribute DRIVE: string; attribute DRIVE of Pinname: signal is “Drive Value”; DIFFDRIVE attribute DRIVE: string; attribute DRIVE of Pinname: signal is “Diffdrive Value”; DIFFRESISTOR attribute DIFFRESISTOR: string; attribute DIFFRESISTOR of Pinname: signal is “DIFFRESISTOR Value”; CLAMP attribute CLAMP: string; attribute CLAMP of Pinname: signal is “Clamp Value”; HYSTERESIS attribute HYSTERESIS: string; attribute HYSTERESIS OF Pinname: signal is “Hysteresis Value”; VREF NA PULLMODE attribute PULLMODE: string; attribute PULLMODE of Pinname: signal is “Pullmode Value”; OPENDRAIN attribute OPENDRAIN: string; attribute OPENDRAIN of Pinname: signal is “OpenDrain Value”; SLOWSLEW attribute PULLMODE: string; attribute PULLMODE of Pinname: signal is “Slewrate Value”; DIN attribute DIN: string; attribute DIN of Pinname: signal is “value “; DOUT attribute DOUT: string; attribute DOUT of Pinname: signal is “value “; LOC attribute LOC: string; attribute LOC of Pinname: signal is “Pin locations”; BANK VCCIO NA Examples IO_TYPE --***Attribute Declaration*** ATTRIBUTE IO_TYPE: string; --***IO_TYPE assignment for I/O Pin*** ATTRIBUTE IO_TYPE OF portA: SIGNAL IS "PCI33"; ATTRIBUTE IO_TYPE OF portB: SIGNAL IS "LVCMOS33"; ATTRIBUTE IO_TYPE OF portC: SIGNAL IS "SSTL18_I"; ATTRIBUTE IO_TYPE OF portD: SIGNAL IS "LVDS25"; 19 MachXO2 sysIO Usage Guide DRIVE --***Attribute Declaration*** ATTRIBUTE DRIVE: string; --***DRIVE assignment for I/O Pin*** ATTRIBUTE DRIVE OF portB: SIGNAL IS “8”; DIFFDRIVE --***Attribute Declaration*** ATTRIBUTE DIFFDRIVE: string; --*** DIFFDRIVE assignment for I/O Pin*** ATTRIBUTE DIFFDRIVE OF portD: SIGNAL IS “2.0”; DIFFRESISTOR --***Attribute Declaration*** ATTRIBUTE DIFFRESISTOR: string; --*** DIFFRESISTOR assignment for I/O Pin*** ATTRIBUTE DIFFRESISTOR OF portD: SIGNAL IS "100"; CLAMP --***Attribute Declaration*** ATTRIBUTE CLAMP: string; --*** CLAMP assignment for I/O Pin*** ATTRIBUTE CLAMP OF portA: SIGNAL IS “PCI33”; HYSTERESIS --***Attribute Declaration*** ATTRIBUTE HYSTERESIS: string; --*** HYSTERESIS assignment for Input Pin*** ATTRIBUTE HYSTERESIS OF portA: SIGNAL IS " LARGE "; PULLMODE --***Attribute Declaration*** ATTRIBUTE PULLMODE : string; --***PULLMODE assignment for I/O Pin*** ATTRIBUTE PULLMODE OF portA: SIGNAL IS “DOWN”; ATTRIBUTE PULLMODE OF portB: SIGNAL IS “UP”; OPENDRAIN --***Attribute Declaration*** ATTRIBUTE OPENDRAIN: string; --***Open Drain assignment for I/O Pin*** ATTRIBUTE OPENDRAIN OF portB: SIGNAL IS “ON”; SLEWRATE --***Attribute Declaration*** ATTRIBUTE SLEWRATE : string; --*** SLEWRATE assignment for I/O Pin*** ATTRIBUTE SLEWRATE OF portB: SIGNAL IS “FAST”; DIN/DOUT --***Attribute Declaration*** ATTRIBUTE din : string; ATTRIBUTE dout : string; --*** din/dout assignment for I/O Pin*** ATTRIBUTE din OF input_vector: SIGNAL IS “TRUE “; ATTRIBUTE dout OF output_vector: SIGNAL IS “TRUE “; 20 MachXO2 sysIO Usage Guide LOC --***Attribute Declaration*** ATTRIBUTE LOC : string; --*** LOC assignment for I/O Pin*** ATTRIBUTE LOC OF input_vector: SIGNAL IS “E3,B3,C3 “; Attributes in Verilog Language Syntax Table 12. Verilog Attribute Syntax Attribute Syntax IO_TYPE PinType PinName /* synthesis IO_Type=”IO_Type Value”*/; DRIVE PinType PinName /* synthesis DRIVE=”Drive Value”*/; DIFFDRIVE PinType PinName /* synthesis DIFFDRIVE =” DIFFDRIVE Value”*/; DIFFRESISTOR PinType PinName /* synthesis DIFFRESISTOR =” DIFFRESISTOR Value”*/; CLAMP PinType PinName /* synthesis CLAMP =” Clamp Value”*/; HYSTERESIS PinType PinName /*synthesis HYSTERESIS = “Hysteresis Value” */; VREF N/A PULLMODE PinType PinName /* synthesis PULLMODE=”Pullmode Value”*/; OPENDRAIN PinType PinName /* synthesis OPENDRAIN =”OpenDrain Value”*/; SLOWSLEW PinType PinName /* synthesis SLEWRATE=”Slewrate Value”*/; DIN PinType PinName /* synthesis DIN= “value” */; DOUT PinType PinName /* synthesis DOUT= “value” */; LOC PinType PinName /* synthesis LOC=”pin_locations “*/; Bank VCCIO N/A Examples //IO_TYPE, PULLMODE, SLEWRATE and DRIVE assignment output portB /*synthesis IO_TYPE=”LVCMOS33” PULLMODE =”UP” SLEWRATE =”FAST” DRIVE =”20”*/; output portC /*synthesis IO_TYPE=”LVDS25” */; //DIFFDRIVE output portD /* synthesis IO_TYPE="LVDS25" DIFFDRIVE="2.0"*/; //DIFFRESISTOR output [4:0] portA /* synthesis IO_TYPE="LVDS25" DIFFRESISTOR ="100"*/; //CLAMP output portA /*synthesis IO_TYPE=”PCI33” CLAMP =”PCI” */; //HYSTERESIS input mypin /* synthesis HYSTERESIS = “LARGE” */; //OPENDRAIN output portA /*synthesis OPENDRAIN =”ON”*/; // DIN Place the flip-flops near the load input input load /* synthesis din=”” TRUE */; 21 MachXO2 sysIO Usage Guide // DOUT Place the flip-flops near the outload output output outload /* synthesis dout=”TRUE” */; //LOC pin location input [3:0] DATA0 /* synthesis loc=”E3,B1,F3”*/; //LOC Register pin location reg data_in_ch1_buf_reg3 /* synthesis loc=”R10C16” */; //LOC Vectored internal bus reg [3:0] data_in_ch1_reg /*synthesis loc =”R10C16,R10C15,R10C14,R10C9” */; 22 MachXO2 sysIO Usage Guide Appendix B. sysIO Attributes Using the Spreadsheet View The sysIO buffer attributes can be assigned using the Spreadsheet View available in the Diamond design tool. The attributes that are not available as HDL attributes, such as VREF and Bank VCCIO, are available in the Spreadsheet View GUI. The Port Assignment tab lists all the ports in a design and all the available sysIO attributes as preferences. Click on each of these cells for a list of all the valid I/O preferences for that port. Each column takes precedence over the next. Therefore, when a particular IO_TYPE is chosen, the columns for the DRIVE, PULL-MODE, SLEW-RATE and other attributes will list the valid combinations for that IO_TYPE. Pin locations can be locked using the Pin column of the Port Assignment tab. Right-clicking on a cell will list all the available pin locations. The Spreadsheet View can run a DRC check to check for incorrect sysIO attribute assignments. All the preferences assigned using the Spreadsheet View are written into the logical preference file (.lpf). Figure 8. Port Assignment Tab of Spreadsheet View 23 MachXO2 sysIO Usage Guide Figure 9. VREF Name and Location Pop-up Window of the Spreadsheet View VREF Assignment in the Spreadsheet View The VREF attribute can be assigned in the Spreadsheet View by clicking on the Vref Location(s) button on the left hand side. It is required to use this button only if a specific location for the VREF driver is desired. Otherwise the software will assign the VREF driver signal to any location that does not violate the sysIO bank rules. When the VREF_NAME is assigned to a specific pin, the software will list VREF_NAME in the VREF column of the Port Assignments tab. Both VREF_NAME and pin location will be reflected in the VREF column of the Pin Attribute sheet. Bank VCCIO Setting in the Spreadsheet View Bank VCCIO is editable in the Global tab of the Spreadsheet View. The value of the Bank VCCIO can be chosen by the users to determine the value of VCCIO of a specific bank. 24 MachXO2 sysIO Usage Guide Figure 10. Bank VCCIO in Global Preference Tab 25 MachXO2 sysIO Usage Guide Appendix C. sysIO Attributes Using Preference File (ASCII File) Designers can enter sysIO attributes directly in the preference (.lpf) file as sysIO buffer preferences. The LPF file is a post-synthesis FPGA constraint file that stores logical preferences that have been created or modified in the Spreadsheet View or directly in a text editor. It also contains logical preferences originating in the HDL source. Modifying the Spreadsheet View in the Diamond software will automatically update the content of the LPF file and vice versa. The settings in the Spreadsheet View are reflected in the preference file once they are saved. Details of the supported preferences and their corresponding syntax can be found in the Diamond Help System. 26