RENESAS R2A20154NS

New Product
R2A20154NS/SP
8-bit 4ch D/A Converter with Buffer Amplifiers for I2C BUS (Corresponds to Fast mode)
R03DS0014EJ0100
Rev.1.00
2011.09.05
Description
The R2A20154 is an integrated circuit semiconductor of CMOS structure with 4 channels of built in D/A
converters with output buffer operational amplifiers. It is the electrical characteristic improvement version of
the M62334.
The input is 2-wires serial method is used for the transfer format of digital data to allow connection with a
microcomputer with minimum wiring. This IC corresponds to Fast mode of I2C BUS standard.
The output buffer operational amplifier employs AB class output circuit with sync and source drive capacity of
1.0mA or more, and it operates in the whole voltage range from Vcc to ground.
Features
 Guarantee Differential nonlinearity error : +/-0.7LSB, Nonlinearity error : +/-1.0LSB
 Digital data transfer format: I2C BUS serial data method (Corresponds to Fast mode: 400kHz)
 Output buffer operational amplifier
It operates in the whole range from Vcc to ground.
 High output current drive capacity: 1mA over
 The very small size SON-8 package is added to the lineup.
Application
Conversion from digital data to analog control data for home-use and industrial equipment.
Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor.
Blurring correction control or various control of the interchangeable lens of digital camera
Block Diagram
Vcc
SCL
SDA
GND
8
7
6
5
I2C BUS transceiver
Power on
reset
8
R03DS0014EJ0100 Rev.1.00
2011.09.05
Channel
decoder
8-bit latch
8-bit latch
8-bit latch
8-bit latch
8-bit upper
segment R-2R
8-bit upper
segment R-2R
8-bit upper
segment R-2R
8-bit upper
segment R-2R
+-
+-
+-
+-
1
2
3
4
Ao1
Ao2
Ao3
Ao4
Page 1 of 8
New Product
R2A20154NS/SP
Pin Arrangement
R2A20154NS
R2A20154SP
Ao1 1
8 Vcc
Ao1 1
8 Vcc
Ao2 2
7 SCL
Ao2 2
7 SCL
Ao3 3
6 SDA
Ao3 3
6 SDA
Ao4 4
5 GND
Ao4 4
5 GND
(Top view)
(Top view)
Outline: PWSN0008KA-A [NS]
Outline: PRSP0008DE-C [SP]
Pin Description
Pin No.
Pin Name
1
Ao1
2
Ao2
8-bit resolution D/A converter output terminal
3
Ao3
(After power on, analog output of every channel is set in DAC data “00h”)
4
Ao4
5
GND
GND terminal
6
SDA
Serial data input terminal
7
SCL
Serial clock input terminal
8
Vcc
Power supply terminal
R03DS0014EJ0100 Rev.1.00
2011.09.05
Function
Page 2 of 8
New Product
R2A20154NS/SP
Absolute Maximum Ratings
(Ta= 25 deg unless otherwise noted)
Item
Symbol
Condition
Ratings
Unit
Supply voltage
Vcc
-0.3 to +6.5
V
Input voltage
Vin
-0.3 to Vcc+0.3 < 6.5
V
Output voltage
Vo
-0.3 to Vcc+0.3 < 6.5
V
Buffer amplifier output current
IAO
Continuous
-2.0 to +2.0
mA
Pd
Ta = +85deg
270(NS) / 272(SP)
mW
Thermal derating factor
K theta
Ta > +25deg
6.75(NS) / 6.8(SP)
mW/deg
Operating temperature
Topr
-30 to +85
deg
Storage temperature
Tstg
-40 to +125
deg
Power dissipation
Electrical Characteristics
(Vcc= +5V +/-10%, GND=0V, Ta= -30 to +85deg unless otherwise noted)
Symbol
Item
Limits
Test Conditions
Vcc
Supply voltage
Supply voltage rise-up time *1
Operating voltage of
Internal resetting *1
Input leak current
Input low voltage
Input high voltage
Hysteresis (SDA, SCL)
Output low voltage (SDA)
Pulse width of spics
5.5
V
-
0.8
2.0
mA
SDA = SCL = GND, IAO=0µA
-
0.5
1.5
mA
100
-
-
µs
-
1.5
1.9
V
1
-
-
ms
-10
-
10
µA
0
-
0.2Vcc
V
0.8Vcc
-
Vcc
V
0.5
0.8
-
V
Isink = 3mA
-
-
0.4
V
0
-
50
ns
IAO =100µA
0.1
-
Vcc – 0.1
IAO =500µA
0.2
-
Vcc – 0.2
Upper side saturation voltage = 0.3V,
Lower side saturation voltage = 0.2V
-1.0
-
1.0
Vcc=0 to 2.7V
tPOR
Vcc < 0.1V
IILK
VIL
VIH
Vhys
VOL
tSP
VIN = 0 to Vcc
VAO
Buffer amplifier output drive
range
IAO
SDL
SL
SZERO
SFULL
Co
Differential nonlinearity
Nonlinearity
Zero code error
Full scale error
Output capacitate load
Buffer amplifier output
impedance
Unit
5.0
trVcc
Buffer amplifier output voltage
range
Max.
2.7
VccPOR Vcc=0 to 2.7V
Time period of re-power on
(Power supply OFF  ON) *1
Typ.
CLK = 500 kHz operation, IAO=0µA,
DATA: 6Ah (at maximum current)
Icc
Supply current
Min.
Vcc=5.12V (20mV/ LSB),
without load (IAO = 0µA)
Ro
V
mA
-0.7
-
0.7
LSB
-1.0
-
1.0
LSB
-2.0
-
2.0
LSB
-2.0
-
2.0
LSB
-
-
0.1
µF
-
5.0
-

*1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on quickly,
initialize is not operate. So, keep the time period of re-powered on (tPOR).
trVcc
Vcc
tPOR
(equivalent to trVcc)
VccPOR
GND
Internal
Reset signal
< 0.1V
GND
Resetting period
R03DS0014EJ0100 Rev.1.00
2011.09.05
Resetting period
Page 3 of 8
New Product
R2A20154NS/SP
I2C BUS Line Characteristics
Item
Symbol
SCL clock frequency
Free time: the bus must be free before a new
transmission can start
Hold time START condition after this period,
the first Clock pulse is generated
Low period of the clock
High period of the clock
Set-up time for START condition.
Only relevant for a repeated START condition.
Data Hold time
Data Set-up time
Rise time of SDA and SCL signals
FAST MODE
Unit
Min.
Max.
Min.
Max.
fSCL
0
100
0
400
kHz
tBUF
4.7
-
1.3
-
µs
tHD:STA
4.0
-
0.6
-
µs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
µs
µs
tSU:STA
4.7
-
0.6
-
µs
tHD:DAT
tSU:DAT
tR
0
250
-
3.45
1000
0
100
-
0.9
300
µs
ns
ns
tF
-
300
-
300
ns
tSU:STO
Cb
4.0
-
400
0.6
-
400
µs
pF
Fall time of SDA and SCL signals
Set-up time for STOP condition
Capacitive load of bus line
STANDARD MODE
All of above value are corresponds to VIHmin and VILmax.
Timing Chart
tR, tF
tBUF
VIH
SDA
VIL
tHD:STA
tSU:DAT
tHD:DAT
tsu:STA
tSU:ST0
VIH
SCL
VIL
tLOW
Start
R03DS0014EJ0100 Rev.1.00
2011.09.05
tHIGH
Start
Stop
Start
Page 4 of 8
New Product
R2A20154NS/SP
I2C BUS Format
STA
W
Slave address
A
A
Sub address
DAC data
A
STP
Note: STA: start condition, A: acknowledge bit, W: write (SDA=Low), STP: stop condition
 Slave address
First
1
Last
0
0
1
1
0
0
 Sub address
First
X
Last
X
X
X
X
X
Don’t care
S1
Channel select data
S1
0
0
1
1
S0
Channel
Select data
S0
0
1
0
1
Channel selection
ch1 selection
ch2 selection
ch3 selection
ch4 selection
 DAC data
First
MSB
D7
Last
LSB
D6
D5
D4
D3
D2
D1
D0
First
MSB
Last
LSB
D7
D6
D5
D4
D3
D2
D1
D0
DAC output
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Vcc/256 x 1
Vcc/256 x 2
Vcc/256 x 3
Vcc/256 x 4
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
0
Vcc/256 x 255
1
1
1
1
1
1
1
1
Vcc
R03DS0014EJ0100 Rev.1.00
2011.09.05
Page 5 of 8
New Product
R2A20154NS/SP
Data Timing Chart SCL and SDA (Model)
< Start condition to slave address bit >
SDA
1
2
3
4
5
6
7
W
A
2
3
4
5
6
7
8
A
SCL
D/A
output
Start condition
< Sun address bit >
SDA
1
SCL
D/A
output
< DAC data bit to stop condition >
SDA
1
2
3
4
5
6
7
8
A
SCL
D/A
output
Stop
condition
 Start condition
With SCL at High, SDA line goes from High to Low
 Stop condition
With SCL at High, SDA line goes from Low to High
( Under normal circumstance, SDA is changed when SCL is Low )
 Acknowledge bit
The receiving IC has to pull down SDA line whenever receive slave data.
( The transmitting IC releases the SDA line just then transmit 8-bit data. )
R03DS0014EJ0100 Rev.1.00
2011.09.05
Page 6 of 8
New Product
R2A20154NS/SP
Digital Data Format
STA
Slave address
Sub address 2
A
W
DAC data 2
A
Sub address 1
A
A
DAC data 1
Sub address n
A
DAC data n
A
A
STP
After the Start condition, the transmitting IC accesses the slave IC by Slave address, and transmits the
data to each channel by two bites (Sub address and DAC data).
Precaution For use
 Supply voltage terminal (Vcc) is also used for D/A converter upper reference voltage setting. If ripple or
spike is input this terminal, accuracy of D/A converter is down, So, when use this device, please connect
capacitor among Vcc to GND for stable D/A conversion.
 This IC’s output amplifier has an advantage to capacitive load, So, it’s no problem at device action when
connect capacitor ( 0.1 µF Max ) among output to GND for every noise elimination.
Application Example
1 Ao1
Analog output
terminals
3 Ao3
R2A20154NS/SP
2 Ao2
Vcc
4 Ao4
8
+
10µF
5V
5V
SCL 7
MCU
SDA 6
GND 5
Ordering Information
Order part No.
Package Name
Package Code
Package type No.
Packing/Quantity
R2A20154SP
SOP-8
PRSP0008DE-C
SP
Embossed Taping/2,500 pcs.
R2A20154NS
SON-8
PWSN0008KA-A
NS
Embossed Taping/5,000 pcs.
R03DS0014EJ0100 Rev.1.00
2011.09.05
Page 7 of 8
R2A20154NS/SP
New Product
Package Dimensions
PRSP0008DE-C [SP]
PWSN0008KA-A[NS]
R03DS0014EJ0100 Rev.1.00
2011.09.05
Page 8 of 8
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