New Product R2A20178NP 8-bit 8ch Multiplying D/A Converter with Buffer Amplifiers R03DS0021EJ0100 Rev.1.00 2011.09.05 Description The R2A20178 is a CMOS 8-bit 8ch D/A converter having a multiplying function and output buffer amplifiers. It has a serial data input and can easily communicate with a microcontroller by simple three-wiring method (DI, CLK, LD), and it is suitable for a use in automatic adjustment applications in conjunction with a MCU. The reference voltage terminals (VDAref1, VDAref2) are 4ch x 2 configuration, and the 4 quadrant operation is possible. Features Guarantee Nonlinearity error : +/-1.0LSB, Differential nonlinearity error : +/-0.7LSB Three-wiring serial data transmission High performance 8ch D/A converter employing an R-2R with higher-order segment method 8 buffer amplifiers operating in a whole supply voltage range from VDD to GND High anti-oscillation stability for capacitive loads 4 quadrant multiplication Very small package : QFN (pin pitch 0.5mm) Application Digital to analog conversion for consumer and industrial equipment. Self adjustment by combination with microcomputer and EEPROM (substitution of half fixed resistance) Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor. Voltage control of transmission power amplifier of transceiver Block Diagram VDD 2 DI 5 CLK 4 12-bit shift register D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 3 LD 15 VDAref2 Address decoder RESET VDAref1 8-bit Latch 8-bit Latch D/A converter D/A converter 16 14 ch2 ch3 ch4 ch5 ch6 ch7 22 VIN1 R03DS0021EJ0100 Rev.1.00 2011.09.05 23 VOUT1 21 VIN8 20 VOUT8 Page 1 of 7 New Product R2A20178NP Pin Arrangement 4 DI 5 VIN3 6 19 VOUT7 21 VIN8 22 VIN1 20 VOUT8 16 RESET 15 VDAref2 14 VDAref1 13 VIN6 VOUT6 12 CLK 17 GND VOUT5 11 3 VIN5 10 LD VIN4 9 2 VOUT4 8 VDD 18 VIN7 VOUT3 7 1 R2A20178NP VIN2 23 VOUT1 24 VOUT2 R2A20178NP (Top view) Outline : PWQN0024KD-A [NP] Pin Description Pin No. Pin Name Function 3 LD 4 CLK 5 DI 16 RESET 23 VOUT1 24 VOUT2 7 VOUT3 8 VOUT4 11 VOUT5 12 VOUT6 19 VOUT7 20 VOUT8 2 VDD Power supply 17 GND Ground 22 VIN1 1 VIN2 6 VIN3 9 VIN4 10 VIN5 13 VIN6 18 VIN7 21 VIN8 14 VDAref1 D/A converter reference voltage input (ch1 to ch4). VOUT= (VIN-VDAref) x n/256+VDAref1 15 VDAref2 D/A converter reference voltage input (ch5 to ch8). VOUT= (VIN-VDAref) x n/256+VDAref2 A low state of LD enables data of DI loading to the 12-bit resister. During a rising edge of LD, the data in the 12-bit shift register on a rising edge of register. Shift clock input. Input data of DI are taken into the 12-bit shift register on a rising edge Of the clock. Serial data input. The serial data length is 12-bit. Reset 8-bit latches. A low state of RESET clear the all 8-bit latches. D/A converter output with 8-bit resolution D/A converter input R03DS0021EJ0100 Rev.1.00 2011.09.05 Page 2 of 7 New Product R2A20178NP Absolute Maximum Ratings (Ta= +25deg unless otherwise noted) Item Symbol Supply voltage (for digital) VDD Conditions Ratings Unit -0.3 to +6.5 V Digital input voltage VIND -0.3 to +6.5 V Analog input voltage VIN -0.3 to VDD+0.3 <+6.5 V Analog output voltage VOUT -0.3 to VDD+0.3 <+6.5 V D/A reference voltage VDAref -0.3 to VDD+0.3 <+6.5 V Power dissipation Pd Ta= +85deg 300 mW Ta> +25deg Thermal derating K theta 7.5 mW/deg Operating temperature Topr -30 to +85 deg Storage temperature Tstg -40 to +125 deg Electrical Characteristics < Analog/Digital Common Part > (VDD,VIN= +5V +/-10%, VDD>VIN, GND=VDAref1=VDAref2 = 0V, Ta = -30 to +85deg, unless otherwise noted.) Item Symbol Supply voltage VDD Supply current IDD < Digital Part > Conditions CLK =1MHz, VDD =5V, IAO =0µA Min Limits Typ Max 2.7 5.0 5.5 V - - 2.0 mA Unit (VDD,VIN = +5V +/-10%, VDD>VIN, GND=VDAref1=VDAref2 = 0V, Ta = -30 to +85deg, unless otherwise noted.) Item Symbol Conditions Limits Unit Min Typ Max -10 - 10 µA Input leak current IILK Digital input “Low” voltage VIL - - 0.2 VDD V Digital input “High” voltage VIH 0.8 VDD - - V < Analog Part > VIN = 0 to VDD (VDD,VIN = +5V +/-10%, VDD>VIN, GND=VDAref1=VDAref2 = 0V, Ta = -30 to +85deg, unless otherwise noted.) Item Input current Symbol Typ Max - - 0.3 mA -2.4 - - mA - 8 - bit VDAref1 =VDAref2 =0.05V, Without load ( IVOUT= 0µA ) -0.7 - 0.7 LSB -1 - 1 LSB IAO = +/-100 µA 0.1 - VCC – 0.1 IAO = +/-500 µA 0.2 - VCC – 0.2 Upper saturation voltage =0.4V, Lower saturation voltage =0.4V -1 - 1 mA CO - - 0.1 µF RO - 5 - ohm IIN IDAref Resolution RES Differential nonlinearity DNL nonlinearity NL Buffer amplifier output voltage range VAO Buffer amplifier output current range IAO R03DS0021EJ0100 Rev.1.00 2011.09.05 Unit Min D/A reference input current Output capacitive load Buffer amplifier output impedance Limits Conditions VIN =5V, VDAref =0 V, Proportional to Max. input current condition (VIN –VDAref) and digital data of each channels VIN1 to VIN8 =5V, VDAref =0 V, Proportional to Max. input current condition (VIN –VDAref) and digital data of each channels V Page 3 of 7 New Product R2A20178NP AC Characteristics (VDD,VIN = +5V +/-10%, VDD>VIN, GND=VDAref1=VDAref2 = 0V, Ta = -30 to +85deg, unless otherwise noted.) Item Symbol Conditions Min Limits Typ Max Unit Clock “L” pulse width tCKL 200 - - ns Clock “H” pulse width tCKH 200 - - ns Clock rise time tCR - - 200 ns Clock fall time tCF - - 200 ns Data setup time tDCH 60 - - ns Data hold time tCHD 100 - - ns LD setup time tCHL 200 - - ns LD hold time tLDC 100 - - ns LD “H” pulse duration time tLDH 100 - - ns D/A output settling time tLDD - - 300 µs RESET “Low” level minimum pulse width tRL 200 - - ns CL <100pF, VOUT : 0.54.5V, Time until the output becomes the final value of 1/2 LSB Timing Chart tCR tCKH tCF CLK tCKL DI tDCH tCHD tCHL tLDH tLDC LD tLDD D/A output R03DS0021EJ0100 Rev.1.00 2011.09.05 Page 4 of 7 New Product R2A20178NP Digital Data Format 12-bit serial data Last LSB First MSB DATA 1 2 3 4 5 6 7 8 9 10 11 12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK Data Assignment D8 D9 D10 D11 D0 D1 D2 D3 : DAC select data D4 D5 D6 D7 : DAC data DAC select data D8 D9 D10 D11 DAC Selection 0 0 0 0 Don’t care 0 0 0 1 VOUT1 selection 0 0 1 0 VOUT2 selection 0 0 1 1 VOUT3 selection 0 1 0 0 VOUT4 selection 0 1 0 1 VOUT5 selection 0 1 1 0 VOUT6 selection 0 1 1 1 VOUT7 selection 1 0 0 0 VOUT8 selection 1 0 0 1 Don’t care 1 0 1 0 Don’t care 1 0 1 1 Don’t care 1 1 0 0 Don’t care 1 1 0 1 Don’t care 1 1 1 0 Don’t care 1 1 1 1 Don’t care D0 D1 D2 D3 D4 D5 D6 D7 DAC Output 0 0 0 0 0 0 0 0 VDAref 1 0 0 0 0 0 0 0 ( VIN – VDAref ) / 256 x 1+ VDAref 0 1 0 0 0 0 0 0 ( VIN – VDAref ) / 256 x 2 + VDAref 1 1 0 0 0 0 0 0 ( VIN – VDAref ) / 256 x 3 + VDAref : : : : : : : : : 1 1 1 1 1 1 1 1 ( VIN – VDAref ) / 256 x 255 + VDAref DAC data R03DS0021EJ0100 Rev.1.00 2011.09.05 Page 5 of 7 New Product R2A20178NP Timing Chart ( Model ) RESET MSB DI D11 LSB D10 D9 D0 CLK LD Vo Note: Input data is carried out LD signal low besides CLK signal positive edge. CLK, LD is kept generally high level. Ordering Information Order part No. Package Name Package Code Package type No. Packing/Quantity R2A20178NP QFN-24 PWQN0024KD-A NP Embossed Taping/2,500 pcs. R03DS0021EJ0100 Rev.1.00 2011.09.05 Page 6 of 7 R2A20178NP New Product Package Dimensions PWQN0024KD-A R03DS0021EJ0100 Rev.1.00 2011.09.05 Page 7 of 7 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. 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