RENESAS R2A20150NP

New Product
R2A20150NP/SA
8-bit I/O Expander for I2C BUS (Corresponds to Fast mode)
R03DS0012EJ0100
Rev.1.00
2011.09.05
Description
The R2A20150NP/SA is a CMOS 8-bit I/O expander, which has serial to parallel and parallel to serial
data converting functions.
It can communicate with a microcontroller via few wiring thanks to the adoption of the 2-wire I2C BUS.
Maximum 8 ICs can be connected to a bus by using 3-chip select pins, so that it is possible to handle up
to 64 bits data.
Features
 Simple 2-wire (SCL and SDA) communication with a microcontroller.
 8-bit data conversion between serial and parallel by I2C BUS.
 Corresponds to Fast mode (400kHz) of I2C BUS specification.
 Possible to set input and output each bit separately.
 By using three chip select pins (CS0,CS1,CS2), R2A20150 can connect with the same BUS line
to maximum 8 pieces.
 Very small package line-up QFN-16 and TSSOP-16.
Application
I/O port expansion of Microcomputer.
Data conversion from serial to parallel and from parallel to serial in peripheral of Microcomputer.
Block Diagram
SCL
2 16
SDA
3 1
CS0
CS1
CS2
16
14
15
13
14
12
I2C BUS
TRANSCIEVER
8
8
OUTPUT
DATA LATCH
GND
8 6
R03DS0012EJ0100 Rev.1.00
2011.09.05
SO
INPUT
DATA LATCH
8
Reset
POWER ON
RESET
15 1
8
I/O SETTING
DATA LATCH
8
13 11
SHIFT
RESISTOR
Input/Output
Output Data
VDD
Number for TSSOP package
Number for QFN package
8
Input Data
I/O PORT
10
12
9
11
8
10
7
9
5
7
4
6
3
5
2
4
D7
D6
D5
D4
D3
D2
D1
D0
Page 1 of 10
New Product
R2A20150NP/SA
Pin Arrangement
3
D2
4
13 CS1
14 CS0
15 SO
SO 1
SCL 2
12
CS2
11
VDD
10
D7
9
D6
16 CS0
SDA 3
D0 4
D1 5
D2 6
D3 7
15 CS1
14 CS2
13 VDD
12 D7
11 D6
10 D5
GND 8
D5 8
D1
D4 7
2
GND 6
D0
D3 5
1
R2A20150NP
SDA
R2A20150SA (Top view)
R2A20150SA
16 SCL
R2A20150NP (Top view)
9
D4
Package: PTSP0016JB-A [SA]
Package: PWQN0016KB-A [NP]
EXPLANATION OF TERMINALS The pin No. of ( ) are for QFN package
Pin No.
TSSOP
QFN
Symbol
I/O
Function
1
15
SO
Output
Serial data output terminal
2
16
SCL
Input
Serial clock input terminal
3
1
SDA
4
2
D0
5
3
D1
6
4
D2
7
5
D3
9
6
D4
10
7
D5
11
8
D6
12
9
D7
14
10
CS2
15
12
CS1
16
13
CS0
13
14
VDD
-
Power supply terminal
8
11
GND
-
GND terminal
R03DS0012EJ0100 Rev.1.00
2011.09.05
Input/Output Serial data input/output terminal
Input/Output
Parallel data input/output terminal
( Initial state after power on is input mode. )
Chip select data input terminal
Input
This IC accessed only when the lower 3bits data from
Slave address coincide with the data of CS0 to CS2.
Page 2 of 10
New Product
R2A20150NP/SA
Absolute Maximum Ratings
Symbol
VDD
VI
Item
Conditions
Input voltage
VO
Output voltage
Output current “High”
IOL
Output current “Low”
Pd
Ratings
Unit
-0.3 to +6.5
V
-0.3 to VDD+0.3 (<6.5)
V
Supply voltage
IOH
K theta
(Ta= 25 deg unless otherwise noted)
-0.3 to VDD+0.3 (<6.5)
V
-5 to 0
mA
Continuous
0 to +4
mA
Peak
0 to +30
mA
D0 ~ D7
*1
D0 ~ D7
Power dissipation
Ta= +85deg
290(NP) / 150(SA)
mW
Thermal derating factor
Ta> +25deg
7.25(NP) / 3.75(SA)
mW/deg
Topr
Operating temperature range
-30 to +85
deg
Tstg
Storage temperature
-40 to +125
deg
*1 : The maximum ratings of Output current “Low” is 4mA when using continuously for each port, but peak current is
30mA (13% duty) when considering duty cycle including power off period.
Recommended Operating conditions
Symbol
Item
Limits
Conditions
Min
Typ
Unit
Max
VDD
Supply voltage
2.7
5.0
5.5
V
VIH
Input high voltage
0.8VDD
-
VDD
V
VIL
Input low voltage
0
-
0.2VDD
V
Electrical Characteristics
Symbol
Item
Circuit current
IILK
Input leak current
Output low voltage (SDA)
VIH
Input high voltage
VIL
Input low voltage
Output high voltage
(D0 ~ D7)
VOL
Output low voltage
(D0 ~ D7)
trVDD
VDDPOR
tPOR
Typ
Max
-
0.05
0.5
mA
-
0.1
10
µA
-10
0
10
µA
-
-
0.4
V
0.8VDD
-
VDD
V
Isink=3mA
0
-
0.2VDD
V
0.5
0.8
-
V
IOH=-1mA, VDD=5V
VDD – 0.4
-
VDD
IOH=-500µA, VDD=3V
VDD – 0.4
-
VDD
Hysteresis of Schmitt trigger input (SDA, SCL)
VOH
Output current “Low”
(D0 ~ D7)
*2
Unit
Min
VIH=VDD, VIL=GND, fSCL=STOP
VOL
IOL
Limits
Conditions
VIH=VDD, VIL=GND, fSCL=400kHz
IDD
Vhys
(VDD = +5V +/-10%, GND=0V, Ta= -30 to +85deg unless otherwise noted)
IOL=5mA, VDD=5V
0
-
0.4
IOL=2.5mA, VDD=3V
0
-
0.4
VOL=0.4V, VDD=5V
5
10
-
VOL=0.4V, VDD=3V
2.5
5
-
VOL=1.0V, VDD=5V
15
25
-
VOL=1.0V, VDD=3V
5
10
-
V
V
mA
Supply voltage rise-up time *3
VDD=0 to 2.7V
100
-
-
µs
Operating voltage of internal reset *3
VDD=0 to 2.7V
-
1.5
1.9
V
Time period of re-power on
(Power supply OFF  ON) *3
VDD < 0.1V
1
-
-
ms
*2 : Output low current should be set; average current of summary of D0 to D3 or D4 to D7 < 16mA.
Average current is calculate by below equation;
Average current = IOL X duty duty : The period of flow IOL (Include power off period)
*3 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on
quickly, initialize is not operate. So, keep the time period of re-powered on (tPOR).
trVDD
VDD
tPOR
(equivalent to trVDD)
VDDPOR
GND
Internal
Reset signal
< 0.1V
GND
Resetting period
R03DS0012EJ0100 Rev.1.00
2011.09.05
Resetting period
Page 3 of 10
New Product
R2A20150NP/SA
I2C BUS Characteristics
Item
Symbol
SCL clock frequency
Free time: the bus must be free before a new
transmission can start
Hold time START condition after this period, the first
Clock pulse is generated
Low period of the clock
High period of the clock
Set-up time for START condition.
Only relevant for a repeated START condition.
Data Hold time
Data Set-up time
Rise time of SDA and SCL signals
fSCL
Fall time of SDA and SCL signals
Set-up time for STOP condition
Capacitive load of bus line
Normal mode
Min.
Max.
100
0
Fast mode
Min.
Max.
0
400
Unit
kHz
tBUF
4.7
-
1.3
-
µs
tHD:STA
4.0
-
0.6
-
µs
tLOW
tHIGH
4.7
4.0
-
1.3
0.6
-
µs
µs
tSU:STA
4.7
-
0.6
-
µs
tHD:DAT
tSU:DAT
tR
0
250
-
3.45
1000
0
100
-
0.9
300
µs
ns
ns
tF
-
300
-
300
ns
tSU:STO
Cb
4.0
-
400
0.6
-
400
µs
pF
All of above value are corresponds to VIHmin and VILmax.
Timing Chart
tR, tF
tBUF
VIH
SDA
VIL
tHD:STA
tSU:DAT
tHD:DAT
tsu:STA
tSU:ST0
VIH
SCL
VIL
tLOW
Start
R03DS0012EJ0100 Rev.1.00
2011.09.05
tHIGH
Start
Stop
Start
Page 4 of 10
R2A20150NP/SA
New Product
Functional Blocks
 I2C BUS Interface
The I2C BUS interface recognizes start/stop conditions, a slave address and a write/read mode selection
by receiving SDA,SCL,CS0,CS1 and CS2 signals and then the latch pulse, dedicated to each data latch
are generated.
 Data Latch
This IC has 3 types of data latch: the I/O setting data latch, the input data latch and the output data latch
and each latch is controlled by the I2C BUS interface.
 I/O setting data latch
These latches set input-state or output-state of each parallel data terminals (D0 to D7). They are
set at the next byte after receiving the slave address byte in the write mode from the master.
In case this latch is set to high, the data is transferred from the I2C BUS interface to the parallel
data terminals. In the opposite transmission: from the parallel data terminals to the I2C BUS,
it is set to low.
 Output data latch
In the write mode, the data from the I2C BUS to the parallel data terminals is latched.
When the master transmits output data after a setting in write mode, the output data is taken into
the latch.
 Input data latch
In the read mode, the data of parallel data terminals is latched in the input data latches. The input
data is taken into the latches from the parallel data terminals on every 8th negative edge of SCL clock.
The latched data is output to the master through the sift resistor. On the output terminal assigned by
the I/O setting latch, the input data latch takes the state of the output terminal.
 Parallel Input/Output Port
In case I/O setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance
and is able to accept an input. In another case I/O setting latch is set to high (output mode), each parallel
terminal output a data according to the state of the output data latch.
 Serial Output Port
The parallel data from each parallel terminal are conversion to 8bit serial data and output to SO terminal.
Without serial output mode, SO terminal goes to low output.
 Power on Reset
When the power is turned on, each latch is reset (initialize) and then the parallel data I/O terminals
become hi-impedance (input mode).
R03DS0012EJ0100 Rev.1.00
2011.09.05
Page 5 of 10
New Product
R2A20150NP/SA
Digital Data Format
1.Write mode: I2C BUS data input to parallel data output
(The data transmits continuously each 8bits after setting slave address and I/O.)
FIRST
S
LAST
Slave address
W
A
I/O setting
A
A
8bit data
A
8bit data
A
P
2.Read mode: Parallel data input to I2C BUS data output)
(The data transmits continuously each 8bits after setting slave address. When final data transmitted,
do not return the acknowledge, then input the stop condition.)
FIRST
S
LAST
Slave address
R A
A
8bit data
8bit data
A
A
8bit data
A
P
Transmission from Master (MCU etc.) to Slave (R2A20150)
Transmission from Slave (R2A20150) to Master (MCU etc.)
 S: Start condition
While SCL level is high, SDA line level should be changed from high to low.
Chip select data
 Slave address
MSB
FIRST
LAST
MSB
0
LSB
A2
A1
A0
CS2
CS1
CS0
0
0
0
L
L
L
0
0
1
L
L
H
0
1
0
L
H
L
LSB
1
1
1
A2 A1 A0
1
H
H
…
1
…
…
1
…
…
 W: Write (SDA = Low), R: Read (SDA = High)
…
Note: Lower three bits (A0, A1, A2) are a programmable address.
This IC is accessed only when the lower 3 bits data of slave
address coincide with the data of CSO to CS2. (refer to the right table)
H
(L=Low,H=High)
 A: Acknowledge bit
(Slave side confirm the data receive, change to Low in the SDA line)
*A: IN a read mode; after final data transmitted, do not return acknowledge. Change to High.)
 I/O setting data (I/O setting of parallel data I/O terminals.)
FIRST
MSB
LAST
LSB
P7 P6 P5 P4 P3 P2 P1 P0
Note: DATA INPUT from parallel data terminals = Low
DATA OUTPUT to parallel data terminals = High
Each bit data corresponds to the I/O state of the parallel data terminals.
 8-bit data
FIRST
MSB
LAST
LSB
D7 D6 D5 D4 D3 D2 D1 D0
 P: Stop condition
While SCL level is high, SDA level should be changed from low to high.
R03DS0012EJ0100 Rev.1.00
2011.09.05
Page 6 of 10
New Product
R2A20150NP/SA
FUNCTIONAL DESCRIPTION
All parallel data I/O terminals are set to the input-state after power-on. In case any terminals need to be
set to the output state, the corresponding terminals should be set during the write mode.
This setting is hold until a next setting.
In the write mode, 8 bits data can be transmitted from the I2C BUS interface to the parallel ports continually
After the slave address and I/O setting.
In the read mode, 8 bits data can be transmitted from the parallel ports to the I2C BUS interface continually
After the slave address setting. This 8 bits serial data is output from the SO terminal. SO terminal sets
to “L” state without read mode.
In the case of a changing between the write- and read-mode, the data must be transmitted again from the
Starting condition.
Transmission from a master (MCU etc.)
In a case of a data conversion from serial to parallel
Transmission from a slave (R2A20150)
Start
condition Slave address
SDA
0
SCL
1
1
1
2
1
3
A2
4
I/O setting byte
A1 A0
5
6
7
0
A
8
DATA
P7 P6 P5 P4 P3 P2 P1 P0
1
2
3
4
5
6
7
A
Stop
condition
DATA
D17 D16 D15 D14 D13 D12 D11 D10 A
D27 D26 D25 D24 D23 D22 D21 D20 A
8
Data output
D0
to
D7
Data output
D 1X
Hi-Z
D 2X
In a case of a data conversion from parallel to serial
All I/O setting resistors are set to low (input) in the write mode, before a parallel data is read.
(All I/O setting resistors are set to the input mode after power-on.)
Start
condition
Slave address
Transmission from a master (MCU etc.)
I/O setting byte
Transmission from a slave (R2A20150)
SDA
0
SCL
1
1
D0 to D7
output
SCL
2
1
3
A2
4
5
A1 A0
6
0
7
8
P7 P6 P5 P4 P3 P2 P1 P0
1
2
3
4
5
6
7
A
8
0
1 1 1
1
2
3
A2 A1 A0
4
5
6
Stop
condition
DATA
Slave address
7
1
DATA
A D17 D16 D15 D14 D13 D12 D11 D10 A
8
1
SO
2
3
4
5
6
7
D 1X
D 2X
Data latch
DATA
D37 D36 D35 D34 D33 D32 D31 D30 A D47 D46 D45 D44 D43 D42 D41 D40 A
8
D17 D16 D15 D14 D13 D12 D11 D10
D0 to D7
Input
(example)
D0 to D7
output
A
Hi-Z
Start
condition
SDA
1
D37 D36 D35 D34 D33 D32 D31 D30
D 3X
Data latch
D47 D46 D45 D44 D43 D42 D41 D40
D 4X
Data latch
Hi-Z
R03DS0012EJ0100 Rev.1.00
2011.09.05
Page 7 of 10
New Product
R2A20150NP/SA
In case the I/O setting is different between each terminals.
An example : the parallel port terminals of D0 to D3 and D4 to D7 are assigned as output and
input terminals, respectively.
Start
condition
SDA
Slave address
0
1
1
2
3
1
A2
I/O setting byte
A1 A0 0
A
P7 P6 P5 P4
DATA
P3 P2 P1 P0
Stop
condition
DATA
A D17 D16 D15 D14 D13 D12 D11 D10 A
D27 D26 D25 D24 D23 D22 D21 D20 A
SCL
1
4
5
6
7
8
1
2
3
4
5
6
7
8
Data output
D0 to
D3
D 2X
Hi-Z
Start
condition
SDA
D 1X
Hi-Z
D4 to
D7
Data output
0
Slave address
1
1
2
3
1
DATA
A2 A1 A0
1
DATA
Stop
condition
DATA
A D17 D16 D15 D14 D13 D12 D11 D10 A D37 D36 D35 D34 D33 D32 D31 D30 A D47 D46 D45 D44 D43 D42 D41 D40 A
SCL
1
4
5
6
SO
7
8
1
2
3
4
5
6
7
8
D17 D16 D15 D14 D13 D12 D11 D10
D37 D36 D35 D34 D33 D32 D31 D30
D47 D46 D45 D44 D43 D42 D41 D40
D0 to D3
D4 to D7
(instance)
D 1X
D 2X
Data latch
D4 to D7
output
D 3X
Data latch
D 4X
Data latch
Hi-Z
* Write mode
The terminal assigned as an output provides the data written in the output data latch.
After power-on, all terminals are reset to the input-state. Then an initial data low of the output latch are
output after the I/O setting has been done. Finally the assigned output are provided after the 8-bit data
transmission.
Then terminal assigned as an input keeps the input condition (High-impedance) regardless of 8-bit data
setting.
* Read mode
The input data is taken into input latch on every 8th negative-going edge of the SCL clock through the
terminal assigned as an input, and then the latched data is output via the SDA line.
The data of the output assigned terminal is also handled in the same procedures as above.
R03DS0012EJ0100 Rev.1.00
2011.09.05
Page 8 of 10
New Product
R2A20150NP/SA
TYPICAL APPLICATION
10F
13
11
VDD
14 12 CS2
Chip select data
15 13 CS1
16 14 CS0
D0 2
4
D1 3
5
D2 4
6
D3 5
7
D4 7
9
Parallel input/
Output terminal
D5 8 10
2 16 SCL
MCU
D6
9 11
D7
10 12
3 1 SDA
GND
SO 15 1
Serial data output
6
8
Number for TSSOP package
Number for QFN package
Ordering Information
Order part No.
Package Name
Package Code
Package type No.
Packing/Quantity
R2A20150SA
TSSOP-16
PTSP0016JB-A
SA
Embossed Taping/2,000 pcs.
R2A20150NP
QFN-16
PWQN0016KB-A
NP
Embossed Taping/3,000 pcs.
R03DS0012EJ0100 Rev.1.00
2011.09.05
Page 9 of 10
R2A20150NP/SA
New Product
Package outline
SA: PTSP0016JB-A
NP: PWQN0016KB-A
R03DS0012EJ0100 Rev.1.00
2011.09.05
Page 10 of 10
Notice
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SALES OFFICES
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
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