19-4789; Rev 0; 10/98 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC Features ♦ Exceeds ANSI, ITU, and Bellcore SONET/SDH Regenerator Specifications This device operates from a single +3.3V to +5.0V supply over a -40°C to +85°C temperature range. The typical power consumption is only 400mW with a +3.3V supply. It is available in a 32-pin TQFP package, as well as in die form. ♦ Differential PECL-Compatible Data and Clock Outputs ♦ 400mW Power Dissipation (at +3.3V) ♦ Clock Jitter Generation: 0.003UIRMS ♦ Single +3.3V or +5V Power Supply ♦ Fully Integrated Clock Recovery and Data Retiming ♦ Additional High-Speed Input Facilitates System Loopback Diagnostic Testing ♦ Tolerates >2000 Consecutive Identical Digits ♦ Loss-of-Lock Indicator Ordering Information Applications SDH/SONET Receivers and Regenerators TEMP. RANGE PIN-PACKAGE MAX3875EHJ PART -40°C to +85°C 32 TQFP Add/Drop Multiplexers MAX3875E/D -40°C to +85°C Dice* Digital Cross-Connects * Dice are designed to operate over this range, but are tested and guaranteed at TA = +25°C only. Contact factory for availability. 2.488Gbps ATM Receiver Digital Video Transmission Pin Configuration appears at end of data sheet. SDH/SONET Test Equipment Typical Application Circuit +3.3V +3.3V 0.01µF PHOTODIODE TTL 0.01µF +3.3V VCC VCC MAX3866 OUT+ PHADJ+ PHADJ- LOL SDI+ PRE/POSTAMPLIFIER OUT- SDI- SYSTEM LOOPBACK TTL 82Ω 82Ω +3.3V MAX3885 130Ω 130Ω 82Ω 82Ω 1:16 DESERIALIZER SCLKO+ SCLKO- SLBI+ SIS 130Ω MAX3875 SLBI- TTL 130Ω SDO+ SDO- IN LOP +3.3V FIL+ FIL- 1µF ____________________________________________________________ Maxim Integrated Products 12-91 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3875 General Description The MAX3875 is a compact, low-power clock recovery and data retiming IC for 2.488Gbps SDH/SONET applications. The fully integrated phase-locked loop recovers a synchronous clock signal from the serial NRZ data input, which is retimed by the recovered clock. Differential PECL-compatible outputs are provided for both clock and data signals, and an additional 2.488Gbps serial input is available for system loopback diagnostic testing. The device also includes a TTLcompatible loss-of-lock (LOL) monitor. The MAX3875 is designed for both section-regenerator and terminal-receiver applications in OC-48/STM-16 transmission systems. Its jitter performance exceeds all of the SONET/SDH specifications. MAX3875 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC..............................................-0.5V to +7.0V Input Voltage Levels (SDI+, SDI-, SLBI+, SLBI-) ...........(VCC - 0.5V) to (VCC + 0.5V) Input Current Levels (SDI+, SDI-, SLBI+, SLBI-)..............±10mA PECL Output Voltage (SDO+, SDO-, SCLKO+, SCLKO-) .......................(VCC + 0.5V) PECL Output Current, (SDO+, SDO-, SCLKO+, SCLKO-).....56mA Voltage at LOL, SIS, PHADJ+, PHADJ-, FIL+, FIL- .................................................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85°C) TQFP (derate 16.1mW/°C above +85°C) ........................1.0W Operating Temperature Range MAX3875EHJ..................................................-40°C to +85°C Operating Junction Temperature (die) ..............-55°C to +150°C Storage Temperature Range .............................-60°C to +160°C Processing Temperature (die) .........................................+400°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS Supply Current ICC Excluding PECL output termination Differential Input Voltage (SDI±, SLBI±) VID Figure 1 Single-Ended Input Voltage (SDI±, SLBI±) VIS Input Termination to VCC (SDI±, SLBI±) RIN PECL Output High Voltage (SDO±, SCLKO±) VOH PECL Output Low Voltage (SDO±, SCLKO±) VOL TTL Input High Voltage (SIS) VIH TTL Input Low Voltage (SIS) VIL VOH TTL Output Low Voltage (LOL) VOL TYP MAX UNITS 122 167 mA 800 mVp-p 50 VCC - 0.4 VCC + 0.2 TA = 0°C to +85°C VCC - 1.025 VCC - 0.88 TA = -40°C VCC - 1.085 VCC - 0.88 TA = 0°C to +85°C VCC - 1.81 VCC - 1.62 TA = -40°C VCC - 1.83 VCC - 1.555 2.0 V -10 +10 µA 2.4 VCC V 0.4 V 25mV MIN 400mV MAX SCLKO+ (SDI+) (SDI-) VID tCK-Q 50mVp-p MIN 800mVp-p MAX SDO Figure 1. Input Amplitude 12-92 V V tCK SDI- V 0.8 Note 1: Dice are tested at TA = +25°C only. SDI+ V Ω 45 TTL Input Current (SIS) TTL Output High Voltage (LOL) MIN Figure 2. Output Clock-to-Q Delay ___________________________________________________________________________________ 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC (VCC = +3.0V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at +3.3V and TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN Serial Output Clock Rate TYP MAX 2.488 Clock-to-Q Delay Figure 2 Jitter Peaking f ≤ 2MHz JP Jitter Transfer Bandwidth 110 JBW Jitter Tolerance Jitter Generation JGEN 1.1 f = 70kHz 1.91 3.6 f = 100kHz 1.76 2.75 f = 1MHz 0.41 0.67 f = 10MHz (Note 3) 0.21 Jitter BW = 12kHz to 20MHz UNITS Gbps 290 ps 0.1 dB 2.0 MHz UIp-p 0.45 0.003 0.006 UIRMS 0.026 0.056 UIp-p Clock Output Edge Speed 20% to 80% 70 ps Data Output Edge Speed 20% to 80% 108 ps 2000 Bits Tolerated Consecutive Identical Digits Input Return Loss (SDI±, SLBI±) 100kHz to 2.5GHz -17 2.5GHz to 4.0GHz -15 dB Note 2: AC characteristics are guaranteed by design and characterization. Note 3: See Typical Operating Characteristics for worst-case distribution. Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) RECOVERED DATA AND CLOCK (DIFFERENTIAL OUTPUT) JITTER TOLERANCE RECOVERED CLOCK JITTER MAX3875 toc02 PRBS = 215 - 1 VIN = 20mVP-P TA = +85°C DATA INPUT JITTER (UIp-p) 223 - 1 PATTERN MAX3875 toc03 10 MAX3875 toc01 1 BELLCORE MASK CLOCK RMS∆ = 1.2ps 0.1 100ps/div 10ps/div PRBS = 223 - 1 50mVp-p INPUT 10k 100k 1M 10M JITTER FREQUENCY (Hz) ____________________________________________________________________________________ 12-93 MAX3875 AC ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (continued) (VCC = +3.3V, TA = +25°C, unless otherwise noted.) JITTER FREQUENCY = 5MHz 0.3 fJITTER = 10MHz VCC = +3.0V TA = -40°C 20 15 10 0 -0.3 -0.6 -1.2 -1.5 -1.8 -2.1 -2.4 5 -2.7 PRBS = 223 - 1 100 10 0.20 1000 0.34 0.48 1k 0.62 10k 10M 140 SUPPLY CURRENT (mA) 10-5 10-6 10-7 10-8 MAX3875toc07 145 MAX3875toc06 10-4 1M SUPPLY CURRENT vs. TEMPERATURE BIT ERROR RATE vs. INPUT VOLTAGE 10-3 100k JITTER FREQUENCY (Hz) JITTER TOLERANCE (UIp-p) INPUT VOLTAGE (mVp-p) BIT ERROR RATE PRBS = 223 - 1 -3.0 0 0 1 BELLCORE MASK -0.9 0.2 0.1 MAX3875 toc05 MAX3875toc05a 0.3 JITTER TRANSFER (dB) 0.5 MEAN = 0.41 σ = 0.028 25 PERCENT OF UNITS (%) 0.6 0.4 30 MAX3875toc04 JITTER FREQUENCY = 1MHz 0.7 JITTER TRANSFER DISTRIBUTION OF JITTER TOLERANCE JITTER TOLERANCE vs. INPUT VOLTAGE 0.8 JITTER TOLERANCE (UIp-p) MAX3875 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC 135 VCC = +5.0V 130 125 VCC = +3.3V 120 115 10-9 110 PRBS = 223 - 1 10-10 105 6.0 6.1 6.2 6.3 6.4 6.5 -50 6.6 -25 0 25 50 75 100 AMBIENT TEMPERATURE (°C) INPUT VOLTAGE (mVp-p) Pin Description PIN NAME 1, 2, 8, 9, 10, 16, 26, 29, 32 FUNCTION GND Supply Ground 3, 6, 11, 14, 15, 17, 20, 21, 24 VCC Positive Supply Voltage 4 SDI+ Positive Data Input. 2.488Gbps serial data stream. 5 SDI- Negative Data Input. 2.488Gbps serial data stream. Signal Input Selection, TTL. Low for normal data input. High for system loopback input. 7 SIS 12 SLBI+ Positive System Loopback Input. 2.488Gbps serial data stream. 13 SLBI- Negative System Loopback Input. 2.488Gbps serial data stream. 18 SCLKO- 12-94 Negative Serial Clock Output, PECL, 2.488GHz. SDO- is clocked out on the falling edge of SCLKO-. ___________________________________________________________________________________ 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC PIN NAME 19 SCLKO+ FUNCTION Positive Serial Clock Output, PECL, 2.488GHz. SDO+ is clocked out on the rising edge of SCLKO+. 22 SDO- Negative Data Output, PECL compatible, 2.488Gbps 23 SDO+ Positive Data Output, PECL compatible, 2.488Gbps 25 LOL 27 PHADJ- Negative Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. 28 PHADJ+ Positive Phase-Adjust Input. Used to optimally align internal PLL phase. Connect to VCC if not used. 30 FIL- Negative Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. 31 FIL+ Positive Filter Input. PLL loop filter connection. Connect a 1.0µF capacitor between FIL+ and FIL-. Loss-of-Lock Output, TTL, PLL loss-of-lock monitor, active low (internal 10kΩ pull-up resistor) SIS PHADJ+ PHADJ- FIL+ FIL- SDO+ D SDI+ Q CML CK AMP SDO- SDIMUX PHASE AND FREQUENCY DETECTOR SLBI+ LOOP FILTER I VCO SCLKO+ Q CML SCLKO- AMP SLBILOL MAX3875 TTL Figure 3. Functional Diagram Detailed Description The MAX3875 consists of a fully integrated phaselocked loop (PLL), input amplifier, data retiming block, and PECL output buffer (Figure 3). The PLL consists of a phase/frequency detector (PFD), a loop filter, and a voltage-controlled oscillator (VCO). This device is designed to deliver the best combination of jitter performance and power dissipation by using a fully differential signal architecture and low-noise design techniques. Input Amplifier Input amplifiers are implemented for both the main data and system loopback inputs. These amplifiers accept a differential input amplitude from 50mVp-p up to 800mVp-p. The bit error rate is better than 1 · 10-10 for input signals as small as 10mVp-p, although the jitter tolerance performance will be degraded. For interfacing with PECL signal levels, see Applications Information. Phase Detector The phase detector incorporated in the MAX3875 produces a voltage proportional to the phase difference between the incoming data and the internal clock. Because of its feedback nature, the PLL drives the error voltage to zero, aligning the recovered clock to the center of the incoming data eye for retiming. The external phase adjust pins (PHADJ+, PHADJ-) allow the user to vary the internal phase alignment. ____________________________________________________________________________________ 12-95 MAX3875 Pin Description (continued) Frequency Detector The digital frequency detector (FD) aids frequency acquisition during start-up conditions. The frequency difference between the received data and the VCO clock is derived by sampling the in-phase and quadrature VCO outputs on both edges of the data input signal. Depending on the polarity of the frequency difference, the FD drives the VCO until the frequency difference is reduced to zero. Once frequency acquisition is complete, the FD returns to a neutral state. False locking is completely eliminated by this digital frequency detector. CF = 1.0µF fZ = 2.6kHz CF = 0.1µF fZ = 26kHz f (kHz) 1 1000 100 10 Loop Filter and VCO The phase detector and frequency detector outputs are summed into the loop filter. An external capacitor, CF, is required to set the PLL damping ratio. Refer to Design Procedure for guidelines on selecting this capacitor. The loop filter output controls the on-chip LC VCO running at 2.488GHz. The VCO provides low phase noise and is trimmed to the correct frequency. Clock jitter generation is typically 1.2psRMS within a jitter bandwidth of 12kHz to 20MHz. Figure 4. Open-Loop Transfer Function H(j2πf) (dB) CF = 0.1µF Loss-of-Lock Monitor A loss-of-lock (LOL) monitor is incorporated in the MAX3875 frequency detector. A loss-of-lock condition is signaled immediately with a TTL low. When the PLL is frequency locked, LOL switches to TTL high in approximately 800ns. Note that the LOL monitor is only valid when a data stream is present on the inputs to the MAX3875. As a result, LOL does not detect a loss-of-power condition resulting from a loss of the incoming signal. Design Procedure Setting the Loop Filter The MAX3875 is designed for both regenerator and receiver applications. Its fully integrated PLL is a classic second-order feedback system, with a loop bandwidth (fL) fixed at 1.1MHz. The external capacitor, CF, can be adjusted to set the loop damping. Figures 4 and 5 show the open-loop and closed-loop transfer functions. The PLL zero frequency, fZ, is a function of external capacitor CF, and can be approximated according to: fz = 12-96 1 2π 60 CF ( ) 0 CLOSED-LOOP GAIN MAX3875 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC -3 CF = 1.0µF f (kHz) 1 10 100 1000 Figure 5. Closed-Loop Transfer Function For an overdamped system (fZ/fL) < 0.25, the jitter peaking (MP) of a second-order system can be approximated by: f MP = 20log 1+ Z fL For example, using CF = 0.1µF results in a jitter peaking of 0.2dB. Reducing CF below 0.01µF may result in PLL instability. The recommended value for CF = 1.0µF to guarantee a maximum jitter peaking of less than 0.1dB. CF must be a low TC, high-quality capacitor of type X7R or better. ___________________________________________________________________________________ 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC System Loopback The MAX3875 is designed to allow system loopback testing. The user can connect a serializer output in a transceiver directly to the SLBI+ and SLBI- inputs of the MAX3875 for system diagnostics. To select the SLBI± inputs, apply a TTL logic high to the SIS pin. Jitter Tolerance and Input Sensitivity Trade-Offs When the received data amplitude is higher than 50mVp-p, the MAX3875 provides a typical jitter tolerance of 0.45UI at jitter frequencies greater than 10MHz. The SDH/SONET jitter tolerance specification is 0.15UI, leaving a jitter allowance of 0.3UI for receiver preamplifier and postamplifier design. The BER is better than 1 · 10-10 for input signals greater than 10mVp-p. At 10mVp-p, jitter tolerance will be degraded, but will still be above the SDH/SONET requirement. The user can make a trade-off between jitter tolerance and input sensitivity according to the specific application. Refer to the Typical Operating Characteristics for Jitter Tolerance and BER vs. Input Amplitude graphs. PECL Input Levels When interfacing with differential PECL input levels, it is important to attenuate the signal while still maintaining 50Ω termination (Figure 6). AC coupling is also required to maintain the input common-mode level. Layout The MAX3875’s performance can be significantly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductance and using fixed-impedance transmission lines on the data and clock signals. Power-supply decoupling should be placed as close to VCC as possible. Take care to isolate the input from the output signals to reduce feedthrough. VCC Applications Information 50Ω Consecutive Identical Digits (CID) The MAX3875 has a low phase and frequency drift in the absence of data transitions. As a result, long runs of consecutive zeros and ones can be tolerated while maintaining a BER of 1 · 10-10. The CID tolerance is tested using a 213 - 1 PRBS, substituting a long run of zeros to simulate the worst case. A CID tolerance of 2000 bits is typical. 0.1µF 25Ω PECL LEVELS 50Ω SDI+ 100Ω 0.1µF 25Ω SDI- Phase Adjust The internal clock is aligned to the center of the data eye. For specific applications this sampling position can be shifted using the PHADJ inputs to optimize BER performance. The PHADJ inputs operate with differential input voltages up to ±1.5V. A simple resistor-divider with a bypass capacitor is sufficient to set these levels. When the PHADJ inputs are not used, they should be tied directly to VCC. MAX3875 Figure 6. PECL Input Interface ____________________________________________________________________________________ 12-97 MAX3875 Input and Output Terminations The MAX3875’s digital outputs (SDO+, SDO-, SCLKO+, SCLKO-) are designed to interface with PECL signal levels. It is important to bias these ports appropriately. A circuit that provides a Thevenin equivalent of 50Ω to VCC - 2V can be used with fixed impedance transmission lines for proper termination. To ensure best performance, the differential outputs must have balanced loads. The input termination can be driven differentially, or can be driven single-ended by externally biasing SDI- or SLBI- to the center of the voltage swing. Pin Configuration Chip Topography FIL+ GND FIL+ FIL- GND PHADJ+ PHADJ- GND LOL TOP VIEW 32 31 30 29 28 27 26 25 GND PHADJ- LOL FIL- PHADJ+ GND GND VCC GND 1 24 VCC GND GND 2 23 SDO+ GND VCC 3 22 SDO- SDI+ 4 21 VCC SDI- 5 VCC 6 19 SCLKO+ SIS 7 18 SCLKO- GND 8 17 VCC SDO+ SDO- VCC VCC 0.072" VCC (1.828mm) SCLKO+ SDI+ 13 14 15 16 VCC GND VCC 12 VCC 11 SLBI- 10 20 VCC SLBI+ 9 GND MAX3875 GND TQFP SDIVCC SCLKO- SIS VCC GND GND GND SLBI+ VCC VCC VCC SLBI- N.C. N.C. 0.071" (1.803mm) TRANSISTOR COUNT: 1515 ________________________________________________________Package Information 32L,TQFP.EP MAX3875 2.5Gbps, Low-Power, +3.3V Clock Recovery and Data Retiming IC Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12-98 _________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.