MP6902 - Monolithic Power Systems

AN077
MP6902
Synchronous Rectification Controller
The Future of Analog IC Technology
MP6902
Synchronous Rectification Controller
Application Note
Prepared by Lei Miao
April 10th, 2013
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AN077
MP6902
Synchronous Rectification Controller
The Future of Analog IC Technology
ABSTRACT
This document will explain the operation principle and present the design procedure of MP6902 in
detail.
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
INDEX
MP6902 Introduction.............................................................................................................................. 4
Driving Method and Operation Logic...................................................................................................... 4
Turn On Phase (t1).......................................................................................................................... 4
Conduction Phase (t1 - t4) ............................................................................................................... 4
Turn Off Phase (t4 - t5) .................................................................................................................... 4
Power Saving Mode at Light Load .................................................................................................. 5
COMPONENTS SELECTION AND DESIGN GUIDE ............................................................................. 6
Components Design Procedure ...................................................................................................... 6
SR Driver Design Guide during System Transient .......................................................................... 7
RC Snubber Design Guide ............................................................................................................. 9
a. Choose proper CS ....................................................................................................................... 9
b. Choose proper RS ..................................................................................................................... 11
c. How to determine CP and LS...................................................................................................... 12
d. Design Example for an optimized RC snubber network ............................................................ 13
SR Design Guide in CCM Flyback Application.............................................................................. 15
CCM Flyback SR Design Example with MP6902 .......................................................................... 20
LAYOUT CONSIDERATIONS ............................................................................................................. 23
Sensing for VD/VSS ........................................................................................................................ 23
VDD Decoupling Capacitor ............................................................................................................. 24
Gate Driver Loop .......................................................................................................................... 24
Layout Example ............................................................................................................................ 24
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
MP6902 INTRODUCTION
MP6902 is a synchronous rectification controller designed for Flyback converters. By driving N-Channel
MOSFET on the secondary side of an isolate/non-isolate Flyback converter, higher efficiency is
achieved compared with traditional schottky diode rectification. This IC regulates the forward voltage
drop of the MOSFET at ~70mV and switches it off as soon as the drain-source voltage of the rectifier
becomes negative. At no/light load condition, the IC turns off the driver signal to save the driving loss.
Figure 1 ― Typical Application for MP6902 in Flyback Converter
DRIVING METHOD AND OPERATION LOGIC
Figure 1 shows the typical application circuit of a Flyback converter with MP6902. The IC senses the
drain-source voltage of the rectifier and compares it with internal turn-on threshold (-70mV) and turn-off
threshold (-30mV) to determine the on/off timing for the SR (Synchronous Rectification) FET, see figure
2:
Turn On Phase (t1)
When the switching current initiates in the SR FET, body-diode conducts which generates a voltage
drop much higher than the turn-on threshold (-70mV) of the IC, this will trigger the driver turns on the
MOSFET.
At the beginning of SR FET’s turn-on, switching current will transfer through the Rds(ON) and lead to the
drain-source voltage drop rises, during which some oscillation will occur on VDS lead by the parasitic
parameters (after t1), in order to prevent the VDS ringing from triggering the driver turns off the SR FET,
a turn on blanking time (~1.6μs) is applied in MP6902, during which the turn-off threshold of the driver
will be increased to a fairly high level so that the voltage ringing on VDS won’t trigger it
Conduction Phase (t1 - t4)
As the drain-source voltage VDS (IDS x Rds(ON)) change with the switching current, when the switching
current drops to the level which makes VDS above -70mV (turn-on threshold) at t3, the IC stops pulling
up the gate driver which makes the driver voltage VGS of the SR FET drops, hence the Rds(ON) of SR
FET increases and the voltage drop VDS is adjusted at ~-70mV.
Turn Off Phase (t4 - t5)
When switching current keeps dropping to the level which make VDS trigger the turn-off threshold (30mV), gate driver is turned off by the internal fast turn-off comparator. Once the SR FET is turned off,
the switching current will flow through the body diode and lead to VDS trigger the turn-on threshold (70mV) again, in order to avoid the gate driver re-turn on, a turn off blanking time is applied and force
the gate driver’s off state lasts for at least ~200ns.
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Figure 2 ― Operation for MP6902 in Flyback Converter
In figure 2, from t1 to t2 is the turn on blanking time which to prevent the VDS ringing affect; from t3 to t4,
gate voltage stops be pulled up by the driver, which begins to drop when VDS rises higher than -70mV;
at t4 VDS triggers -30mV turn off threshold, gate driver is fast pulled down; from t5 to t6, turn off blanking
time forces gate driver remains turn off.
Power Saving Mode at Light Load
When the system is running with light load, rectifier conduction loss no longer dominates the
secondary-side power loss, in which condition it is preferred the SR FET keeps off to save the driver
loss.
MP6902 senses the secondary rectifier conduction duration tON each cycle, when tON keeps smaller
than the internal light load timing tLL (typical 2.2μs, programmable on LL pin) for more than ~100us, the
IC will shutdown the gate driver and keeps it off until tON has increased to tLL+tLL_H (tLL_H is the light load
timing hysteresis, typical 0.2μs). Figure 3 and figure 4 show the procedure of MP6902 enter/exit light
load mode.
SR Gate
Normal mode
Light load mode
100us
tLL
tLL
tLL
Load become light
Switching current
Figure 3 ― MP6902 Enters Light Load Mode
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Figure 4 ― MP6902 Exits Light Load Mode
COMPONENTS SELECTION AND DESIGN GUIDE
Components Design Procedure
From figure 1, the external components recommended for MP6902 in Flyback converter are:
z R3, series resistor in VD sensing line, typical 1kΩ to protect VD pin from excessive current flows
into it when pin voltage goes below -0.7V (SR FET’s body diode conduction). Too large value of
this resistor may delay the turn-on/off timing of the driver due to the parasitic capacitance on VD
pin.
z R4, gate driver resistor for SR FET. An anti-parallel diode may be required when fast turn off speed
of the gate is preferred.
z R5 and C5, LL pin resistor and capacitor used to program the light load timing tLL, C5 is typically
1nF used to decouple the noise, R5 is selected from 30kΩ to 300kΩ to set the light load timing tLL
as following:
R5(kΩ)
⋅ 2.2μs
tLL =
(1)
100kΩ
C4, decouple capacitor for IC’s power supply, typical no smaller than 1μF
EN pin of the IC is internal pulled up by the regulator from VDD with a ~15μA current source. Leave
this pin open if unused. When use external signal to control EN, it is highly recommended the pull
down current be larger than 15uA to make sure the EN pin can be pulled to low.
z R2 and D2, series resistor and diode from auxiliary winding which used as the power supply of IC.
The VDD power voltage can be derived from:
N
VDD = au ⋅ VOUT
(2)
Ns
Where Ns and Nau are the turn counts for secondary and auxiliary winding, VOUT is the system output
voltage.
z
z
When secondary rectifier is put on low-side, the power supply of MP6902 can be derived directly from
output voltage.
Figure 5 shows another non-auxiliary winding power solution for MP6902, R2, R6, D3, Q3 forms an
external LDO circuit, in which D3 provides the output clamp of the LDO, R6 (typical <1kΩ) limits the
LDO current, while R2 provides the turn on signal for Q3, which can be selected as several tens kΩ.
The D2 can also be connect to system output voltage (VOUT+) instead of transformer winding, when
the LDO output is not high enough to power the VDD.
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Figure 5 ― Non-auxiliary Winding Power Solution for MP6902
SR Driver Design Guide during System Transient
When the Flyback system is working during start-up, shutdown and OCP/Short, the SR driver IC may
be turned off due to insufficient power supply lead by the system output drop out. In this case, the
switching current will flow through the body diode of the SR FET, if the reverse recovery time of the
body-diode is not as short as a Schottky, fairly large reverse current and voltage spike may be
observed on the SR FET, especially in CCM condition.
Figure 6 ― SR Driver VDD Power Supply During System Transient
Figure 6 shows an example of SR driver power supply during system transient, although the system is
switching as soon as the output voltage (VOUT) is set up, the SR driver won’t stat to work until the power
supply (VDD) has crossed above the VDD UVLO, before which the switching current will flow through the
SR FET’s body diode.
In order to avoid reverse current and voltage spike lead by the output voltage drop out, we can:
z Parallel a small schottky diode on the SR FET. When the SR driver is turned off due to the system
output drop out, the switching current will flow through the external schottky diode which has lower
forward voltage drop and reverse recovery time compared with SR FET’s body diode.
z Make the VDD UVLO of the driver IC be crossed when system output is still fairly low. For example,
design the VDD of the SR driver IC be ~20V at steady state, so that the driver won’t be shut down
until the output voltage had dropped to ~30% according to (2) (the VDD UVLO of the SR driver is
~6V). This could help to extend the SR driver’s active state during system start-up or shutdown.
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
See figure 7 which SR driver startup earlier than in figure 6.
Figure 7 ― Extend the SR Driver’s Active Duration
z
Design the VDD power supply derived from secondary transformer winding as figure 5 shows.
This will make the VDD power supply capacitor charged as soon as the system is switching, which
means the VDD power supply voltage level rises much faster.
Figure 8 shows the simulation of the SR driver’s VDD power supply charge speed during system
startup. In which VDD1 is the SR driver’s power supply derived from transformer winding; VDD2 is the
power supply derived from auxiliary winding. From the comparison results, VDD1 is charged as soon
as the Flyback converter is switching (VD is the secondary side winding voltage), while VDD2 follows
the output voltage (VOUT) charge speed, which is much slower.
Figure 9 is the experimental results of the SR driver start when system is during start-up or SCP,
from which the simulation results in figure 8 is verified.
Figure 8 ― SR Driver Power Supply Charge Speed Comparison at Startup
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
400us
100us
Time Scale: 100μs/div
CH1: VGS (5V/div)
CH2: VDS (10V/div)
CH3: VDD (5V/div)
CH4: ISR (5A/div)
(a) SR VDD power from auxiliary winding
Time Scale: 100μs/div
CH1: VGS (5V/div)
CH2: VDS (10V/div)
CH3: VDD (5V/div)
CH4: ISR (5A/div)
(b) SR VDD power from external LDO circuit
Figure 9 ―SR Driver Power Charge during System Start-up & SCP Recovery
RC Snubber Design Guide
Generally, we need a simple RC snubber network putting in parallel to the drain-source of the SR FET,
which is responsible for damping the voltage overshoot lead by reverse current through the SR FET,
see figure 10.
diF VD
=
dt
LS
CP
RS
LS
+
CS
iF(t)
Irr
SR MOSFET
iF
Without
Snubber
+ VF -
LS ⋅
di Ls
dt
VD
-
VF(t)
VD
Figure 10 ― RC Snubber on SR MOSFET of Flyback Secondary Side
Figure 10 shows the equivalent model of the Flyback secondary side circuit with an RC snubber on SR
FET, where VD implies the secondary side voltage derived in equation (3), VF is the drain-source
voltage on SR FET, RS and CS forms the RC snubber network while LS is the leakage inductance of the
transformer secondary winding, CP implies the stray capacitance of the secondary side circuit.
VD = VOUT + VIN _ DC / n
Where VOUT is the output voltage; VIN_DC
ratio.
(3)
is the input DC voltage and n is the Flyback transformer turn-
a. Choose proper CS
In order to simplify the analysis model of CS impact on VF(t), consider RS as a constant 0, we can get
figure 11 and equation (4) as following, where CK implies “CS+CP” in figure 10.
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
CK
LS
+
+
VF
-
VD
-
Figure 11 ― Simplified Equivalent Circuit for RC Snubber Network (RS=0)
d2 VF (t)
V (t)
VD
+ F
=
2
L S ⋅ CK L S ⋅ CK
dt
VF (0 + ) = 0;
(4-a)
dVF (0 + )
= iF (0 + ) = Irr
dt
(4-b)
Where Irr is the peak reverse current through the SR MOSFET, which can be also find in figure 10.
From (4), the drain-source voltage through the SR MOSFET VF is as follows:
VF (t) = VD − VD ⋅ cos(ωO ⋅ t) + VD ⋅
ωO =
1
L S ⋅ CK
;CB = LS (
CB
⋅ sin(ωO ⋅ t)
CK
Irr 2
)
VD
(5-a)
(5-b)
When cos(ωOt) equals to 0, the VF(t) gets to its maximum which implies the peak voltage spike on SR
FET:
VF _ MAX = VD ⋅ (1 +
CB
)
CK
(6)
Figure 12 ―CS Value Effect on the SR FET Voltage Spike
From (6) and figure 12, we can know by designing CS larger, the damping effect on SR FET voltage
spike will be better. But in real application, considering the power loss on RC snubber in (7), CS is not
recommended to be set too large. Generally we choose CS as 2~3 times of CP for a fairly well damping
effect.
PSnubber =
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⋅ VD2 ⋅ CS ⋅ fs
2
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
b. Choose proper RS
The analysis model of RS impact on VF(t) is much more complicated than CS, due to the CS value is
always selected much larger than CP, figure 13 and (8) shows an simplified model for RS which neglects
the CP impact.
Figure 13 ― Simplified Equivalent Circuit for RC Snubber Network (CP=0)
d2 VF (t)
dV (t)
+ RS ⋅ CS ⋅ F + VF (t) = VD
2
dt
dt
+
dV (0 ) Irr RS ⋅ VD Irr ⋅ RS 2
VF (0 + ) = Irr ⋅ RS ; F
=
+
−
dt
CS
LS
LS
L S ⋅ CS
(8-a)
(8-b)
From (8), the drain-source voltage through the SR MOSFET VF is derived as follows:
I
α
⎡
⎤
VF (t) = VD − (VD − RS ⋅ Irr ) ⋅ ⎢cos(ω⋅ t) − sin(ω⋅ t)⎥ ⋅ e−α⋅t + rr ⋅ sin(ω⋅ t) ⋅ e−α⋅t
ω
CS ⋅ ω
⎣
⎦
RS
1
ω = ωO 2 − α 2 ; ωO =
;α =
2
⋅ LS
LS ⋅ CS
(9-a)
(9-b)
According to (9), by setting d’VF(t)/dt=0, the drain-source voltage spike across the SR FET will reach
to its maximum when:
⎡
⎤
I
(VD − RS ⋅ Irr ) ⋅ 2α + rr
⎢
⎥
CS
1
⎥
t = tM = ⋅ tan−1 ⎢ −
2
2
⎢
Irr ⋅ α ⎥
ω
ω −α
−
⎢ (VD − RS ⋅ Irr )
⎥
CS ⋅ ω ⎦
ω
⎣
(10)
Put (10) into (9), we can get the peak voltage spike on the SR FET with RC snubber is:
VF _ MAX = VD + e −α⋅tM ⋅ (VD − RS ⋅ Irr )2 +
2α ⋅ (VD − Irr ⋅ RS ) Irr
Irr 2
⋅
⋅
CS ωO 2 ⋅ CS 2
ωo 2
(11)
But VF_MAX in (11) is so complicated which can’t tell how RS affect this value, so we need further simplify
(11) as follows:
VF _ MAX = VD + VD ⋅ e
f(x,y) = −
x=
⎧⎪
⎫⎪
x
⋅ tan−1 [ f ( x,y )]⎬
⎨−
2
⎩⎪ 1− x
⎭⎪
⋅ 1 − 2xy + y 2
(2x − 4x 2 y + y) ⋅ 1 − x 2
1 − 3xy − 2x 2 + 4x 3 y
RS
2 L S / CS
;y =
LS
Irr
⋅
VD
CS
(12-a)
(12-b)
(12-c)
Once CS is selected, y in (12) becomes a constant which makes VF_MAX a function of x. Figure 14 shows
the drain-source peak voltage spike as function of x and y, from which we can see with different y value,
x that implies RS selection always has an optimized value which makes the drain-source peak voltage
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
spike (VF_MAX) minimum. With smaller y, the optimized x value will be closer to 1; while with y value
becomes larger, x needs to be selected smaller, which means smaller RS value needed.
4
y=2
3.75
3.5
3.25
y=1.5
VF_MAX / VD
3
2.75
2.5
2.25
2
y=1
1.75
y=0.8
1.5
1.25
1
y=0.5
y=0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
x = RS/2(LS/CS)
0.7
0.8
0.9
1
0.5
Figure 14 ― RS Value Effect on the SR FET Voltage Spike
c. How to determine CP and LS
The analysis above implies how to select RS and CS to make the RC snubber network best fit the
system according to different stray capacitance (CP) and inductance (LS). So before the RC snubber
design started, we need to determine the CP and LS of the system which may be derived by the
following simple method:
i.
ii.
iii.
Keep RC snubber unconnected, parallel a capacitor C1 on SR MOSFET and capture the drainsource voltage VDS oscillation frequency fsw1 by oscillograph.
Keep RC snubber unconnected, parallel a capacitor C2 on SR MOSFET and capture the drainsource voltage VDS oscillation frequency fsw2 by oscillograph.
Calculate the CP and LS by the following equation:
fsw1 =
fsw 2 =
1
2π ⋅ L S ⋅ (CP + C1)
1
2π ⋅ L S ⋅ (CP + C2)
(13-a)
(13-b)
Following is an example to determine CP and LS for a 20W universal input adapter application with CCM
Flyback:
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Time Scale: 40ns/div
CH1: VGS (5V/div)
CH2: VDS (10V/div)
CH4: ISR (5A/div)
C1=470pF; fsw1=10.2MHz
(a) VDS spike oscillation with C1
Time Scale: 100ns/div
CH1: VGS (5V/div)
CH2: VDS (10V/div)
CH4: ISR (5A/div)
C2=2.2nF; fsw2=6.85MHz
(b) VDS spike oscillation with C2
Figure 15 ―Drain-Source Voltage Spike Oscillation
According to (13) and bench test results in figure 15, CP and LS can be calculated as ~940pF and
~0.2μH.
d. Design Example for an optimized RC snubber network
A design example of RC snubber network for a 20W universal input adapter with CCM Flyback is as
follows:
- Input AC voltage: 90Vac~265Vac (VIN_DC: 120V~380V)
- Output DC voltage VOUT: 5V
- Transformer turn ratio n: 15 (From primary to secondary)
- Secondary stray capacitance and inductance: CP=940pF, LS=0.2uH, which is already got from (13)
and figure 15.
The RC snubber network needs to be optimized based on the condition when drain-source voltage
spike has its maximum value. For a universal input Flyback converter, the drain-source voltage spike
will reach its maximum during system start-up with high line input, in which condition both CCM
switching current and VD level is the highest.
Time Scale: 10μs/div
CH2: VDS (20V/div)
CH4: ISR (2A/div)
Figure 16 ― Maximum Voltage Spike during Start-Up at High Line Input
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Figure 16 shows the bench test result of the maximum voltage spike and reverse current (Irr) during
system start up at high-line input without RC snubber applied. Also based on the specification of this
20W Flyback converter, we can get:
Irr ≈ 2.8A
VD = VOUT + VIN _ DC / n ≈ 30V
CP ≈ 940pF;L S ≈ 0.2uH
According to the analysis above, we choose CS as 2~3 times of CP, in this design example, CS is
selected as 2.2nF:
CS = 2.2nF
So, from (12), now y can be derived as:
y=
LS
Irr
⋅
= 0.89
VD
CS
With y≈0.9, we can get the optimized RC snubber design is to make x be ~0.7 according to figure 14:
x=
RS
2 ⋅ L S / CS
≈ 0.7
(14)
From (14), RS can be calculated which is ~13.3Ω. So connect the RC snubber network as CS=2.2nF &
RS=13.3Ω, the maximum voltage spike on SR FET during system start-up at high line input is showed
in figure 17, we can find over 30V voltage spike is damped by the RC snubber compared with in figure
16.
Time Scale: 10μs/div
CH2: VDS (20V/div)
CH4: ISR (2A/div)
CS=2.2nF; RS=13.3Ω
Figure 17 ― Maximum Voltage Spike during Start-Up at High Line Input with RC Snubber
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Time Scale: 10μs/div
CH2: VDS (20V/div)
CH4: ISR (2A/div)
CS=2.2nF; RS=25Ω
(a) VDS voltage spike with RS=25Ω
Time Scale: 10μs/div
CH2: VDS (20V/div)
CH4: ISR (2A/div)
CS=2.2nF; RS=6.5Ω
(a) VDS voltage spike with RS=6.5Ω
Figure 18 ― Maximum Voltage Spike with different RS Value
Figure 18 shows the maximum voltage spike with the same CS but different RS value. We can find by
choosing RS larger or smaller than the optimized value (13.3Ω), the maximum voltage spike will be
larger.
SR Design Guide in CCM Flyback Application
It is required to pay more attention on the turn-off timing of the SR driver in CCM Flyback application.
Figure 19 shows the operation of MP6902 in CCM Flyback system, when CCM turn-off of switching
current ISD occurs at t1, the sensed drain-source voltage VDS on MP6902 will have a rapid increase
which is lead by the voltage drop (VLK) on the parasitic inductance of the SR FET’s package:
VDS = −ISD ⋅ rds(ON) + VLK
(15)
VLK = L S ⋅
dI
dt
(16)
Where the LS is the parasitic inductance of the SR FET’s package, dI/dt is the switching current slew
rate when CCM turn-off occurs. Due to the negative slew rate of dI/dt, VLK is reverse polarity compared
with the voltage drop on SR FET’s on resistance (rds(ON)).
For LS, figure 20 shows the typical LS value of a traditional TO220-3 package MOSFET simulated by
Ansoft. For some SMD packages, such like SO8 and TO252, the LS is a bit smaller, which is in figure
21. The trace on the PCB layout will also bring in some leakage inductance, which is ~1nH/mm.
Figure 19 ― Operation of MP6902 in CCM Flyback System
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Figure 20 ― TO220-3 Package Inductance vs. Switching Frequency Simulate by Ansoft
D2PAK
DPAK
Pakcage Inductance (nH)
6
SO8
5
PowerPAK
4
3
2
1
0
0
1
2
3
Frequency (MHz)
4
5
Figure 21 ― Surface Mount Packages Inductance vs. Frequency
For the CCM switch current turn-off slew rate dI/dt, it can be derived as:
dI VD
=
dt LS
(17)
VD = VOUT + VIN _ DC / n
(18)
Where VD is the Flyback secondary side voltage, VIN_DC is the input DC voltage, n is the transformer
turn ratio from primary to secondary, LS is the leakage inductance of the secondary transformer winding,
which can be estimated as ~2%-3% of the secondary winding inductance.
Following is an example for a 20W universal input adapter application with CCM Flyback:
-
Input AC voltage: 90Vac~265Vac (VIN_DC: 120V~380V)
Output DC voltage VOUT: 5V
Primary winding inductance Lm :1.8mH (leakage inductance: ~2%-3% of Lm)
Transformer turn ratio : 15 (From primary to secondary)
Switching Frequency : ~60kHz
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Derived from (17) and (18), the secondary CCM turn-off dI/dt for this case is around 60A/us~150A/us
due to the different input. With a TO220 package SR FET (~6.5nH package inductance at 60kHz from
figure 20), the voltage drop on package inductance VLK will be 400mV~900mV according to (16). This
voltage drop is much larger compared with the voltage drop on rds(ON) and dominate the VDS in (15)
trigger -30mV turn-off threshold of the IC affirmatively.
Figure 22 shows the test verification results for this 20W Flyback converter at low-line input, the drainsource voltage across SR FET rises to above 500mV as soon as the CCM current turn-off occurs, the
CCM dI/dt is ~60A/μs.
Time Scale: 40ns/div
CH2: VDS (500mV/div)
CH4: ISR (1A/div)
Figure 22 ― Drain-Source Voltage Bounce at CCM Current Turn-Off Falling Edge
From above analysis, in CCM Flyback application, the MP6902’s turn off threshold is always tend to be
triggered when the secondary CCM current turn-off falling edge occurs (t1 in figure 19).
Figure 23 ― CCM Turn Off of MP6902 in Flyback Converter
Figure 23 shows the different turn-off timing of the SR FET gate driver which affect the switching
current (ISD).
In figure 23(a), reverse current (shoot through) occurs due to the gate driver VGS is turned off after
switching current ISD crosses zero (at t2).
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Although the IC’s turn off threshold (-30mV) is triggered when switching current CCM turn-off occurs at
t1, there is always a time delay between t1 and gate driver’s turn-off, which is so-called turn off delay
(tD_off), the tD_off mainly include:
-
Internal Logic Delay: the SR driver IC’s response time, which is internal fixed.
-
Gate Driver Falling Time: the time for the driver IC to pull down the SR FET’s gate, depend on the
dynamic characteristics of the MOSFET (Qg etc.).
Turn-Off Delay vs. Cload
80
Turn-Off Delay (ns)
70
60
50
40
30
20
10
0
0
5
10
15
20
Cload (nF)
25
30
35
Figure 24 ― Turn off Delay vs. CLOAD for MP6902
Figure 24 shows the typical turn off delay of MP6902 with different capacitor load on gate driver. If this
turn off delay is smaller than the CCM current turn-off falling time (tf, from t1 to t2 in figure 23), no shoot
through occurs, such like in figure 23(b).
The CCM current turn-off falling time in figure 23 can be derived as:
tf =
If
dI/ dt
(19)
Where If is switching current level when the CCM turn off occurs, dI/dt is the turn-off current slew rate
which can be derived from (17).
In Flyback CCM operation, If can be calculated as:
If =
IOUT
n2 ⋅ VOUT
n ⋅ VOUT
−
⋅ (1 −
)
n ⋅ VOUT
2 ⋅ Lm ⋅ fs
VIN _ DC + n ⋅ VOUT
1−
VIN _ DC + n ⋅ VOUT
(20)
Where Lm is the transformer primary winding inductance, IOUT is the output current and fs is the system
switching frequency.
From figure 23, known that in order to avoid reverse current lead by shoot through in CCM Flyback with
MP6902, it is preferred TD_off ≤ tf to make sure the gate driver be pulled down before switching current
drops to zero.
But when the Flyback system operates in CrCM, in which condition If in (20) is nearly zero, the reverse
current (Irr) lead by shoot through will easily occurred, see figure 25:
Irr =
dI
dI
⋅ (tD _ off − t f ) ≈ ⋅ tD _ off
dt
dt
(21)
When apply MP6902 in a CCM Flyback system, we need always to take such critical (CrCM) conditions
into consideration, which may has highest reverse current or voltage spike.
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Figure 25 ― CrCM Turn off of MP6902 in Flyback Converter
Basically there are two critical conditions which need to pay attention to:
i.
At steady state: with the input voltage when the system is working in CrCM at full load condition.
ii.
At system transient (start-up etc.): system output start-up with maximum input voltage, during
which the system may also works in CrCM.
Following are some design guides which to reduce the reverse current and voltage spike on SR FET for
these critical conditions:
z
Design proper snubber network on SR FET to absorb the energy lead by the reverse current to
avoid high voltage spike on MOSFET. Refer to “RC Snubber Design Guide” section.
z
Select the SR FET with smaller Qg, which help to reduce the tD_off. Basically we can evaluate our
desired tD_off based on figure 14 and equation (12):
For example, if we hope the maximum voltage spike VF_MAX be less than 1.5 times of VD, then
known from figure 14, to get VF_MAX/VD ≤1.5, we need to design y ≤1:
y=
LS
Irr
⋅
≤1
VD
CS
Because LS, CS (selected as 2~3 times of CP, can preset a certain value) value is already known,
we can get the desired reverse current level as follows:
Irr ≤ VD ⋅
CS
LS
According to equation (21) for the reverse current in critical condition, the desired tD_off is finally
derived as:
VD ⋅
tD _ off ≤
CS
LS
dI/ dt
z
Add totem-pole circuit on driver to increase the sink ability, which could help to decrease the gate
driver falling time during turn-off.
z
According to (17), increase the leakage inductance of the transformer is an effective way to make
dI/dt smaller. A small saturable core put in series with the primary winding is also helpful to
decrease the dI/dt.
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
By above actions, we need to make sure that the BV of the SR FET never be crossed in such critical
conditions to ensure the system’s safety with MP6902.
CCM Flyback SR Design Example with MP6902
A detailed Flyback SR design example based on a 20W universal input adapter will be presented in this
section. The system specification is as following:
-
Input Voltage VIN_DC: 120V to 380V (85VAC to 265VAC)
Output DC voltage VOUT: 5V
Output Current IOUT: 4A
Transformer turn ratio n: 15
Transformer inductance Lm: 1.8mH
Switching frequency fs: 60kHz max
Secondary-side leakage inductance LS: ~0.2uH (Refer to “RC Snubber Design Guide” section for
how to get this value)
RC snubber Capacitor CS: 2~3 times of CP, preset as 2.2nF
This Flyback system is designed to operate in CCM at full load with low line input, while at high line
input, the system will always operate in DCM at steady state.
So considering the CCM operation, get the secondary CCM current turn-off slew rate dI/dt according to
(17) and (18):
dI VD VOUT + VIN _ DC / n
=
=
dt L S
LS
Figure 26 ― Secondary CCM Current Slew Rate
Figure 26 shows the SR CCM current slew rate. Because the system is designed work at CrCM at full
load in ~170VAC (240V DC) input, the critical conditions which may occur highest reverse current or
voltage spike for this case is:
1. Steady state: 170VAC (240V DC) input, full load condition. (~100A/us dI/dt according to figure 25)
2. System start up: 265VAC (380V DC) input, full load condition. (~150A/us dI/dt according to figure
25)
For this 5V output Flyback system, the maximum VD from (18) will be ~30V, so a 60V MOSFET is
selected. Considering 25% margin for the BV of the SR FET, it is desired that the maximum voltage
spike on SR FET (VF_MAX) be less than ~45V, which means VF_MAX/VD ≤1.5.
So from figure 14 and equation (12), to make VF_MAX/VD ≤1.5, the y value in (12) should follow:
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
y=
LS
Irr
⋅
≤1
VD
CS
L S = 0.2μH;CS = 2.2nF
(22-a)
(22-b)
Put (21) and (22) into the two critical conditions for this case:
1. Steady state, 170VAC (240V DC) input:
Irr = tD _ off ⋅ 100A / μs ≤ 2.2A
(23-a)
2. System start up, 265VAC (380V DC) input:
Irr = tD _ off ⋅ 150A / μs ≤ 3.15A
(23-b)
From (23), we can get the desired TD_off for this case is ~22ns. Then select the 60V SR MOSFET as
AM90N06 from Analog Power, which has about 25ns turn-off delay according to figure 24.
After determine the tD_off, maximum Irr can be get then from (21). Then design the RS for the RC
snubber network (refer to “RC Snubber Design Guide” section), which is ~12Ω.
Verify the design in bench test for the two critical conditions, check the reverse current and voltage
spike which is in figure 27 and figure 28.
From the bench verification results, we can see that the reverse current and voltage spike in both
critical conditions are within the desired target.
Time Scale: 10μs/div
CH1: VGS (5V/div)
CH2: VDS (10V/div)
CH4: ISR (5A/div)
(a) VIN=170VAC Steady State Overview
Time Scale: 20ns/div
CH1: VGS (2V/div)
CH2: VDS (10V/div)
CH4: ISR (1A/div)
VF_MAX=29.2V; Irr=2.09A
(a) VIN=170VAC Steady State Zoom-view
Figure 27 ― Reverse Current and Voltage Spike in the Critical Condition (Steady State)
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Time Scale: 10μs/div
CH1: VGS (5V/div)
CH2: VDS (10V/div)
CH4: ISR (5A/div)
(a) VIN=2650VAC Start Up Overview
Time Scale: 20ns/div
CH1: VGS (2V/div)
CH2: VDS (10V/div)
CH4: ISR (1A/div)
VF_MAX=42.1V; Irr=2.89A
(a) VIN=265VAC Start Up Zoom-view
Figure 28 ― Reverse Current and Voltage Spike in the Critical Condition (Start Up)
Sometimes you may find some error between the calculation and experimental results, which makes
the bench verified reverse current and voltage spike exceed your desired target, or you may find the
calculated tD_off from (22) and (23) is so small which you can’t select proper SR MOSFET. In these
cases, you may need to:
z
z
Select the CS larger, recalculate the desired Irr and tD_off according to (22) and (23). Recalculate RS
for the RC snubber.
Make the LS larger, recalculate the dI/dt in (17) and desired Irr, tD_off according to (22) and (23).
Recalculate RS for the RC snubber.
Figure 29 shows the summarized design procedure for applying MP6902 in CCM Flyback system.
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Figure 29 ― MP6902 Design Procedure in CCM Flyback System
LAYOUT CONSIDERATIONS
Listed below are the main recommendations which should be taken into considerations when designing
the PCB with SR driver in a Flyback converter:
Sensing for VD/VSS
The sensing connections (VD/VSS pin) must be as close as possible to the MOSFET (drain/source).
Make the sensing loop as small as possible, put the IC out of the power loop to make sure the sensing
loop and power loop won’t interfere each other. (See figure 30)
Figure 30 ― Voltage Sensing for VD/VSS on SR Driver
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
VDD Decoupling Capacitor
A decoupling ceramic capacitor (no small than 1uF) from VDD to PGND is recommended to be put close
to the IC in order to get adequate filtering.
Gate Driver Loop
In order to minimize the parasitic inductance, the gate driver loop is recommended to be as small as
possible. Leave the driver signal far away from the VD sensing trace on the layout.
Layout Example
C5
R5
R4
Q1
G
D
R3
S
CSN
0
C4
RSN
C3
0
R2
D2
LAYOUT TRACE
COMPONENTS PAD
JUMP WIRE
Figure 31 ― Single Layer with TO220 Package SR FET
Figure 31 shows a layout example of single layer with a through-hole transformer and TO220 package
SR FET, correspond with the application circuit in figure 1 (RSN and CSN are the RC snubber network for
the SR FET).
The sensing loop (VD/VSS pin to the SR FET) is minimized and separate from the power loop, VDD
decoupling capacitor (C4) is put just beside the VDD pin.
Figure 32 shows another layout example of single layer with a PowerPAK/SO8 package SR FET, which
also has a minimized sensing loop and power loop without interfering each other.
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AN077 – MP6902 SYNCHRONOUS RECTIFICATION CONTROLLER
Figure 32 ― Single Layer with Power PAK/SO8 Package SR FET
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
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