AN059 Primary-Side-Control with Active PFC Offline LED Controller The Future of Analog IC Technology MP4021A, Primary-Side-Control with Active PFC Offline LED Controller Application Note Prepared by JiaLi Cai Sep 08, 2011 AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 1 AN059 Primary-Side-Control with Active PFC Offline LED Controller The Future of Analog IC Technology 1. INTRODUCTION ............................................................................................................................... 3 2. RIMARY-SIDE-CONTROL, BOUNDARY CONDUCTION MODE OPERATION WITH PFC.............. 3 3. PIN FUNCTION AND OPERATION INFORMATION......................................................................... 8 4. DESIGN EXAMPLE......................................................................................................................... 15 A. Specifications......................................................................................................................... 15 B. Schematic ............................................................................................................................... 15 C. Turns Ratio-N, Primary MOSFET and Secondary Rectifier Diode Voltage Rating Selection ..................................................................................................................................................... 16 D. Transformer Design ............................................................................................................... 17 E. Input EMI Filter (L1, L2, CX1, CX2, CY1) ............................................................................... 22 F. Input Bridge (BD1) .................................................................................................................. 22 G. Input Capacitor (C4)............................................................................................................... 22 H. Output Capacitor (C1, C2)...................................................................................................... 23 I. RCD Snubber (R6, C8, D2)....................................................................................................... 23 J. VCC Power Supply (R5, R13, C6, C7, D3, D6) ....................................................................... 25 K. ZCD and OVP Detector (R1, R2, C11, D5) ............................................................................. 25 L. Gate Driving Resistor and MULT Pin Resistor Divider (R7, R3, R4, C5) ............................. 25 M. Current Sensing Resistor and Feedforward (R8, R9, R10, R12, R14)................................. 25 N. ZCD OCP Detector (R15, R16, D8)......................................................................................... 26 O. Layout Guideline.................................................................................................................... 26 P. BOM......................................................................................................................................... 28 5. EXPERIMENTAL RESULT.............................................................................................................. 29 ANNEX: DESIGN GUIDE FOR REPLACING MP4021 WITH MP4021A…………………………………34 AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 2 AN059 Primary-Side-Control with Active PFC Offline LED Controller The Future of Analog IC Technology 1. INTRODUCTION The MP4021A is a primary-side-control offline LED lighting controller with PFC integrated. The primaryside-control can significantly simplify the LED lighting driving system by eliminating the opto-coupler and the secondary feedback components in an isolated single stage converter. Its proprietary real current control method can accurately control the LED current from the primary side information. Internally integrated current accuracy compensations can enhance the LED current accuracy for line input voltage variation (universal input voltage range), output voltage variation and transformer inductance tolerance. The MP4021A integrates power factor correction function and works in boundary conduction mode. The power factor correction function can achieve the PF>0.9 in a universal input voltage range. The boundary conduction mode operation can reduce the switching losses and improve the EMI performance. The extremely low start up current and the quiescent current can reduce the power consumption thus lead to an excellent efficiency performance. The MP4021A provides multiple advanced protections to enhance the system safety. The protections include over-voltage protection, short–circuit protection, cycle-by-cycle current limit, VCC UVLO and thermal shutdown. The special construction inside the FB pin allows MP4021A also quite suitable for non-isolate applications. In non-isolate condition, the feedback signal can be directly applied on FB pin. Figure 1—Typical Application 2. RIMARY-SIDE-CONTROL, BOUNDARY CONDUCTION MODE OPERATION WITH PFC The conventional off-line LED lighting driver usually uses the secondary side control. The LED current is directly sensed in the secondary side and fed to comparison with the reference which is typically made up by TL431, the EA output is compensated and fed to primary side by an opto-coupler to determine the duty cycle and thus regulate the LED current. Although this control method has its advantage that directly control the LED current and the current accuracy can be conformed in any conditions, but it also brings obvious disadvantages, lots of circuits and components are needed in the secondary side, including sensing circuit, comparison and compensation circuit, opto-coulpler and bias power supplies which significantly increases the cost and system complexity. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 3 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER Besides, the primary side input stage of a conventional LED lighting driver typically uses a full wave rectifier bridge with an E-cap filter to get an unregulated DC voltage. The E-cap should be large enough to keep a relatively low ripple on the DC voltage. This means the instantaneous input line voltage is lower than the DC voltage on the E-cap most time of a line half-cycle, thus the rectifier diodes only conduct a small portion and make the line input current like a series of narrow pulses whose amplitude maybe 10 times higher than the average DC level. A lot of drawbacks are resulted: much higher peak and RMS current draw from the line, distortion of the line input current causes a poor power factor (most time only 0.5-0.6) and induces large high harmonic contents. As Shown in Figure 1, the MP4021A uses primary-side-control, no need any secondary feedback components, which can sharply reduce the component amount and cost. As we know, the LED current is the average current of transformer secondary side during a line half-cycle Io = Is _ avg , the MP4021A can calculate the average current of the transformer secondary side from the primary side information and control it to a required value, this is the MP4021A primary-side-control principle. The MP4021A integrates power factor correction function and works in boundary conduction mode. The boundary conduction mode, makes the transformer work on the boundary between the continuous and discontinuous mode, which is quite different from the well-known resonant converter. Figure 2 shows the drain-source voltage waveform of primary switch in a conventional current-mode flyback converter operating in the discontinuous conduction mode (DCM). During the first time interval, the drain current ramps up to the desired current level. The power MOSFET then turned off. The leakage inductance in the flyback transformer rings with the MOSFET parasitic capacitance and causes a high voltage spike, which is limited by a clamp circuit. After the inductive spike has damped, the drain voltage equals to the input voltage plus the reflected output voltage. The drain voltage would immediately drop to the bus voltage when the current in the output diode drops to zero if the parasitic ring of the primary inductance and the parasitic capacitance is ignored. However, the drain voltage rings down to this level as shown in Fig 2 due to the parasitic resonance by the primary inductance and the total parasitic capacitance. For example, the inductance is 1mH and the parasitic capacitance is 100pF, then the resonant frequency is 500kHz. The resonant circuit is lightly damped and the resonant frequency given below is independent of the input voltage and load currents: fresonant = 1 2π ⋅ Lm ⋅ Ceqp Where Lm is the primary inductance; Ceqp is the equivalent primary side parasitic capacitance which including parasitic capacitance of the primary winding, the parasitic capacitance of the MOSFET and the parasitic capacitance of the secondary side (including the secondary winding and output rectifier diode) reflect to primary side. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 4 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER Figure 2—Single-Pulsed Flyback Converter In a conventional fixed frequency flyback converter at DCM operation, the primary switch (MOSFET) is turned on at a fixed frequency and turned off when the current reaches the desired level. The device's turn-on time may occur at any point during this parasitic resonance. In some cases the device may turn on when the drain voltage is lower than the bus voltage (means low switching losses and high efficiency), and in some cases the switch will turn on when the drain voltage is higher above the bus voltage (means high switching loss). This characteristic is often observed on the efficiency curves of a discontinuous flyback converters with a constant load, the efficiency fluctuated with the input voltage as the turn-on switching loss changes due to the variation of the drain voltage at the turn on point. In boundary conduction operation, the switch does not have a fixed switching frequency. The switch will always turn on by the controller when the drain voltage reaches its relatively low point. This can be achieved by detecting the auxiliary winding voltage VZCD, which is a ratio of primary winding voltage. Show in the Figure 3, setting a falling edge detecting near zero, when the secondary side current deceases to zero, the parasitic resonance make the ZCD voltage decrease, when it reaches to detecting threshold, the MOSFET turning on signal will be triggered. The detecting delay time is determined by the transformer magnetizing inductance, parasitic capacitance and ZCD filtering capacitor. The switch on time (T1 in Figure 3) is determined by the feedback loop as conventional peak current mode control. The energy stored in the magnetizing inductor is fully transferred to the output. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 5 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER Figure 3—Boundary Conduction Mode Compared to the conventional flyback under CCM and DCM operation, the boundary conduction mode operation can minimize the turn on switching loss, thus increasing efficiency and lowering device temperature rise. N:1 EMI filter GATE MULT Control Multiplier PWM/PFC Current control Gate driver Current sense CS Current Sense COMP Current LImit OTP Latch off or Restart Protection Power supply UVLO FB/NC VCC Real Current Control Power Supply OVP GND OCP ZCD Zero Current Detection Zero current detection Figure 4—MP4021A Function Block Diagram and the Controlled LED Driving Converter The MP4021A function block diagram and the controlled LED Driving Converter are shown in Figure 4. The converter consists of an EMI filter, a diode bridge rectifier, a flyback circuit with the controller MP4021A. The goal is to regulate the output LED current to a required constant value and achieve the AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 6 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER power factor correction function of input current. The operation of the converter can be summarized by the following description. The AC mains voltage is rectified by the diode bridge, the rectified half sinusoid wave is applied to the flyback circuit. When the MOSFET is turned on, the transformer primary side current begins to ramp up from zero, and this current will be sensed at CS pin through a sensing resistor. The sensed current signal will be fed to the primary-side-control block to calculate its average value. The internal error amplifier compares the average value with an internal reference (0.4V), generating a signal error proportional to the difference between them. If the bandwidth of the error amplifier is narrow enough (below 20Hz), the error signal is a DC value over a line half-cycle and kept at a constant value until the average value equals the reference. That means the output LED current is regulated to a required constant value. The error signal is fed into the multiplier block and multiplied by a partition of the rectified mains voltage. The result will be a rectified sinusoid whose peak amplitude depends on the mains peak voltage and the value of the error signal. The output of the multiplier is then fed into the negative input of the current comparator, thus it represents a sinusoidal reference for PWM. As the voltage on the current CS pin equals the value on the negative input of the current comparator, the external MOSFET is turned off. As a consequence, the peak primary current will be enveloped by a rectified sinusoid and has the same phase with the main input voltage, so a good power factor can be implemented. It is possible to prove also that this operation produces a constant ON-time over each line half-cycle. VCS = Rs ⋅ Vin ⋅ Ton Lm Have VCS = VMultiplier , VMultipier = K1 ⋅ K 2 ⋅ Vin * (VCOMP − 1.5) , got Ton = Lm ⋅ K1 ⋅ K 2 ⋅(VCOMP − 1.5) Rs Where Lm is the primary inductance, Rs is the current sensing resistor, K1 is the multiplier gain, K 2 is the ratio of the MULT pin voltage to mains voltage. After the MOSFET has been turned off, the transformer discharges its magnetizing energy into the load at the secondary side until its current goes to zero. When the current reaches to zero, the transformer has now run out of energy, the drain node is floating and the inductor resonates with the total capacitance of the drain. The drain voltage drops rapidly below the instantaneous line voltage and the detecting signal on ZCD drives the MOSFET on again and another conversion cycle starts. So, in each duty cycle, the MOSFET turns on at the current reaching zero, the converter works at boundary conduction mode. The relatively low drain voltage at turning on reduces both the turn on loss and the drain capacitive energy which is also dissipated at MOSFET turning on. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 7 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER Figure 5—Transformer Both Side Current and MOSFET Gate Timing The transformer current on both side and the MOSFET gate timing are shown in Figure 5. The operation frequency increases with the instantaneous mains voltage increases. when the mains voltage closed to the zero-crossing point, the frequency maybe very high. The MP4021A has internally set a 3.5µs minimum off time to limit the maximum switching frequency and help for high efficiency and low EMI performance. PIN FUNCTION AND OPERATION INFORMATION Pin1 (MULT) The MULT pin is one of the input pin of the internal multiplier. This pin should be connected to the tap of the resistor divider from the rectified instantaneous line voltage. The output of the multiplier will be shaped as sinusoid too. This signal provides the reference for the current comparator which sets the primary peak current shaped as sinusoid in phase with the input line voltage cycle by cycle. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 8 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER + Figure 6—The MULT Pin Connection Circuitry The MULT pin linear operation voltage range is 0~3V, for an universal AC input application, the MULT pin voltage need to be set low at the minimum AC input voltage so that the MULT voltage will not exceed 3V at the maximum AC input voltage. But also, the MULT pin voltage can not be set too low, this will cause a high COMP voltage to regulate the same LED current, The COMP voltage may saturate when the MULT pin is set too low. A recommended model to set the MULT voltage is shown as follow: 2 ⋅ Vin _ max(rms) ⋅ RMULT2 ≈ 2.5 ~ 3 RMULT1 + RMULT2 Considering the losses, the RMULT1 should be large enough, for example, 85V~265VAC input, the RMULT1, RMULT2 can be chosen as 1M, 6.8kΩ with a 100pF bypass capacitor. Pin2 (ZCD) Figure 7—The ZCD Pin Connection Circuitry AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 9 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER The ZCD pin connection circuitry is shown in Figure 7. The ZCD pin is connected to the auxiliary winding through a resistor divider. The ZCD pin is used for three functions. One is to detect zero-cross condition of the auxiliary winding voltage after the secondary side current decreases to zero, which achieves the boundary conduction mode operation to minimize the switching losses and EMI. The second function of ZCD pin is to implement the output over voltage protection by comparing to the internal 5.4V reference. The third function is to activate the over current protection by detecting the primary-side current. The internal gate turn-on signal occurs when the ZCD pin voltage gets a falling edge below 0.31V from the resistor divider with a 0.65V hysteresis. A ceramic by pass capacitor is needed to absorb the high frequency oscillation of the leakage inductance and the parasitic capacitance after primary switch turns off which may mis-trigger the ZCD pin detection (see Figure 9). The switching frequency of MP4021A is variable, the frequency is changing with the input instantaneous line voltage. To limit the maximum frequency and get a good EMI and efficiency performance, MP4021A employs an internal minimum off time limiter—3.5μs, shown in Figure 8. ZCD GATE 3.5us Figure 8—Minimum Off Time The output over voltage protection is achieved by detecting the positive plateau of auxiliary winding voltage which is proportion to the output voltage (see Figure 9). Once the ZCD pin voltage is higher than 5.4V, the OVP signal will be triggered and latched, the gate driver will be turned off and the VCC voltage dropped below the UVLO which will make the IC reset and the system restarts again. The output OVP setting point can be calculated as: Vout − ovp ⋅ Naux R ZCD2 ⋅ = 5.4V Nsec R ZCD1 + R ZCD2 Where Vout _ ovp is the output OVP setting voltage; Naux is the auxiliary winding turns of the transformer and Nsec is secondary winding turns of the transformer. Following should be considered when choosing the resistor value: the losses and the ZCD falling edge detection delay time with the ceramic bypass capacitor, enlarging the delay time will reduce output LED current, basically, the delay time should be limited in 1.5μs. To avoid the OVP mis-trigger by the oscillation spike after the switch turns off, the MP4021A integrates an internal TOVPS blanking time for the OVP detection, typical 1.5μs (see Figure 9). Moving the current-limiting resistor between the output of the aux-winding and the ZCD resistor divider can also work as suppresser to avoid the mis-trigger OVP. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 10 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER Figure 9—The ZCD Voltage As over current protection, tie a resistor divider form CS sensing resistor to ZCD pin, shown in Figure 7. When the power MOSFET in the primary-side is turned on, the ZCD pin monitors the rising primaryside current, once the ZCD pin reaches OCP threshold, typical 0.6V, the gate driver will be turned off to prevent the chip form damage and the IC works at quiescent mode, the VCC voltage dropped below the UVLO which will make the IC shut down and the system restarts again. The primary-side OCP setting point can be calculated as: IPRI _ OCP ⋅ RCS ⋅ R OCP2 − VD = 0.6V ROCP1 + ROCP2 Where IPRI_OCP is primary-side over current protection current value, VD is the voltage drop of the diode. Please note that, when the MOS is turned on, the taps of the ZCD zero-current detector resistor divider and the OCP resistor divider are connected by a diode. So, to avoid the effect of the ZCD zero-current detector, the value of the resistors to set the OCP threshold (ROCP1 & ROCP2) should be much smaller than those of the ZCD zero-current detector (RZCD1 & RZCD2). For some applications, for example, the primary-side inductance value is very small, the minimal-off time feature could cause the system works in DCM at the zero-crossing of the BUS voltage. To improve the OCP function in this condition, please remove CZCD and reduce the value of RZCD1 and RZCD2 proportionally. Pin3 (VCC) Figure 10—The VCC Pin Connection Circuitry and the Power Supply Flow-Chart AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 11 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER The VCC pin provides the power supply both for the internal logic circuitry and the gate driver signal. The VCC pin connection circuitry and the power supply flow-chart is shown in Figure 10. When AC power supply is on, the bulk capacitor CVCC1 (typically 22μF) is first charged by the start up resistor RVCC1 from the AC line, once the VCC voltage reaches 13.6V, the IC will be enabled and begin to switch, the power consumption of the IC increases, then the auxiliary winding starts working and mainly takes the charge of the power supply for VCC. Since the voltage of auxiliary winding is proportion to that of the secondary winding, the VCC voltage will be finally regulated to a constant value. If VCC drops below the UVLO threshold 9V before the auxiliary winding can provide the power supply, the IC will be shut down and the VCC will restart charging from AC line again. If fault condition happens at normal operation, the switching signal will be stopped and latched, the IC works at quiescent mode, when the VCC voltage drops below 9V the system restarts again. So, the RVCC1 should be large enough to limit the charging current which ensures the VCC voltage can drop below 9V UVLO threshold at quiescent mode (typically 0.75mA consumption current in quiescent mode). Also, a small ceramic capacitor (typically 0.1μF) is needed to reduce the noise. Pin4 (GATE) Gate drive output for driving external MOSFET. The internal totem pole output stage is able to drive external high power MOSFET with 1A source capability and 1.2A sink capability. The high level voltage of this pin is clamped to 13.5V to avoid excessive gate drive voltage. And for normal operation, the low level voltage is higher than 6V to guarantee enough drive capacity. Connect this pin to the MOSFET gate in series with a driving resistor. A smaller driving resistor provides faster MOSFET switching, reduces switching loss and improve MOSFET thermal performance. However larger driving resistors usually provide better EMI performance. It is a tradeoff. For different applications, the driving resistors should be fine tuned. Typically, the value can be 5Ω~20Ω. Pin5 (CS) The CS pin is used to sense the primary side current via a sensing resistor, the resulting voltage is internally fed both to the current comparator to determine the MOSFET turn off time and the average current calculation block to calculate the primary current average value. The output LED mean current can be calculated approximately as: N ⋅ VFB I0 ≈ 2 ⋅ RS Where N is the turn ratio of primary winding to secondary winding, VFB is the feedback reference voltage (typically 0.4V), Rs is the sensing resistor connected between the MOSFET source and GND. The maximum voltage on CS pin is clamped at 2.5V to get a cycle-by-cycle current limit. In order to avoid the premature termination of the switching pulse due to the parasitic capacitance discharging at MOSFET turning on, an internal leading edge blanking (LEB) unit is employed between the CS Pin and internal feedback. During the blanking time, the internal fed path is blocked. Figure 11 shows the leading edge blanking. Figure 11— The Leading Edge Blanking AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 12 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER In the case of current sensing, shows as Figure 12, the MOSFET has a delay time due to the propagation delay of the gate control circuit, the delay time is the inherent characteristic of the control circuit, so Tdelay can be assumed as constant. The delay will lead an error of the primary side peak current. The error increases with the input instantaneous line voltage increase. △I2 is bigger than △I1 due to the bigger rising slope (the higher input voltage, the bigger rising slope). So, the difference of △I will cause a bad output LED current line regulation. Figure 12—The Propagation Delay of the Primary Current The propagation delay influence to the line regulation can be well improved by adding feed-forward from AC line voltage to CS pin, shown in Figure 13, the higher line voltage, the higher feed-forward offset. The feed-forward offset value need fine tune in real application and it is case by case. Figure 13—The Feedforward Compensation on CS Pin Pin6 (GND) Ground pin, current return of the control signal and the gate drive signal. It is recommended to connect power GND and analog GND to this pin in the PCB layout. The power GND for power switches and the analog GND for the control signals is desired to be separated and only connected at this pin. Pin7 (FB/NC) Feedback signal pin. Shown in Figure 14, the FB signal is fed to the error amplifier and comparing with the 0.4V reference, at steady state, the average value of FB will be regulated to 0.4V. The average current calculation block output is internally connected to the FB with high input impedance, if there is no other external feedback signal is applied on FB pin, the average current from CS pin will be regulated, if there is external FB signal with low input impedance apply in this pin, the external FB signal will be regulated. This structure makes the MP4021A suitable both for primary side control application without other feedback signals and direct control application with external feedback signal applied. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 13 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER Figure 14—FB Pin Structure Pin8 (COMP) Loop compensation pin. Connect a compensation cap from this pin to AGND. This cap should be low ESR ceramic cap such as X7R. The COMP pin is the internal error amplifier output. In order to get a limit loop bandwidth <20Hz, the cap should be select from 2.2µF to 10µF. A larger cap results in small input and output current ripple and better thermal, EMI, steady states performance, but also, a large cap means a longer soft start time which will cause a bigger voltage drop for VCC at start up (see Figure 15), if the VCC drops below UVLO, the start up may fail. So the compensation cap selection and the VCC voltage drop at start up should be double checked in real design. VCC ILED VCOMP VGATE 400ms/div Figure 15—COMP and VCC Waveforms at Start Up Output Short Circuit Protection When the output short circuit happens, theoretically, the positive plateau of auxiliary winding voltage is also near zero, the VCC can not be held on and it will drop below VCC UVLO. The IC will shut down and restart again. And at the same time, the primary current will rise up when output short circuit occurs, so it will trigger the ZCD over current protection to prevent the damage from output short circuit failure. Auto Restart The MP4021A integrates an auto starter, the starter starts timing when the MOSFET is turned on, if ZCD fails to send out another turn on signal after 130µs, the starter will automatically send out the turn on signal which can avoid the IC unnecessary shut down by ZCD missing detection. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 14 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER 4. DESIGN EXAMPLE 8W LED Bulb Driver with High Power Factor and Excellent Line Regulation A. Specifications • Input AC Vin (Vac ,t) = • • mains: 85V~265V RMS, Vac_min=85V, Vac_max=265V, Vin_max= 2 ⋅ Vac _ max , 2 ⋅ Vac ⋅ sin(2 ⋅ π ⋅ fmains ⋅ t) , Input AC mains frequency: fmains=50Hz Output: LED voltage Vo=16V, LED current Io=500mA, Po=VO*IO=8W Output OVP threshold: 22V B. Schematic MP4021A Figure 16—Schematic AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 15 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER C. Turns Ratio-N, Primary MOSFET and Secondary Rectifier Diode Voltage Rating Selection Figure 17 shows the typical Drain-Source voltage waveform of the primary MOSFET and secondary rectifier diode. From the waveform, the primary MOSFET Drain-Source voltage rating VP-MOS can be got as: VP −MOS = Vin _ max + N ⋅ VO + 150V (1) Where 150V maximum spike voltage is assumed here. The secondary rectifier diode voltage rating VDIODE can be got as: VDIODE = Vin _ max / N + VO + 40V (2) Where 40V maximum spike voltage is assumed here. Figure 17—Drain-Source Voltage of Primary MOSFET and Secondary Rectifier Diode From (1) and (2), the voltage rating of primary MOSFET and secondary rectifier diode versus turns-ratio N is shown in Figure 18. Then the turns-ratio N can be determined for the required MOSFET and Rectifier diode voltage rating. Sometimes N can be selected within a range, then smaller N means larger turn on time and larger primary RMS current, this will lead a larger size transformer, so a relatively larger N is preferred. Here choosing N=6, so 650V or 700V MOSFET and 150V, 200V schottky or fast recovery diode can be used. 3 1×10 1000 140 940 880 120 820 760 Vp_MOSFET ( N ) 700 Vs_diode( N ) 100 640 580 80 520 400 460 400 70.984 2 2 3 4 5 6 7 8 9 N 10 11 12 13 14 15 15 60 4 4 5 6 7 8 9 10 11 12 N 13 14 15 15 Figure 18—Voltage Rating of Primary MOSFET and Secondary Rectifier Diode vs. Turn Ratio-N AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 16 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER D. Transformer Design Primary Inductance Lp As described in page 7, the MP4021A implements constant ON-time operation during a line cycle with a given RMS line voltage. The turn-off time is variable with the instantaneous line voltage. Ton = Get: Lp ⋅ Ip Vin (Vac ,t) Toff = (3), Toff (Ton ,Vac ,t) = Lp ⋅ Ip (4), N ⋅ Vo Vin (Vac ,t) ⋅ Ton N ⋅ Vo (5) Considering the Toff limit within MP4021A, the Toff equation should be modified as: Vin (Vac ,t) ⋅ Ton Vin (Vac ,t) ⋅ Ton if > 3.5μs N ⋅ Vo N ⋅ Vo Toff (Ton ,Vac ,t) = (6) 3.5μs,otherwise Shown as Figure 19, the output LED current equals the average value of the secondary winding current during a half-line cycle. The calculating equation is shown in (7), it sums the secondary current in each cycle and then get the average value. t1 ← a sum ← 0 Io ( a, b, T o n , V a c ,L p ) = w h ile ( t1 < b ) (7) ⎪⎧ ⎡ V ( V , t1 + T o n ) ⋅ T o n ⋅ ⎨ ⎢ in a c Lp ⎩⎪ ⎢⎣ + T o ff ( T o n , V a c , t1 + T o n ) sum ← sum + t1 ← t1 + T o n 1 2 ⎤ ⎪⎫ ⎥ ⋅ N ⎬ ⋅ T o ff ( T ⎥⎦ ⎭⎪ on , V a c , t1 + T o n ) sum b −a Figure 19—Secondary Side Current AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 17 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER Usually, the system will define a minimum frequency fs_min, the minimum frequency will occur at π Vin = 2 ⋅ 85 sin( ) , here set fs_min=45 kHz, 2 Io (0,0.01,Ton _ 85V ,85,Lp ) = 0.5A fs _ min = 1 = 45kHz Ton _ 85V + Toff (Ton _ 85V ,85,0.005) (8) (9) Combine (8) and (9), can get Lp=2.2 mH, Ton_85V=9.86μs. The maximum primary peak current: Ipk _ max = Ton _ 85V ⋅ Vin (85,0.005) = 0.54A Lp (10) When getting the Lp, the maximum operation frequency also can be calculated, the maximum frequency will occur at Vin reach to zero crossing at 265VAC. fs _ max = Ton _ 265V 1 = 178kHz + Toff (Ton _ 265 V ,265,0) (11) The Primary Winding RMS Current: t1 ← a su m ← 0 (12) Ip ri _ rm s (a,b, To n , V a c ,L p ) = w h ile( t1 < b ) ⎧⎪ ⎫⎪ To n V ( V , t1 + To n ) ⋅ t 2 1 su m ← su m + ⎨ ( in a c ) ⋅ dt⎬ ⋅ ∫ 0 Lp ⎩⎪ To n + To ff (To n , V a c , t1 + To n ) ⎭⎪ [ To n + To ff ( T o n , V a c , t1 + To n ) ] t1 ← t1 + To n + T o ff (To n , V a c , t1 + To n ) su m b−a The maximum primary RMS current: Ipri _ rms _ max = Ipri _ rms (0,0.01,Ton _ 85V ,85,2.2 ⋅ 10 −3 ) = 0.156 A AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. (13) 18 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER The secondary winding RMS current: (14) t1 ← a sum ← 0 Isec_ rms (a,b,Ton ,Vac ,Lp ) = while(t1 < b) N4 ⋅ Vo2 Lp 2 Toff (Ton ,Vac ,t1+ Ton ) V (V ,t1 + T ) ⋅ T ⎪⎧ ⎪⎫ on on sum ← sum + ⎨ ( in ac − t)2 ⋅ dt ⎬ ⋅ ∫0 N ⋅ Vo ⎩⎪ Ton + Toff (Ton , Vac ,t1 + Ton ) ⎭⎪ [Ton + Toff (T on ,Vac ,t1+ Ton )] t1 ← t1 + Ton + T off (Ton ,Vac ,t1 + Ton ) sum b−a The maximum secondary winding RMS current: Isec_ rms _ max = Isec_ rms (0,0.01,Ton _ 85V ,85,2.2 ⋅ 10 −3 ) = 0.933 A (15) The Transformer Core Selection The transformer core needs to be appropriately selected for a certain output power within the entire operation frequency. Ferrite is widely adopted in flyback transformer. The core area product (AEAW) which is the core magnetic cross-section area multiplied by window area available for winding, is widely used for an initial estimate of core size for a given application. A rough indication of the required area product is given by following: AE ⋅ A W ⎛ Lp ⋅ IPk _ max ⋅ Irms _ max =⎜ ⎜ Bmax ⋅ K u ⋅ K j ⎝ ⎞ ⎟⎟ ⎠ 4/3 cm4 (16) Where Ku is winding factor which is usually 0.2~0.3 for an off-line transformer. Kj is the current-density coefficient (typically 0.042~0.045 A/m2 for ferrite core). IPk_max and Irms_max are the maximum peak current and RMS current of the primary inductance. Bmax is the allowed maximum flux density in normal operation which is usually preset to be the saturation flux density of the core material (0.3T~0.4T). So the estimated least core area product is 0.0347 cm4. Please refer to the manufacture’s datasheet to select the proper core which has enough margins. Also, the core shape should taken consideration to best meet the layout dimension. Here choosing EFD20 core. AE = 0.31 cm2, AW = 0.507 cm2, AE*AW=0.157 cm4. The core magnetic path length: lc=5.3 cm The relative permeability of the core material: μ γ = 2400 Primary and Secondary Winding Turns With a given core size, there is a minimum number of turns for the transformer primary side winding to avoid saturation. The normal saturation specification is E-T or volt-second rating. The E-T rating is the maximum voltage, E, which can be applied over a time of T seconds. (The E-T rating is identical to the AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 19 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER product of inductance L and peak current) Equation (17) defines a minimum value of NP for the transformer primary winding to avoid the core saturation: NP = Lp ⋅ Ipk _ max Bmax ⋅ A E × 10 4 (17) Where: Lp = the primary inductance of the transformer (H) Bmax= the maximum allowable flux density (T) AE= the effective cross sectional core area (cm2) Ipk_max= the maximum primary peak current (A) The maximum allowable flux density B should be smaller than the saturation flux density Bsat. Since Bsat decreases as the temperature goes high, the high temperature characteristics should be considered. Here get: Np = 144 Secondary turn count is a function of turn ratio N and primary turn count NP: NS = NP / N = 24 (18) Wire Size Once all the winding turns have been determined, wire size must be properly chosen to minimize the winding conduction loss and leakage inductance. The winding loss depends on the RMS current value, the length and the cross section of wire. The wire size could be determined by the RMS current of the winding: Spri = Ssec = Ipri _ rms _ max J Isec_ rms _ max J = 2.596 ⋅ 10 −2 (mm2 ) (19) = 1.554 ⋅ 10 −1 (mm2 ) (20) Here J is the current density of the wire which is 6A/mm2 typically. Due to the skin effect and proximity effect of the conductor, the diameter of the wire selected is usually less than 2*Δd (Δd: skin effect depth): Δd = 1 = 0.36 （ mm) π ⋅ fs _ min ⋅ μ ⋅ σ (21) Where μ is the magnetic permeability of the conductor, which is usually equals to the permeability of vacuum for most conductor, i.e. 4π × 10 −7 H/m, σ is the conductivity of the wire (for copper, σ is typically 6 × 10 7 S/m at 0 deg, σ will be larger as temperature increases, which means the Δd will get smaller). Therefore, multiple strands of thinner wire or Litz wire is usually adopted to minimize the AC resistance, the effective cross section area of multi-strands wire or Litz wire should large enough to meet the requirement set by the current density. Here can choose 0.2mm*1 wire for primary winding, 0.3mm*2 wires for secondary winding, the wire area for primary is S1=3.14*10-2 mm2, for secondary is S2=1.66*10-1 mm2. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 20 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER The Auxiliary Winding The auxiliary winding is mainly used to provide power for VCC and detect the current zero crossing for boundary mode operation, so the current requirement for auxiliary winding is very small, larger than 10mA is enough. The auxiliary winding output DC voltage is proportion to the output LED voltage with the turn ratio of Naux/Ns. Since the output LED voltage is 16V, considering the voltage drop in VCC current limit resistor R13, the Naux can be selected a bit larger than the secondary winding turns Ns. Here, Naux=27, 0.18mm wire is selected. The Window Area Fill Factor Calculation After the wire sizes have been determined, it is necessary to check whether the core window area can accommodate all the selected windings. The window area required by each winding should be calculated respectively and added together, the area for interwinding insulation and spaces existing between the turns should also be taken into consideration. The fill factor, means the winding area comparing to the whole window area of the core, should be well below 1 due to these interwinding insulation and spaces between turns. It is recommended that a fill factor no greater than about 20% be used. Np ⋅ S1 + Ns ⋅ S2 + Naux ⋅ S3 AW = 0.091 < 0.2 (22) If the required window area is larger than the selected one, either wire size must be reduced, or a larger core must be chosen. Of course, a reduction in wire size increases the copper loss of the transformer. The Air Gap With the selected core and winding turns, the air gap of the core is given as: G = μ0 ⋅ AE ⋅ NP 2 lc − = 0.36 （ mm) Lp μ r (23) Where AE is the cross sectional area of the selected core, μ0 is the permeability of vacuum which equals 4π × 10 −7 H/m. Lp and NP is the primary winding inductance and turns respectively, lc is the core magnetic path length and μr is the relative magnetic permeability of the core material. The Transformer Manufacture Instructions There are two main considerations for the transformer manufacture. To minimize the effect of the leakage inductance spike, the coupling between the transformer primary side and the secondary side should be as tight as possible. This can be accomplished be interleaving the primary and secondary winding in transformer manufacture (shown in Figure 20). To minimize the coupling influence from primary winding to auxiliary winding, the same mean dots of the two windings should be separated far away, a good mode is to place the GND pin of the auxiliary winding between the two dots, refer to Figure 21. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 21 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER Figure 20—The Transformer Winding Diagram Pin Out 1 8 2 7 3 6 4 5 View from the top Figure 21—The Transformer Pin Out and the Connection Diagram E. Input EMI Filter (L1, L2, CX1, CX2, CY1) The input EMI filter is comprised of L1, L2, CX1, CX2 and together with the safety rated Y class capacitor CY1. The value of the components should be selected mainly to pass the EMI test standard, but also need take the power factor into consideration. F. Input Bridge (BD1) The input bridge can use standard slow recovery, low cost diodes. Just three items need mainly considered in selecting the diodes bridge, the maximum input RMS current, the maximum input line voltage and the thermal performance. G. Input Capacitor (C4) In order to get a high power factor, the input decoupling capacitor should be limited in value. The function of the capacitor is mainly to attenuate the switching current ripple for the transformer high frequency magnetizing current. The worst condition will occur on the peak of the minimum rated input voltage. The maximum high frequency voltage ripple of the cap should be limited in 20%, or the big voltage ripple will influence the sensing accuracy of the MULT pin which will also influence the PFC function. C4 ≈ Ipk _ max − 2Ipri _ rms _ max 2 ⋅ π ⋅ fs _ min ⋅ Vac _ min ⋅ 0.2 = 68nF (24) In real applications, the input capacitor will be designed with taking EMI filter and the power factor value into account, the real value usually could be smaller than the calculated value, here, a 33nF/400V film cap is selected. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 22 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER H. Output Capacitor (C1, C2) The output voltage ripple has two components, the switching frequency ripple associated with the flyback converter, and the low frequency ripple associated with the input line voltage (50Hz). The selection of the output bulk cap depends on the output current, the admitted overvoltage and the desired voltage ripple. But for LED load application, the requirement is usually for the LED current ripple. In this case, the load is 5 LEDs in series, 500mA output current, 40% current ripple limitation, in order to meet this limitation, the output voltage ripple should be within 10% of the output voltage. The maximum RMS current of the output capacitor can be obtained as: Iout _ cap _ rms _ max = Isec_ rms _ max 2 − Io _ rms2 (25) Where Io_rms is the output RMS current and Isec_rms_max is the maximum secondary RMS current in (15). The maximum RMS current should be smaller than the RMS current specification of the capacitor. The maximum switching voltage ripple occurs at the peak of the minimum rated input line voltage, and the ripple (peak-peak) can be estimated by: ΔVo _ swtiching = Io _ max ⋅ Toff (Ton _ 85 V ,85,0.005) Cout + (Isec_ pk _ max − Io _ max ) ⋅ RESR (26) Where Io_max is the maximum instantaneous output LED current, the value is the 500mA mean value pluses the 20% peak ripple; Toff (Ton _ 85 V ,85,0.005) is the turn off time at the peak of the minimum rated input line. RESR is the ESR of output capacitor, typically 0.03 each cap; Isec_pk_max is the maximum peak current of the secondary winding. The maximum low frequency (twice line frequency, 100Hz) ripple can be estimated the function of the capacitor impedance and the peak capacitor current (equals the Io_max). ΔVo _ line = Io _ max 1 (2π ⋅ 2fline ⋅ Cout )2 + RESR 2 (27) It can be seen from the calculations, the output voltage ripple is dominated by the low frequency ripple (100Hz). Let ΔVo _ line = 1.4V , get the Cout=690μF. Here selecting two 470μF/35V bulk caps in parallel to minimize the ESR and the sharing the capacitor RMS value. A 30kΩ pre-load resistor is also added to limit the output voltage under open load condition. I. RCD Snubber (R6, C8, D2) The peak voltage across the MOSFET at turn-off includes the instantaneous input line voltage, the reflecting voltage from secondary side, and the voltage spike due to leakage inductance. To protect the MOSFET from over voltage damage. A RCD snubber is usually adopted to absorb the leakage inductance energy and clamp the drain voltage as shown in Figure 22. The value of the capacitor C8 and resistor R6, depend on the energy stored in the leakage inductance, and the energy must be dissipated by the RC network during each cycle. Figure 23 shows the voltage of the primary MOSFET and the snubber capacitor A point during turn-off. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 23 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER Figure 22—RCD Snubber on Primary Side Figure 23—MOSFET Drain Voltage and Snubber Capacitor A Point Voltage The energy stored in the leakage inductance at maximum input voltage can be obtained as: ELk _ max = 1 ⋅ Lleakage ⋅ Ipk _ Vin _ max 2 2 (28) Where Ipk_Vin_max is the peak current at maximum input voltage in primary side. Assuming all the leakage inductance energy is transferred to the snubber cap. A secondary relationship is: ELk _ max = 1 ⋅ C8 ⋅ ⎡⎣(Vin _ max + N ⋅ Vo + Vspike )2 − (Vin _ max + N ⋅ Vo + Vspike − ΔVC8 )2 ⎤⎦ 2 (29) Where Vspike is the spike voltage clamped by the RCD snubber, ∆VC8 is the voltage changing on the snubber cap caused by the leakage inductance. Assuming ∆VC8 << Vspike, and the 1 ⋅ 2π ⋅ L leakage ⋅C8 < TVin _ max , 4 ΔVC8 = Vspkie （ ⋅ 1− e − t1 R6⋅C8 ） (30) 1 4 Where t1 is the time TVin _ max − ⋅ 2π ⋅ L leakage ⋅C8 . TVin_max is the switching period at Vin_max. For selecting the snubber resistor R6, the reflecting voltage from secondary side must be taken into consideration, this voltage will constantly add on the snubber resistor after MOSFET turns off, so the resistor R6 should be large enough to reduce reflecting voltage loss. In this case, according to the equation (6), (7), (10), the Ipk_Vin_max=0.349A, Ton_265V=2.05μs, Tvin_max=10.09μs, the leakage inductance is estimated as 1% of the primary inductance, 22μH, selecting the snubber parameters: C8=22nF, R6=100kΩ. Get, Vspike=123V, ∆VC8=0.45V. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 24 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER The voltage rating for the snubber cap and the diode should be larger than the Vin_max, the diode can use fast recover diode, such as FR107. It is hard to theoretically calculate the power dissipation of the snubber resistor R6, it needs to monitor the thermal performance of the resistor in test, if the temperature rise is high, it needs to change to a bigger power dissipation resistor. J. VCC Power Supply (R5, R13, C6, C7, D3, D6) The detailed VCC power supply function is described in page 11. The circuitry consists of R5, R13, C6, C7, D3, D6. Following should be taken into consideration for selecting the bulk capacitor C6, the voltage ripple at VCC and the VCC dropping time at quiescent mode, usually, the VCC ripple should be limited within 1V, typically 22μF is selected. The start resistor R5 with C6 determines the system start delay time, if a shorter delay time is required, select a smaller R5, but the power dissipation of the resistor and the charging current need to be taken care, here a 499kΩ resistor is selected. The resistor R13 is used to limit the charging current from the auxiliary winding, normally, there is oscillation spike voltage at the rising edge of the positive plateau of the auxiliary winding, the charging current should be limited within 100mA. But there will be about 2mA constant operation mean current flow through the resistor, so the value of the resistor can not be too large, usually, the resistor is selected from 100Ω~1kΩ. The voltage rating for the rectifying diode D3 should meet the following equation: VD3 > VCCmax + Naux ⋅ Vin _ max + Vaux _ negtive _ spike Np (31) Where VCCmax is the maximum VCC voltage, in this case, VCCmax= 15V, Naux and Np are the auxiliary winding and primary winding turns, Vaux_negtive_spike is the maximum negative spike on auxiliary winding, in this case, Vaux_negtive_spike= 40V, A 100pF ceramic bypass capacitor (C7) is added to reduce the high frequency noise influence on VCC pin, and a 18V zener diode (D6) is also added to limit the VCC voltage at open load condition. K. ZCD and OVP Detector (R1, R2, C11, D5) Please refer to page 9 for detailed design information. The resistor divider by R1 and R2 sets the OVP threshold: N R2 = 5.4V Vo _ ovp ⋅ aux ⋅ (32) Ns R1 + R 2 Where Vo _ ovp is the output OVP setting voltage; Naux is the auxiliary winding turns of the transformer and Ns is secondary winding turns of the transformer. In this case, Vo_ovp=20V, Naux=27, Ns=24, we can select R2=22.1kΩ, R1=80.6kΩ. A 10pF ceramic bypass capacitor (C11) is added on ZCD pin to absorb the high frequency oscillation on ZCD voltage at MOSFET turning off. Also, a diode (D5) is connected from ZCD pin to GND to clamp the ZCD negative voltage which can help improve the noise influence for the ZCD pin. L. Gate Driving Resistor and MULT Pin Resistor Divider (R7, R3, R4, C5) Considering both fro the EMI performance and the MOSFET switching speed, the gate driving resistor (R7) is selected as 20Ω. For the MULT pin resistor divider setting information, please refer to page 8. Here selecting the R3=1MΩ, R4=6.8kΩ,, C5=100pF. M. Current Sensing Resistor and Feedforward (R8, R9, R10, R12, R14) The current sensing resistor can be approximately set by the following equation: Rs ≈ AN059 Rev. 1.4 12/30/2013 VFB ⋅ N 2 ⋅ Io www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. (33) 25 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER Where N is the turn ratio of primary winding to secondary winding, VFB is the feedback reference voltage (typically 0.4), Rs is the sensing resistor connected between the MOSFET source and GND. But in real application of primary side control, it is hard to get a totally accurate equation for the output current, because there are many factors influencing the output current setting value, such as the internal logic delay of the IC, the transformer inductance, the MOSFET input and output capacitor, the ZCD detection delay time, even the RCD snubber and the gate driver resistor…etc. So, this is why the current sensing resistor is last decided in design and the value must be fine tuned in bench test to get the required output current. For the feedforwad compensation function description, please refer to page 12. There are the same influence factors for the feedforward compensation, it also need fine tune case by case. In this application with bench test, the sensing resistor is tuned as 2Ω and feedforward compensation can be very small (R10=10MΩ, R12=100Ω). N. ZCD OCP Detector (R15, R16, D8) Please refer to page 11 for detailed design information. The primary-side OCP setting point can be calculated as: IPRI _ OCP ⋅ RCS ⋅ R 16 − VD8 = 0.6V R15 + R16 (34) Where IPRI_OCP is primary-side over current protection current value, VD is the voltage drop of the diode. To avoid the effect of the ZCD zero-current detector, the value of the resistors to set the OCP threshold (R15 & R16) should be smaller than those of the ZCD zero-current detector (R1 & R2). In this case, we select R15=510Ω, R16=3kΩ, D8 is 1N4148, the primary-side OCP setting point is limited to less than 800mA. O. Layout Guideline z The path of the main power flow should be as short as possible, and the wire should be as wide as possible, the cooper pour for the power devices should be as large as possible to get a good thermal performance. z Separate the power GND and the analog GND, connect the two GND only at a single small point (here is the anode of D5). z In order to minimize the coupling influence from the primary winding to the auxiliary winding, the same mean dot of the two windings should be far away. It is better to be separated by the GND. z The IC pin components should be placed as close as possible to the corresponding pin, especially the ZCD bypass capacitor and the COMP pin capacitor. z The primary side and the secondary side should be well isolated, the trace from the transformer output return pin to the return point of the output filter capacitor should be as short as possible. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 26 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER Figure 24—The Bottom Layer Figure 25—The Top Layer AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 27 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER P. BOM Qty 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 2 1 1 2 1 1 1 1 AN059 Rev. 1.4 12/30/2013 RefDes BD1 C1, C2 C3 C4 C5, C7 C6 C8 C9 C10 C11 CX1 CX2 CY1 D1 D2 D3 D4 D5, D8 D6 D7 F1 L1, L2 Q1 R1 R2 R3, R11 R4 R5 R6 R7 R8 R9 R10 R12 R13 R14 R15 JR1, JR2 R16 R17 R18, R19 RV1 T1 U1 U2 Value DF06S NC 33nF/400V 100pF 22nF/630V NC 10pF 68nF 47nF 2.2nF/250V NC US1K ES1D MURS320 1N4148 BZT52C18 NC 250V/2A 4.7mH STK0765BF Description BRIDGE, 600V, 1A Electrolytic Capacitor, 35V Package SMD DIP Manufacturer Fairchild Rubycon Manufactuer_P/N DF06S CBB, 400V Ceramic Capacitor, 50V, X7R Electrolytic Capacitor, 50V Ceramic Capacitor, 630V, X7R DIP 0603 DIP 1206 Panasonic LION Jianghai TDK ECQE400VDC333K 0603B10K500T CD281L-50V22 C3216X7R2J223K Ceramic Capacitor, 10V, X7R Ceramic Capacitor, 50V, COG Film Capacitor, X2, 275V Film Capacitor, X2, 275V Y Capacitor, 250V 0805 0603 DIP DIP DIP Murata Murata Carli Carli Hongke GRM21BR71A225KAO1 GRM1885C1H100JAO1 PX683K3IC39L270D9R PX473K3IC39L270D9R JYK09F222ML72N Diode, 1A, 800V Diode, 1A, 200V Diode, 3A, 200V Diode, 0.15A, 75V Zener Diode, 5mA, 18V SMA SMA SMC SOD-123 SOD-123 Vishay Taiwan Semi ON Semi Diodes Diodes US1K-E3/61T ES1D MURS320T3 1N4148W BZT52C18-F Fuse, 250V, 2A Inductor, 4.7mH MOSFET, 7A, 650V Film RES, 1% Film RES, 1% Film RES, 1% Film RES, 1% Film RES, 1% Film RES, 5% Film RES, 1% Film RES,1% Film RES,1% Film RES,1% Film RES, 1% Film RES, 1% Film RES, 1% Film RES, 1% Film RES, 5% Film RES, 1% DIP DIP TO-220F 0603 0603 1206 0603 1206 1206 0603 1206 1206 1206 0603 1206 1206 0603 0603 0603 COOPER Any AUK Yageo Yageo Yageo Yageo Panasonic Yageo Yageo Royalohm Royalohm Royalohm Yageo Royalohm Royalohm Yageo Royalohm Yageo SS-5-2A STK0765BF RC0603FR-0780K6L RC0603FR-0722K1L RC1206FR-071ML RC0603FR-076K8L ERJ8ENF4993V RM12JTN104 RC0603FR-0720RL 1206F150KT5E 1206F330KT5E 1206F1005T5E RC0603FR-07100RL 1206F1001T5E 1206F100KT5E RC0603FR-07510RL RR1608(0603)L0R0JT RC0603FR-073KL Film RES, 5% 1206 Liz CR06T05NJ5K1 L P=2.2mH, N P:N S:N AUX=144:24:27 Offline LED Lighting Controller EFD20 SOIC8 Yangyang MPS NC NC EFD20 MP4021A NC FX0136 MP4021GS-A-Z www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 28 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER 5. EXPERIMENTAL RESULT All measurements performed at room temperature 5.1 Efficiency Vs Line Voltage Efficiency vs Line voltage Pin (W ) 10.09 9.93 9.76 9.65 9.59 9.51 9.48 9.43 9.46 9.5 9.53 9.59 9.64 Vo (V) 15.82 15.78 15.77 15.76 15.75 15.75 15.75 15.74 15.74 15.74 15.73 15.74 15.73 Io (mA) 512 509 507 506 505 504 504 503 502 503 503 504 504 efficiency (%) 80.28 80.89 81.92 82.64 82.94 83.47 83.73 83.96 83.53 83.34 83.02 82.72 82.24 85.00 84.00 83.00 Efficiency (%) Vin (VAC) 86 90 100 110 120 136 151 175 201 221 231 251 263 82.00 Efficiency 81.00 80.00 79.00 78.00 77.00 76.00 75.00 85 115 145 175 205 235 265 Vin (VAC) Figure 26— Efficiency Vs Input Line Voltage 5.2 Output LED Current Line Regulation Vin (VAC) 86 90 100 110 120 136 151 175 201 221 231 251 263 Io 512 509 507 506 505 504 504 503 502 503 503 504 504 (mA) Output Current Accuracy vs Line Voltage Output Current Accuracy (%) 5.00 4.00 3.00 2.00 1.00 0.00 -1.00 -2.00 -3.00 -4.00 -5.00 85 115 145 175 Vin (VAC) 205 235 265 Figure 27— Output Current Accuracy Vs Input Line Voltage 5.3 PF, THD VS Line Voltage Vin (VAC) 86 90 100 110 120 136 151 175 201 221 231 251 263 PF (%) 99.2 99.2 99.1 99 98.8 98.5 98.2 97.4 96.4 95.3 94.8 93.4 92.5 THD (%) Third harmonic (%) 14.9 14.8 14.8 15 15.1 15.1 15.2 16.5 16.7 16.7 16.9 16.8 17 14.2 14.2 14.1 14.3 14.4 14.5 14.5 15.2 15.4 15.4 15.4 15.4 15.5 AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 29 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER PF, THD vs Line Voltage 100 90 80 PF 70 THD % 60 Third harmonic 50 Class C limit of third harmonic 40 30 20 10 0 85 115 145 175 205 235 265 Vin (VAC) Figure 28— Output Current Accuracy Vs Input Line Voltage 5.4 Conducted EMI Figure 29— Conducted EMI performance at 220V AC input AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 30 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER 5.5 Steady State Figure 30— 110 VAC, Full Load Figure 31— 220 VAC, Full Load 5.6 Input Voltage and Current Figure 32— 110 VAC, Full Load AN059 Rev. 1.4 12/30/2013 Figure 33— 220 VAC, Full Load www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 31 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER 5.7 Boundary Conduction Operation ILED 200mA/div. VZCD 2V/div. ILED 200mA/div. VZCD 2V/div. VGATE 10V/div. VGATE 10V/div. VCS 1V/div. VCS 1V/div. Figure 32— 110 VAC, Full Load Figure 33— 220 VAC, Full Load 5.8 Start Up Figure 34— 110 VAC, Full Load AN059 Rev. 1.4 12/30/2013 Figure 35— 220 VAC, Full Load www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 32 AN059 –PRIMARY-SIDE-CONTROL WITH ACTIVE PFC OFFLINE LED CONTROLLER 5.9 OVP (Open load at normal operation) Figure 36— 110 VAC Figure 37— 220 VAC 5.10 SCP (Short LED+ to LED- at normal operation) Figure 38— 110 VAC AN059 Rev. 1.4 12/30/2013 Figure 39— 220 VAC www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 33 Design Guide for Replacing MP4021 with MP4021A The Future of Analog IC Technology ANNEX Design Guide for Replacing MP4021 with MP4021A Prepared by Zhijun Ye Feb 09, 2012 AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 34 Design Guide for Replacing MP4021 with MP4021A The Future of Analog IC Technology CONTENT A-1. INTRODUCTION.......................................................................................................................... 36 A-2. SUMMARY OF IMPROVEMENTS ............................................................................................... 36 A-3. ZCD OVER-CURRENT PROTECTION........................................................................................ 37 A-4. DESIGN EXAMPLE OF ZCD OCP CIRCUITRY .......................................................................... 38 A-5. BENCH TEST RESULTS............................................................................................................. 39 A-5.1. Steady State.................................................................................................................... 39 A-5.2. Short LED+ to LED- at Normal Operation ..................................................................... 39 A-5.3. Thermal Test at Output SCP .......................................................................................... 40 AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 35 Design Guide for Replacing MP4021 with MP4021A The Future of Analog IC Technology A-1. INTRODUCTION The MP4021/MP4021A is a primary-side-control offline LED lighting controller with PFC integrated. The MP4021A are designed to be a pin and functionality compatible chip with MP4021. The MP4021A is the improved revision of MP4021. This note is a guide to assist users of MP4021 converting existing designs to MP4021A and it summarizes the differences between MP4021 and MP4021A to be aware of for applications. For detailed information on the chips, please refer to the datasheets. The features in MP4021A that are not in conflict with those in MP4021 are not listed in this document. A-2. SUMMARY OF IMPROVEMENTS Compared with the MP4021, the MP4021A features four electrical characteristic improvements and one added protection function. They are all summarized in Table A-1. Table A-1—Functional Improvements Item MP4021 MP4021A Improvements 1. The Distribution of Feedback Voltage ±3.5% ±2.65% 2. The Lower COMP Clamp Voltage 0.9V 1.5V 3. The Gain of the Multiplier K=0.6 K=1 Prevent COMP saturation 4. VCC UVLO 12V / 8V 13.6V / 9V Raise GATE output voltage to increase driving capacity 5. Over-current Detector No Yes More reliable SCP Circuitry optimization to improve the accuracy of LED current regulation Item 1 to 4 almost have no impact on the existing MP4021 solutions. For Item 5, an additional SCP detector circuitry is applied to implement ZCD over-current protection for MP4021A’s solution. Figure A-1 shows a typical 8W LED Bulb driver application for universal input with MP4021A. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 36 DESIGN GUIDE FOR REPLACING MP4021 WITH MP4021A R6 100k C8 22nF/630V D1 NC EFD20 Np:Ns:Naux=144:24:27 Lp=2.2mH C4 33nF/400V BD1 DF06S R3 1M 1 R5 499k T1 D2 US1K R10 10M 8 2 3 5 D3 R13 1 47nF/275VAC CX2 R18 5.1k C5 100pF R4 6.8k L2 R19 4.7mH 5.1k L1 4.7mH CX1 68nF/275VAC F1 250V/2A RV1 275VAC 2 3 C6 C7 22uF/50V 100pF MULT FB VCC GND GATE CON2 C3 C1 470uF/35V NC CY1 R1 80.6k COMP 8 ZCD D6 BZT52C18 4 470uF/35V C2 MURS320R11 1M 4 1k ES1D D4 CS 2.2uF/10V 7 C10 C9 NC R7 5 R2 22.1k 20 Q1 STK0765BF 6 U1 MP4021A 2.2nF/250V C11 D5 1N4148 10pF R12 100 R8 1.5 R9 3.3 R14 1 CON1 Over-current Detector Circuitry R15 510 R16 3k D8 1N4148 Figure A-1—Universal Input, Isolated Flyback Converter, Drive 5 LEDs in Series, 500mA LED Current for 8W LED Bulb Lighting with MP4021A R15, R16 & D8 are used to monitor the OCP condition. The primary-side OCP threshold is set by the forward voltage of D8 and the divider ratio of R15 and R16. A-3. ZCD OVER-CURRENT PROTECTION Figure A-2 is the MP4021A Function Block Diagram of ZCD OCP Circuitry. Figure A-2—MP4021A Function Block Diagram of ZCD OCP Circuitry AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 37 DESIGN GUIDE FOR REPLACING MP4021 WITH MP4021A The MP4021A’s ZCD pin is multi-purpose. As over current detector, the MP4021A integrates a SCP comparator, shown in red block of Figure A-2. For primary-side control proposal, Rs is the primary sensing resistor which samples the primary current. Tie a resistor divider form CS sensing resistor to ZCD pin thru a diode, shown in blue block of Figure A-2. When the power MOSFET of the primary-side is turned on, the ZCD pin monitors the rising primary-side current, once the ZCD pin reaches OCP threshold, typical 0.6V, the gate driver will be turned off to prevent the chip form damage. And then the IC works at quiescent mode, the VCC voltage dropped below the UVLO which will make the IC shut down and the system restarts again. The primary-side OCP setting point can be calculated as: IPRI_ OCP ⋅ RS ⋅ R OCP2 − VD = 0.6V ROCP1 + ROCP2 Where IPRI_OCP is primary-side over current protection current value, VD is the voltage drop of the diode. ROCP1 and ROCP2 is used to program the over current protection threshold (IPRI_OCP). Please note that, when the MOS is turned on, the taps of the ZCD zero-current detector resistor divider and the OCP resistor divider are connected by a diode. So, to avoid the effect of the ZCD zero-current detector, the value of the resistors to set the OCP threshold (ROCP1 & ROCP2) should be about 10 times smaller than those of the ZCD zero-current detector (RZCD1 & RZCD2). A-4. DESIGN EXAMPLE OF ZCD OCP CIRCUITRY Take the solution of Figure A-1 for example. Step 1: Check the max VCS @ min input voltage for normal operation. (VCS_MAX) According to the bench test result, VCS_MAX @ 85VAC =1.2V Step 2: Set primary-side OCP point (VCS_OCP) to about 15%-20% higher than VCS_MAX. VCS_OCP = (1+20%) x VCS_MAX = 1.44V Since RZCD2=22.1kΩ, set ROCP2=3kΩ & the forward voltage of 1N4148 is about 0.6V Step 3: Set the ZCD OCP resistor divider by the equation: ROCP1 = VCS _ OCP ⋅ ROCP2 0.6 + VD − ROCP2 = 600Ω Here, set ROCP1=510Ω to get a lower threshold. Step 4: Verify the setting on the bench. For SCP, with lower primary-side OCP point, the system can earlier run into quiescent mode. But make sure to be left sufficient margin to avoid SCP mis-triggering at low line input. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 38 DESIGN GUIDE FOR REPLACING MP4021 WITH MP4021A A-5. BENCH TEST RESULTS Based on the solution of Figure A-1. A-5.1 Steady State For normal operation, the main difference is ZCD waveform when the primary-side MOS is turned on. With MP4021, the ZCD negative voltage is clamped to -0.6V by external ZCD diode D5. With MP4021A, the sampled CS voltage is added on ZCD pin thru the ZCD OCP circuitry. VCS 1V/div. ILED 200mAdiv. ILED 200mA/div. VZCD 2V/div. VZCD 2V/div. VGATE 10V/div. VGATE 10V/div. VCS 1V/div. (a) MP4021 solution (b) MP4021A solution Figure A-3— The Operation of Steady State @ 110VAC, Full Load A-5.2 Short LED+ to LED- at Normal Operation Once output short circuit occurs, the voltage of the auxiliary winding falls down following the output voltage of the secondary winding and then the VCC drops to lower than UV threshold and re-starts the system. The MP4021’s GATE keeps switching until VCC drops to UVLO. With MP4021A, as long as the primary-side over-current condition is detected, ZCD OCP is triggered and switching stops until the system re-starts again. VCS 2V/div. VCC 5Vdiv. VCOMP 5V/div. VGATE 10V/div. (a) MP4021 solution (b) MP4021A solution Figure A-4—The SCP Operation @ 220VAC, Full Load AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 39 DESIGN GUIDE FOR REPLACING MP4021 WITH MP4021A A-5.3 Thermal Test at Output SCP Table A-2—Thermal Test at Output SCP (Burn-in 0.5 hour@265VAC) (a) The solution with MP4021 (b) The solution with MP4021A Temp(℃) △ (℃) Differential inductor 29.4 6.7 BD1 package Bridge diode 30.5 7.8 11.6 BD1 pin Bridge diode 28.5 5.8 45.8 17.9 C1 Bulk Cap 25.2 2.5 83 55.1 T1 windings Transformer 28.9 6.2 Transformer 74.1 46.2 T1 core Transformer 28.6 5.9 U1 package MP4021 39.7 11.8 U1 package MP4021 27.2 4.5 U1 pin MP4021 39.6 11.7 U1 pin MP4021 28.1 5.4 D4 Output diode 116.7 88.8 D4 Output diode 30.3 7.6 R6 Snubber resistor 57.2 29.3 R6 Snubber resistor 34.3 11.6 C8 Snubber cap 61.4 33.5 C8 Snubber cap 36.1 13.4 D2 Snubber diode 55.2 27.3 D2 Snubber diode 33.5 10.8 Q1 MOSFET 45.6 17.7 Q1 MOSFET 29.7 7 R8, R9 Sense resistor 46.2 18.3 R8, R9 Sense resistor 30.6 7.9 Temp(℃) △ (℃) 33 Bridge diode RefDes Description 5.1 L1,L2 39.4 11.5 Bridge diode 39.5 C1 Bulk Cap T1 windings Transformer T1 core RefDes Description L1,L2 Differential inductor BD1 package BD1 pin The MP4021A solution is with ZCD OCP circuitry. Once output short circuit occurs, the system can works in hiccup mode, all the components are cool. Please consult datasheets and applications (AN038 and AN059) for details on the different electrical characteristics and performances between MP4021 and MP4021A. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. AN059 Rev. 1.4 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 40