AN045 Boost PFC Application Note Using The MP44010 The Future of Analog IC Technology MP44010 Boost PFC Application Note Prepared by Fei Wang / Jeffery Ding / Stone Lin Nov, 2011 AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 1 AN045 Boost PFC Application Note Using The MP44010 The Future of Analog IC Technology ABSTRACT This application note explains the basic operation of a boost PFC controller and provides a design example of the MP44010 operating with a wide input voltage and boundary conduction mode. The design example is described in detail with design parameters at the end of this application note. MP44010 Introduction The MP44010 is a boundary conduction mode PFC controller, designed to provide simple and high performance active power factor correction using minimum external components. The MP44010 provides two-step effective over-voltage protection that guarantees safe operation. The MP44010 features ultra-low start-up current and low quiescent current. To minimize distortion, a zerocrossing detection circuit is added to the output of multiplier of the MP44010. The MP44010 is integrated with an R/C filter on the current sense pin to filter out the leading edge noise. D4 L1 Vo R3 D2 D3 D1 R9 C2 R4 R5 C4 R6 R1 C5 Vac C1 U1 ZCS VIN COMP FB + R7 C6 Q1 MP44010 GATE MULT CS GND R10 R2 C3 R8 Figure 1—MP44010 Typical Application Circuit AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 2 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 INDEX Abstract ................................................................................................................................................. 2 MP44010 Introduction.............................................................................................................. 2 Boost PFC operation using MP44010 .................................................................................................... 4 ZCS (Zero Crossing Sensing) Block ............................................................................................... 4 Current Sense Block....................................................................................................................... 5 Multiplier Block ............................................................................................................................... 5 OVP (Over Voltage Protection) Block ............................................................................................. 6 Boost PFC DESIGN using THE MP44010 ............................................................................................. 7 Power Stage Design ....................................................................................................................... 7 a. Diode Bridge........................................................................................................................ 7 b. Input Capacitor .................................................................................................................... 8 c. Inductor................................................................................................................................ 8 d. Power MOSFET................................................................................................................. 11 e. Output Diode ..................................................................................................................... 11 f. Output Capacitor................................................................................................................. 11 Control Circuit Design................................................................................................................... 12 a. Start-up Resistor................................................................................................................ 12 b. VIN Bias Charge Circuit through Auxiliary Winding ............................................................ 12 c. MULT Resistor Divider ....................................................................................................... 12 d. Current Sense Resistor...................................................................................................... 13 e. ZCS Resistor ..................................................................................................................... 13 f. Feedback Resistor.............................................................................................................. 13 g. Compensation Network Design.......................................................................................... 14 Design Tips................................................................................................................................... 21 a. Reducing power dissipation ............................................................................................... 21 b. Improving power factor (PF). ............................................................................................. 23 Design example ................................................................................................................................... 23 Design of power stage components: ............................................................................................. 23 Design of control circuit:................................................................................................................ 25 References: ......................................................................................................................................... 28 AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 3 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 BOOST PFC OPERATION USING MP44010 The MP44010 senses the inductor current through the current sense pin and compares it to the sinusoidal-shaped signal, which is generated from the multiplier. When the external power MOSFET turns on, the inductor current rises linearly. When the peak current hits the sinusoidal-shaped signal, the external power MOSFET begins to turn off and the diode turns on. The inductor current also begins to fall. When the inductor current reaches zero, the power MOSFET begins to turn on again, which causes the inductor current to start rising again. The power circuit works in boundary conduction mode, and the envelope of the inductor current is sinusoidal-shaped. The average input current is half of the peak current, so the average input current is also sinusoidal-shaped. A high power factor can be achieved using this control method. The related blocks in the PFC circuit are described in detail in the following pages. ZCS (Zero Crossing Sensing) Block * * ZCS 5 Disable starter 2.1 1.35 S R Q Drive GATE 7 Figure 2—ZCS Block As the converter is running, the signal of the ZCS is obtained by the auxiliary winding on the boost inductor. When the inductor current reaches zero, the voltage across the inductor reverses. When the negative edge of ZCS is going from above 2.1V to below 1.35V, it triggers the MOSFET to turn on. Thus, the external MOS can be turned on with the negative-going edge. At start-up, when there is no signal present at the ZCS, an internal starter forces the driver to deliver a pulse to the gate of the MOSFET to perform the function. The ZCS pin is also used to activate the disable function. If the voltage on the ZCS pin is below 190 mV, the MP44010 will be shut down. As a result, its power consumption is reduced. To re-enable the chip operation, the pull-down must be released. AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 4 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 Current Sense Block The current comparator senses the voltage through the current sense resistor and compares it to the output of the multiplier to determine the exact time for turning off the external MOSFET. To avoid spurious switching of the MOSFET due to noise at the CS pin, an internal R/C filter is added to the CS pin. Multiplier Block R8 COMP 2 MULT 3 CS 4 CMP E/A 30mV Figure 3—Multiplier Block The multiplier has two inputs: one sees a partition of the instantaneous rectified line voltage and the other one sees the output of the E/A. If the E/A output voltage is constant during a half line cycle, the output of the multiplier will be shaped as a sinusoid and is the reference signal for the current comparator, which controls the peak current cycle by cycle. Figure 4—Multiplier Characteristics As shown in Figure 4, the multiplier circuit operates optimally in the linear region. The two parameters that need to be determined are COMP and the peak voltage of the MULT pin. The COMP voltage can AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 5 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 be measured at the output of the E/A. Once the COMP voltage is chosen, the peak voltage of the MULT pin should be set according to the linear curve in Figure 4. If MULT and CS do not follow the linear curve in Figure 4, the divider ratio of the line voltage or the sense resistor should be adjusted. If the circuit works in the linear region but does not cover the full range of the multiplier, either the divider ratio of the line voltage or the sense resistor can be increased to maximize the full range of the multiplier. Near the zero crossing of line, the output of the multiplier is close to zero, so there is no switching of the power MOSFET that results in input current distortion. A special circuit of 30mV offset that has been added to the output of the multiplier can optimize the input current THD. OVP (Over Voltage Protection) Block Vo COMP ΔI R9 R10 FB 1 2 E/A PWM 2.5V Drive 2.2V 40µA Figure 5—OVP Block The MP44010 provides two-step precise over-voltage protection (OVP), which is accomplished by monitoring the current flow through the COMP pin. At steady state, the voltage control loop keeps the output voltage close to the nominal value, set by the resistor divider R9 and R10. Neglecting the output ripple, the current through R9-IR9, equals that through R10-IR10. Given that the reference voltage is 2.5V, the voltage at the FB pin will be also 2.5V, and the current through R10 and R9 is calculated as follows: IR10 = AN045 Rev. 1.2 12/30/2013 V − 2.5 2.5 = IR 9 = o R10 R9 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 6 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 To achieve high PF, a compensation network is connected between FB pin and COMP pin. When the output load drops, an abrupt change of output voltage ΔVO>0 will take place. Because the voltage across R10 is fixed at 2.5V, the current through R10 will remain the same, then current through R9 becomes: I'R9 = Vo − 2.5+ΔVo . R9 The difference in current, ΔIR9=I’R9- IR10=ΔVo/R9, will flow through the compensation network and enter the E/A (COMP pin). The current is internally monitored by the MP44010. If the current exceeds 40μA, the dynamic OVP is triggered and the power MOSFET is turned off. This dynamic OVP condition is maintained until the current falls below approximately 10μA, at which point the inner starter is enabled and IC is allowed to restart. When the output load is very light, the output voltage tends to exceed the nominal value and increase gradually. Therefore, the dynamic OVP function will not be as effective. If this condition occurs, the E/A will saturate low and triggers the static OVP to turn off the power MOSFET. As the E/A returns to the linear region, the converter will resume operation. BOOST PFC DESIGN USING THE MP44010 This section discusses the different components of the boost PFC design as well as design example based on the MP44010 and given requirements. The definitions of frequently mentioned parameters through the following pages are summarized below. Input AC RMS voltage: Vac (Vac_min~Vac_max) Input RMS current: Iac Input power: Pin Output DC voltage: Vo Output power: Po Efficiency: η=Po/Pin Minimum switching frequency: fsw_min Switching frequency : fsw Peak inductor current: ILpk Power Stage Design a. Diode Bridge The diode bridge should withstand the maximum reverse input AC voltage and the maximum input current. Two of the criteria to be considered for selecting a diode bridge are the maximum instantaneous voltage, which is the peak voltage of the line voltage, and the maximum input RMS AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 7 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 current (which is the input RMS current at low line). In addition, package size, and thermal performance should also be considered. For handling line frequency current, a standard low-cost diode bridge with slow recovery can be used. b. Input Capacitor The input capacitor after the diode bridge is used to provide a bypass path for high switching frequency current and minimize fluctuation on the rectified sinusoidal input voltage. In general, a voltage drop up to 10% on the input capacitor may be expected. A worst case occurs under minimum input voltage due to the biggest current ripple, as shown in the equation below. Cin = Iac_ max 2π ⋅ fsw ⋅ r⋅ Vac_ min In the above equation, r is the coefficient (0.01~0.1) and fsw is the switching frequency at the peak of the minimum input AC voltage. A capacitor with good high frequency performance, such as ceramic cap or tantalum cap should be selected. c. Inductor For critical mode Boost PFC, the on-time of MOSFET can be written as below: Ton = L⋅ ILPK ⋅ sin(θ) 2 Vac sin(θ) = L⋅ ILPK 2 Vac From the above equation, one can see that the on-time is related to L, ILpk and Vac. For a given L and Po, Ton is constant when Vac is fixed. The off time of MOSFET can be written as: Toff = L⋅ ILPK ⋅ sin(θ) Vo − 2 Vac sin(θ) Fsw is 1/T, which equals 1/ (Ton +Toff), which can be described as the following equation. fsw (θ) = V 2 ⋅ (Vo − 2 Vac sin(θ)) 1 1 = ⋅ ac Ton + Toff 2 ⋅ L⋅ Pin Vo The minimum switching frequency occurs at the peak of AC input voltage. As the curve in Figure 6 shows, the switching frequency varies with input AC RMS voltage with the minimum frequency occurring at the peak of the AC input voltage. The curve is measured with Vac=85~265V, L=280μH at 150W output power. AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 8 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 fs w Vac Figure 6—Switching frequency vs. VAC As the above figure shows, the minimum frequency occurs at maximum input voltage. So the inductance should be calculated based on maximum input voltage: L= Vac_max 2 (Vo − 2Vac_max ) 2fsw_min ⋅ Pin ⋅ Vo The recommended value for fsw_min is above 20kHz (typically, 30~40 kHz) which is above the audible frequency. Once inductance is calculated, magnetic core size should be chosen according to the condition below: L ⋅ I Lpk ⋅I Lrms Ap = Ae ⋅ A w > Where ILrms = B max ⋅ K c ⋅ j ILpk 6 Ae is the effective area of the core section; Aw is the effective area of the core window; Bmax is the max swing of the magnetic flux density (generally Bmax=0.3~0.4T); Kc is the winding factor, which is about 0.3 in inductor design; j is the current density in the wire, which is typically 4A/mm2. With the selected core size, the inductor turn number is: Np = AN045 Rev. 1.2 12/30/2013 L ⋅ ILpk Bmax ⋅ A e www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 9 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 To avoid saturation of the core, air gap is necessary: σ= Np 2 ⋅ A e ⋅ μ L Where µ is the magnetic permeability. As previously described in this document, the zero current sensing of this MP44010 is performed by sensing the falling-edge of auxiliary winding of the inductor. Therefore, auxiliary winding turn number needs to be properly determined to guarantee normal operation of ZCS. The maximum turns ratio of main to auxiliary winding is: N= Vo − 2Vacmax ZCSrising_max Where: ZCSrising_max is the max rising threshold of ZCS. The real turn ratio should be not higher than the calculated value and the turn number of auxiliary winding is Ns = Np N . After complete the above design, the wire size should be properly chosen to minimize the winding conduction loss and the leakage inductance. The loss depends on the current value flow through the winding, the length of wire and the wire size. The wire size is determined by the RMS current flow through the winding. So the primary wire size should be: SP = ILrms j Due to the skin effect and proximity effect of the conductor, the diameter of the selected wire is generally less than 2*Δd. Δd is the skin depth: Δd= 1 π ⋅ fs_min ⋅ μ ⋅ G Where G is the conductivity of the wire (for copper wire, G is typically 6×107S/m. Usually, multiple strands of thinner wire or Litz wire is adopted to minimize the AC resistance. The effective cross section area of multi-strands wire or Litz wire should be large enough to meet the requirement set by the current density. After the wire size have been determined, it is necessary to double check whether the window area with selected core can accommodate the windings calculated in the pervious steps. If not, the core should be re-selected as former design steps. AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 10 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 d. Power MOSFET The voltage rating of MOSFET is determined by output voltage, OVP threshold, and some margin, such that VDS >Vo +ΔVOVP . The current rating of the MOSFET is determined by the RMS value of the current flowing through the MOSFET. The RMS current of MOSFET follows the below equation: IQrms =2 2Iac ⋅ 1 4 2 Vac − ⋅ 6 9π Vo In addition, the MOSFET pulsed- drain current should be higher than the peak inductor current. ID_pulse > ILpk e. Output Diode The boost diode should have the same voltage criteria as the MOSFET. The average current of output diode is the same with the output current of PFC regulator: IDo =Io And the RMS current could be calculated according to below formula to estimate the power consumption of the diode: IDrms =2 2Iac ⋅ 4 2 Vac ⋅ 9π Vo When the inductor current drops to zero, the diode will start to block the current. However, if the recovery speed of the diode is slow, the inductor current will continue to go negative, which affects efficiency and the circuit operation. Therefore, a diode with a fast recovery is recommended. f. Output Capacitor In general, two criteria for selecting output capacitor are output voltage ripple, ∆Vo, and hold-up time. Output ripple is a function of effective series resistance, ESR, of the capacitor, output current, Io, line frequency (fL), and output capacitance as shown in the equation below: Δ Vo = 2Io 1 + ESR2 2 (2π ⋅ 2 fL ⋅ Co ) The calculated ripple with the selected cap should be lower than the actual allowable output ripple. The capacitor should be chosen so that the hold-up time satisfies the following equation: Co = 2Pin ⋅ t hold Vo_min 2 - Vo_holdup 2 Where Vo_min is the minimum output voltage under all normal operating conditions and Vo_holdup is the required minimum operating output voltage that is needed to supply the downstream DC-DC converter when the line voltage is shut down. The maximum voltage at the output is a combination of output DC AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 11 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 voltage, output voltage ripple, and OVP threshold. Therefore, the voltage rating of the capacitor needs to be higher than this maximum output voltage at worst case. Control Circuit Design a. Start-up Resistor Under the condition of not using an external Vin power supply, a simple approach to handling start-up is by having a start-up resistor to connect to the rectified mains voltage. The IC will be off until Vin capacitor is charged higher than threshold through start-up resistor. According to required start-up time, the start-up resistor can be roughly calculated based on below equation: R start = Tstart ( 2Vac -VIN_th ) C vcc ⋅ VIN +Iq ⋅ Tstart Since the start-up resistor causes a voltage drop between the rectified AC voltage and the supply voltage of the chip, using a big value resistor helps to minimize the power dissipation due to I2R. b. VIN Bias Charge Circuit through Auxiliary Winding Generally, the current flow through the start-up resistor is not high enough during normal operation of the IC. A bias charge circuit connecting auxiliary winding could be used to power the IC, as shown in the typical application circuit in Figure 1. This circuit contains D2, D3, C2 and R4. In the figure, when the auxiliary winding voltage is positive, C2 will be charged through R4, and the charge current will also charge C3 through D2. At the same time, the Zener diode, D3, can avoid having too much charge voltage. When the auxiliary winding voltage is negative, C2 will be discharged through R4 and D3. D2 is reverse blocked. c. MULT Resistor Divider As mentioned earlier, the operation of the multiplier should be in linear region. For example, to keep the MULT pin voltage below 3V which is in the linear range of MULT voltage at maximum AC input condition, the MULT voltage under minimum AC input has to satisfy the following condition: VMULT_min =VMULT_max Vac_min Vac_max To prevent the output of the multiplier from saturating under minimum AC input voltage, the below condition must be met: VCS_max = 1.62 ⋅ VMULT_min < 1.6V Otherwise, the calculation has to be re-done with a lower MULT voltage. As to the resistor divider, the value should be as below: V R2 = MULT_max R1+R2 2Vac_max AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 12 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 d. Current Sense Resistor As discussed in the Multiplier section, the current flow through the MOSFET should be sensed by an external resistor. When the voltage on current sense resistor is equal to Multiplier output, the MOSFET will be turned off. The sensed voltage on current sense resistor should be less than the maximum output of the Multiplier, such that: RS =R8 ≤ VCS_max ILpk Where VCS_max is the maximum output of the Multiplier calculated in previous section. In addition, the current limit function can be realized when the voltage on sensing resistor is equal to the high-clamp voltage of CS pin. The max current limit is: Ilimit = VCS_clamp RS = VCS_clamp R8 When selecting a MOSFET, the current rating of the MOSFET is important. It needs to be able to handle a current higher than the current limit to avoid any damage to the MOSFET. e. ZCS Resistor The ZCS resistor connects the ZCS pin and auxiliary winding. The main purpose of the resistor is to avoid excessive voltage on the ZCS pin. Therefore, a minimum ZCS resistor is required to ensure that the ZCS pin voltage is lower than high clamp voltage under maximum auxiliary winding voltage: R5=R ZCS ≥ Vaux_max − VZCSclamp_H 2.5mA Where Vaux_max is the maximum voltage on auxiliary winding output voltage, which is Vo/N. VZCSclamp_H is the upper clamp voltage of the ZCS pin. Generally, R5 is not bigger than 100kΩ. f. Feedback Resistor Vo can be set by using the appropriate feedback resistors. Since the OVP threshold is sestet by using the high-side feedback resistor, R9. This resistor should be selected, which is calculated as: R9= ΔVOVP IOVP Where ΔVOVP is the dynamic OVP threshold above normal Vo and IOVP is dynamic OVP triggering current. The low-side feedback resistor can simply be calculated as: R10 = AN045 Rev. 1.2 12/30/2013 2.5 ⋅ R9 Vo − 2.5 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 13 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 g. Compensation Network Design Figure 7 shows the circuit block of control loop inside and outside of the MP44010. G PS(s) D4 L1 Vo D1 R1 Vac R5 C1 R9 Q1 + C6 LOAD R10 G PMW(s) R2 CS ZCS GATE Timer MP44010 ZCS Kp*Vac I Lpk *R8 Vcs MULT R8 S + PMW Comparator R Multiplier KM*VMULT*VCOMP G MULT(s) Q 2.5V VCOMP GND EA + - FB COMP G EA(s) Compensation network Figure 7—Control Loop Diagram of MP44010 Based on the above control loop diagram, the block diagram of voltage loop can be simplified, as is shown in the Figure 8. Vac Reference + - G EA(s) Error amplifier VCOMP Vac ZCS GMULT(s) Multiplier VCS G PWM(s) PWM Generation ILpk GPS (s) Power stage Vo H(s) Feedback Figure8—Block Diagram of Voltage Loop While Gvc(s) is the control to output transfer function, it can be calculated by: GVC (s) = GPS (s) ⋅ GPWM (s) ⋅ GMULT (s) The open voltage loop transfer function can be calculated by: T(s) = GVC (s) ⋅ GEA (s) Please note that H(s) is treaded as part of GEA (s) and H(s)=1 in this file. To design a high stability voltage loop, the crossover frequency (bandwidth) and the phase margin of T(s) need to be properly designed. The phase margin is usually designed to be larger than 30o in practical application, this can be achieved by designing compensate network of voltage error amplifier. Because PFC output has 2nd line frequency harmonics, it is coupled to the output of voltage error AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 14 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 amplifier and causing input current reference distortion. To get better THD and high PF, the voltage error amplifier should attenuate the 2nd line frequency and maintain its output voltage to a constant value. Therefore, the bandwidth usually is very low. As a rule of thumb, the bandwidth should not exceed 25Hz. The procedure to design the compensation is: Step 1: Calculate control to output transfer function Gvc(s) Control to output transfer function includes all components in voltage loop excluding error amplifier. Gvc(s) must be calculated before designing the voltage error amplifier compensation network. a). Calculate the transfer function of Multiplier The Multiplier output is the reference of inductor current. The relationship between COMP voltage and Multiplier output voltage is: VCS = K M ⋅ VMULT ⋅ VCOMP = K M ⋅ K P ⋅ 2Vac ⋅ VCOMP Where, KM is the gain of the multiplier and KM=0.64. KP is the ratio of the resistor divider of the input voltage, it can be calculated by: KP = R2 R1+R2 For a given Vac, the transfer function of Multiplier can be calculated: GMULT (s)= dVCS = KM ⋅ KP ⋅ 2Vac dVCOMP b). Calculate the transfer function of PWM The Ton is achieved by comparing voltage of Rs and multiplier output. Toff is achieved by ZCS circuit. The output of the multiplier is the control signal to control the inductor current through sensing the voltage signal on sensing resistor. In such low frequency we discussed here, the inner current loop can be considered as ideal, which means the inductor current always follow the reference signal, then the relationship between inductor current and reference signal could be got: Vcs = ILpk ⋅ R s = ILpk ⋅ R8 So the transfer function of PWM block could be expressed as: GPWM (s)= AN045 Rev. 1.2 12/30/2013 dILpk dVcs = 1 R8 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 15 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 c). Calculate the transfer function of power stage The power stage can be modeled as is shown in Figure 9 in the half line frequency cycle. It includes a controlled current source in parallel with the output capacitor Co and load resistor Ro. Re is the equivalent impedance which indicates disturbance of Vo. Figure 9—Small Signal of Power stage The model is derived based on power balance equation below. Io = I Iin ⋅ Vac V = Lpk ⋅ ac Vo 2 ⋅ 2 Vo In the period of half line frequency, Vac can be thought as constant for the small signal of control to voltage. Therefore, small signal of above equation is: io = I P Vin V V 1 ⋅ iLpk − Lpk ⋅ in2 ⋅ v o = ⋅ in ⋅ iLpk − o2 ⋅ v o Vo 2 ⋅ 2 Vo 2 ⋅ 2 Vo 2 ⋅ 2 Vo 1 ⋅ Re = Assume, Then we can get Vo2 Po V v 1 ⋅ in ⋅ iLpk =i0 + o Re 2 ⋅ 2 V0 The small signal is got based on above equation. The transfer function of the power stage can be derived as: GPS (s)= While And AN045 Rev. 1.2 12/30/2013 dVo dVo dIo = ⋅ dILpk dIo dILpk dIo Vac = dILpk 2 2Vo dVo 1 = Zo = Ro // R e // dIo sCo www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 16 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 If PFC downstream with a DC/DC converter, when load is changing, the input current of the cascaded DC/DC varied inversely with input voltage, the characteristic is similar to a constant power load within the bandwidth of DC/DC converter. Therefore, Ro = − Vo2 Po Ro is opposite in phase to Re, so the effect of Ro and Re can be ignored. GPS(s) can be calculated by: GPS (s)= 2 Vac 1 ⋅ ⋅ 4 Vo s ⋅ Co If PFC downstream with a resistive load, then, Vo2 Ro = Po So Ro equals to Re, GPS(s) can be calculated by: GPS (s)= 2 Vac ⋅ ⋅ 8 Vo Ro s ⋅ Ro ⋅ Co 1+ 2 Finally, the transfer function of the control-to-output can be got with: GVC (s) = GPS (s) ⋅ GPWM (s) ⋅ GMULT (s) For constant power load, For resistive load, GVC (s) = GVC (s) = 1 KM ⋅ KP ⋅ Vac 2 1 ⋅ ⋅ 2 Rs ⋅ Vo s ⋅ Co 1 K M ⋅ K P ⋅ Vac 2 Ro ⋅ ⋅ ⋅ 4 Vo Rs 1 s ⋅ Ro ⋅ Co 1+ 2 Due to large Co, the pole frequency of Gvc(s) is very low, usually 1~2Hz, the difference of Gvc(s) between resistive load and constant power load appears in low frequency phase, while the gain is almost the same. Considering the resistive load is rarely happened to PFC, so only constant power load is taking into account for further designing. Step 2: Determine Compensation Network Type Bode plot is widely used to access the stability based on the phase and gain margin of open loop gain T(s). As shown in the Figure 10. AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 17 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 Figure 10—Gain margin and phase margin Definition Criteria for accessing loop stability: a). Phase margin: >45o. b). Gain margin: >15dB. c). Generally, the gain slope of T(s) at crossover frequency fc is -20dB/dec. d). High gain at lower frequency will make better regulation accuracy. Therefore, we can draw the bode plots of the GVC(s) with constant power load, as is shown in Figure 11. Figure 11—Bode Plots of GVC(s) From Figure11 to see, the DC gain of the GVC(s) is high enough for good regulation accuracy. But the phase margin (PM) of GVC(s) is always 900, and the crossover frequency fc_VC is hundreds of Hertz. Bode plot of the 3 types compensation networks are analysis based on the given GVC(s). AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 18 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 Type-1 compensation network includes a proportion and a pole, as shown in the Figure 12. This type of compensation can provide larger than 45o phase margin, but its drawback is the gain at lower frequency would be limited. This would cause worse load regulation. Figure 12—Bode Plots of Type1 Compensation Network Type-2 compensation network with a pole and a zero is shown in the Figure 13. This type of compensation can provide larger than 45o phase margin and high DC gain. Comparing with type-3, it is not very easy to get very high gain margin for type-2 compensation network at two times of line frequency (2fL).Therefore, the ability of attenuating 2nd line frequency harmonic at the input of E/A is a little weaker than type-3. Therefore, this type compensation network is always used in such application that PF requirement is not very strict. Figure 13—Bode Plots of Type2 Compensation Network Type-3 compensation network includes two poles and a zero, as shown in the Figure 14. This type of compensation can provide larger than 45o phase margin and high DC gain. The pole with higher frequency is selected to provide enough gain to attenuate 2nd line frequency harmonic at input of E/A. Therefore, the THD and PF can be further improved. AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 19 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 Figure 14—Bode Plots of Type3 Compensation Network Step 3: Calculate Compensation Network The compensation network with two poles and a zero is selected as an example. The transfer function of the voltage error amplifier is: GEA (s)= 1+s ⋅ R6 ⋅ C4 C4 ⋅ C5 ⎞ ⎛ s ⋅ R9 ⋅ ( C4+C5 ) ⋅ ⎜ 1+s ⋅ R6 ⋅ ⎟ C4+C5 ⎠ ⎝ The procedure for compensation calculation is: Firstly, determine the crossover frequency (fc) of T(s). Generally, fc is about 1/10~1/5 of 2 fL (fL is line frequency). Secondly, determine the position of fcz. If fcz equals to fc, then phase margin of H(s) would be 45o; if we want the phase margin is larger than 45o, and then the fcz would be set to be smaller than fc, as is shown in the figure14. 1 =fc 2 ⋅ π ⋅ R6 ⋅ C4 GEA (fcp ) = GVC (fc ) fcz = And Thirdly, the value of G EA (2f L ) can be determined to attenuate 2nd line frequency harmonic. Due to slope of G ea (f) is -20dB/div from fcp to 2fL, therefore, below relationship is valid: GEA (fcp ) − GEA (2fL ) fcp =2 ⋅ fL ⋅ 10 And fcp = Finally, fI = AN045 Rev. 1.2 12/30/2013 20 1 1 ≈ (C4>>C5) 2 ⋅ π ⋅ R6 ⋅ (C4//C5) 2 ⋅ π ⋅ R6 ⋅ C5 1 1 ≈ 2 ⋅ π ⋅ R9 ⋅ (C4+C5) 2 ⋅ π ⋅ R9 ⋅ C4 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 20 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 fI can be selected at very low frequency, due to R9 is a known value, so base on above formulas, C4, R6 and C5 can be calculated. Design Tips a. Reducing power dissipation 1) For the PFC stage, an NTC resistor is widely used to avoid high inrush current. When the circuit enters steady state, the resistor continuously generates power loss. To reduce this part of power loss, it is suggested that the NTC resistor is placed between the rectified diode and output cap because there is less current flowing through the NTC resistor. 2) There is some power loss associated with the EMI filter; it is mainly due to the resistance of CM choke and DM choke. Therefore, using chokes with low resistance is recommended. 3) Start-up resistor also continuously generates power loss. As start-up resistor selection section on Page 12 described, the start-up resistor is selected based on acceptable start-up time. That means shorter start-up time is, bigger power consumption on start-up resistor is (see figure (1) as below). So in some cases, the power loss caused by start-up resistor may be very considerable. Therefore, a fast start-up circuit is recommended to shorten start-up time and reduce power consumption (see figure (2) as below): (1) Start-up using start-up resistor (2) Start-up using high-voltage current source Figure15—Start-up circuit AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 21 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 During start-up, the GS voltage of Q1 is clamped by zener diode due to no voltage on Cvcc. So Cvcc could be charged by Q1 and RB. When the voltage of Cvcc reaches to setting value, Q1 could be turned off so that the power consumption could be sharply reduced. 4) At light load, the downstream stage would run into burst mode. Therefore, the power loss of PFC stage can be reduced by synchronized ON/OFF of the PFC stage and the downstream stage. For example, MP44010 can be synchronized by HR1000 to reduce the light load power loss. Figure 12 shows the recommended circuit. Figure 16—Circuit to synchronize between MP44010 and HR1000 at light load 5) At light load, the power loss can be further saved by inserting LN60A01 to disconnect the resistor of voltage divider. The implement circuit is shown in the Figure 17. Figure 17—Power Consumption Reduction with LN60A01 AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 22 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 At light load, the pin 9 (PFC) of HR1000 is asserted low when it operates at burst mode, and the signal generated from pin 9 is applied to synchronize the ON/OFF of MP44010; it also can drive LN60A1 to connect or disconnect resistor of voltage divider at the same time. And the control signal of LN60A01 also can be external signal from MCU system. It’s important to select proper R11, because at light load, R11 could affect OVP of MP44010. To avoid triggering dynamic OVP wrongly, R11 should be chosen to follow the below equation: R10 Vbus_OVP -2.5 R11 ≥ R9+R10 40 ⋅ 10-6 b. Improving power factor (PF). Having a low enough bandwidth can guarantee that PF is not affected by output ripple. The EMI filter is also important for PF. Too large of an X-cap for the DM filter can cause big phase shift of input current and result in poor PF, especially at high line condition. Therefore, under the same EMI performance, smaller X-cap helps to provide good PF. If having a big X-cap is necessary, a small cap from MULT pin to GND is recommended to improve PF at high line. This cap is used to compensate the phase shift of input current caused by X-cap. There will be trade-offs with this since this technique may lower the PF at low line. DESIGN EXAMPLE Input AC RMS voltage: Vac=220V (Vac_min=85V─Vac_max=265V) Output DC voltage: VO = 400V Output voltage ripple: VO_ripple≤10V Output voltage OVP threshold: ΔOVP=40V Output power: PO=100W (constant power load) Efficiency: ηmax=97%, ηmin=93% Minimum switching frequency: fsw_min=40kHz Design of power stage components: (1) Bridge Diode The maximum input RMS current is: Iac_ max = Po = 1.265 (A) ηmin ⋅ Vac_min (1) To provide enough margin, GBU406 (600V/4A) is selected. (2) Input capacitor By setting the coefficient r as 0.05, the input capacitance can be obtained by using the formula below: AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 23 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 Cin = Iac_ max 2π ⋅ fsw ⋅ r⋅ Vac_ min = 1.03 × 10−6 (F) (2) A 1μF tantalum capacitor with 450V voltage rating is selected as the input capacitor to provide high frequency energy during switching cycle. (3) Inductor The inductance should be calculated based on the given specs: Vac_max 2 (Vo − 2Vac_max ) ⋅ ηmax L= = 5.4 × 10 −4 (H) 2fsw_min ⋅ Po ⋅ Vo Set the inductance as 550μH. (3) The needed Ap is: A p =A e ⋅ A w = L ⋅ ILpk ⋅ ILrms Bmax ⋅ K c ⋅ j = 6.84 × 10−9 (mm4) (4) Consider EI core, the EI30 core is selected according to above Ap. The inductor turn number is: Np = L ⋅ ILpk Bmax ⋅ A e = 51(Turn) (5) The needed air gap is: Np 2 ⋅ A e ⋅ μ = 6.54 × 10 −4 (m) L The maximum turn ratio of main to auxiliary winding is: V − 2Vac Nmax = o = 10.9 ZCSrising_max σ= (6) (7) With some margin, the turn ratio is set as N=6. And the turn number of auxiliary winding is: Ns = Np N = 8 (Turn) (8) (4) Power MOSFET The maximum RMS current of MOSFET is: IQrms_max =2 2Iac_max ⋅ 1 4 2 Vac_min − ⋅ = 1.26 (A) 6 9π Vo (9) The pulsed-drain current should be: ID_pulse > ILpk = 3.578 (A) (10) The CoolMOS IPP50R350CP (500V/9A) is selected to meet the power requirement of the design. (5) Output diode The average current of the output diode is: AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 24 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 IDo =Io = Po = 0.25(A) Vo (11) Super-fast recovery diode MUR160 (600V/1A) is selected to meet the design. (6) Output capacitor Here, the output capacitor is selected only based on output voltage ripple and ESR of output capacitor is assumed as 0.2Ω: 1 Co = 2 ⎛ Δ Vo ⎞ 2 2π ⋅ 2 fline ⎜ ⎟ − ESR ⎝ 2Io ⎠ The E-cap (450V/100μF) is selected as the output capacitor. = 8 × 10−5 (F) (12) Design of control circuit: (1) Calculate start-up resistor With 3s start-up time, the start-up resistor can be roughly calculated as: Rstart = Tstart ( 2Vac -VIN_th ) Cvcc ⋅ VIN +Iq ⋅ Tstart = 1.27 × 106 (Ω) (13) A 1MΩ resistor is selected to meet the calculation. (2) Calculate MULT resistor divider Maximum MULT pin voltage should be selected within the linear operating range (0~3V). Considering some margin, the maximum MULT pin voltage is set as 2.5V. So: VMULT_min =VMULT_max Vac_min Vac_max = 0.8 (V) (14) Then maximum CS pin voltage can be calculated as: VCS_max = 1.62 ⋅ VMULT_min < 1.6V (15) The below value is lower than CS clamp voltage (1.6V). The MULT resistor divider ratio can be obtained using the below equation: V R1 = MULT_max R1+R2 2Vac_max (16) Select 1.5MΩ as R1 and 10kΩ as R2. (3) Calculate current sense resistor R8 Based on the above calculation, the current sense resistor should meet: V R8 ≤ CS_max = 0.363 (Ω) ILpk AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. (17) 25 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 Select 0.3Ω as sensing resistor to meet the above design. (4) Calculate ZCS resistor R5 The ZCS resistor should meet the below equation: Vaux_max − VZCDclamp_H R5 ≥ 2.5 × 10 −3 = 1.688 × 10 4 (Ω) (18) Select 68kΩ resistor as the ZCS resistor. (5) Feedback resistor divider ΔVOVP (19) = 1× 106 (Ω) IOVP Select a 1MΩ resistor as a high-side feedback resistor. In addition, attention to the package size of this R9= resistor is needed, due to its power loss. 2.5 ⋅ R9=6.29 × 103 (Ω) Vo − 2.5 Select 6.34kΩ resistor as low-side feedback resistor. R10 = (20) (6) Calculate compensation circuit Based on the above parameter calculation, the compensation network can be calculated according to small signal model analysis in previous section. Step1: Set design goal, fc=15Hz, fI=0.1Hz, GEA(2fL)=-50dB and fcz=10Hz. Then C4 and R6 can be calculated: 1 =1.592 ⋅ 10−6 (F) 2 ⋅ π ⋅ R9 ⋅ fI (21) 1 =9.947 ⋅ 103 (Ω) 2 ⋅ π ⋅ fcz ⋅ C4 (22) C4= Selecting C4=1.6uF R6= Selecting R6=10kohm Due to G VC (f c ) =43.154 dB, then fcp can be calculated. GEA (fcp ) − GEA (2fL ) fcp =2 ⋅ fL ⋅ 10 20 =45.465 (Hz) (23) So C5 can be calculated too: C5 ≈ 1 = 3.159 ⋅ 10 −7 (F) 2 ⋅ π ⋅ R6 ⋅ fcp (24) Selecting C5=0.33uF Finally, the bode plots of GVC(s), GEA(s) and T(s) are shown in the below figure: AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 26 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 Figure 18—Final Bode Plot of the Compensation Network From Figure18, we can see the fc is change to 20Hz, the reason is using the simplified formula to calculate it. The phase margin is about 45o, the result can meet our design target. The final schematic of the design is shown in the Figure 19. Figure 19—100W Boost PFC Design Example AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 27 AN045 –BOOST PFC APPLICATION NOTE USING THE MP44010 REFERENCES: [1]. Lloyd H. Dixon, “Magnetics Design for Switching Power Supplies,” in Unitrode Magnetics Design Handbook, 1990. [2]. Yuri Panov and Milan M. Jovanovic, “Small-Signal Analysis and Control Design of Isolated Power Supplies with optocoupler feedback,” IEEE trans. Power Electronic., vol.20, NO.4, pp. 823-832, July 2005. [3]. Robert W. Erickson and Ragan Maksimovic, Fundamentals of Power Electronics (Second Edition). Kluwer Academic Publishers, 2001 [4]. MP44010 Datasheet-MPS NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. AN045 Rev. 1.2 12/30/2013 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. 28