AN084 Switching Mode Power Supply Design with 900V Switching Regulator－MP110 The Future of Analog IC Technology Application Note for Switching Mode Power Supply Design with 900V Switching Regulator---MP110 Prepared by Hui Li June, 2014 AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 1 AN084 Switching Mode Power Supply Design with 900V Switching Regulator－MP110 The Future of Analog IC Technology ABSTRACT This paper presents design guidelines for switching mode power supply using 900V switching regulator-MP110 from MPS, including Flyback and Buck converter as shown in Figure-1 and Figure-2. MP110 is the industry’s first 900V monolithic regulator. A programmable PWM controller and 900V planar power MOSFET are combined in single chip. The design is quite simple and straightforward with the help of step-by-step design procedure described in this application note. Experimental results based on the design example are also presented in the last part of section 3 and section 4. Figure-1 Flyback Converter with 900V Switching Regulator—MP110 Figure-2 Buck Converter with 900V Switching Regulator—MP110 AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 2 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 INDEX 1. 2. 3. 4. 5. MP110 INTRODUCTION ........................................................................................................................................ 4 PULSE WIDTH MODULATION (PWM) CONTROL INTRODUCTION ........................................................... 4 FLYBACK CONVERTER DESIGN PROCEDURE ............................................................................................ 5 A. Predetermined Input and Output Specifications ................................................................................... 5 B. Determine the Startup Circuitry ................................................................................................................. 7 C. Turns Ratio-N, Primary MOSFET and Secondary Rectifier Diode Selection.................................. 8 D. Determine Switching Frequency.............................................................................................................. 10 E. Current Sensing Resistor Design ............................................................................................................ 11 F. Primary Side Inductance Lm Design ...................................................................................................... 14 G. Input Over Voltage Protection Function ................................................................................................ 15 H. Transformer Design .................................................................................................................................... 16 H-1. Transformer Core Selection ................................................................................................................. 16 H-2. Primary and Secondary Winding Turns.............................................................................................. 16 H-3. Wire Size................................................................................................................................................. 16 H-4. Air Gap .................................................................................................................................................... 17 I. RCD Snubber Design .................................................................................................................................. 18 J. Output Diode Design................................................................................................................................... 21 K. Output Filters Design .................................................................................................................................. 21 L. Thermal Performance Check .................................................................................................................... 22 M. PCB Layout .................................................................................................................................................... 23 N. Design Flow Chart ....................................................................................................................................... 24 O. Experimental Verification .......................................................................................................................... 25 BUCK CONVERTER DESIGN PROCEDURE .................................................................................................. 32 A. Predetermine the Input and Output Specifications............................................................................. 32 B. Determine Switching Frequency and Operation Mode ...................................................................... 32 C. Inductor and Sensing Resistor Design .................................................................................................. 33 D. Freewheel Diode........................................................................................................................................... 36 E. Output Capacitor Design ........................................................................................................................... 36 F. Vcc Power Supply and Power Feedback Circuit Design ................................................................... 37 F-1. VCC Charge Diode Selection .............................................................................................................. 37 F-2. VCC Capacitor Selection ...................................................................................................................... 37 F-3. Zener Diode Selection ........................................................................................................................... 37 G. Thermal Performance Check .................................................................................................................... 38 H. Design Flow Chart ....................................................................................................................................... 40 I. Experimental Verification .......................................................................................................................... 40 REFERENCES ....................................................................................................................................................... 45 AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 3 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 1. MP110 INTRODUCTION MP110 is a monolithic regulator with programmable pulse width modulation (PWM) controller, 900V power MOSFET and high voltage current source in one chip. Based on the PWM technique, the switching frequency is fixed and doesn’t have much influence on other frequency band. When the load is below a given level, the regulator enters burst mode. As a result, it is prone to be used in the applications that are sensitive to noise, or need excellent light load efficiency and no load power consumption. Internal Vcc Under Voltage Lockout (UVLO), Over Load Protection (OLP), Vcc Over Voltage Protection (Vcc OVP), Short Circuit Protection (SCP), Input Over Voltage Protection (Input OVP) and Thermal Shutdown (TSD) are all implemented in the IC to provide full protection features and minimize the external component count. This paper presents practical design guidelines for off-line Flyback converter and Buck converter employing MP110. Step-by-step design procedure for PWM controlled Flyback converter and Buck converter using MP110 is introduced in this application note, mainly including transformer design, output filter design, component selection, thermal consideration, PCB layout and EMI design. 2. PULSE WIDTH MODULATION (PWM) CONTROL INTRODUCTION PWM control is typical fixed frequency control scheme for Flyback converter. By implementing a fixed switching frequency mode control, the switching frequency is fixed and the peak current is regulated by FB voltage according to the required output power. During the ON time of the MOSFET, the Drain-Source current increases. Once the current reaches the regulated peak current limit, the MOSFET is turned off. The peak current limit decreases as the output power decreases. If the output power decreases in further, the controller enters burst mode for lower no load power consumption. The switching frequency of MP110 is programmable and can be set up to 300kHz. It is easy to set the proper switching frequency to avoid specified frequency band. Figure-3 shows the Drain-Source voltage waveform of primary switch in a PWM control Flyback converter. During the ON time of MOSFET, the Drain-Source current increases linearly until the peak current limit is reached. Then the MOSFET turns off. The leakage inductance of the Flyback transformer rings with the parasitic capacitance and causes a high voltage spike, which should be limited by a clamping circuit. When the one cycle elapses, the MOSFET turns on again and next period begins. AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 4 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 N:1 + VOUT - + Rsn C sn VBUS Dsn ID + Vds - - vds ID ILIMIT Figure-3 Key Waveforms of Flyback Converter 3. FLYBACK CONVERTER DESIGN PROCEDURE A. Predetermined Input and Output Specifications - Input AC voltage range: Vac(min), Vac(max), for example 85Vac~420Vac RMS - DC bus voltage range: Vin(min), Vin(max). - Output: Vo , Io(min), Io(max), Pout - Estimated efficiency: η, It is used to estimate the power conversion efficiency to calculate the maximum input power. If there is no reference data, η is set to be 0.7~0.75 for low output voltage applications and 0.8-0.85 for high output voltage applications. - Estimated efficiency of transformer to output: ηps, 0.85 for low output voltage applications and 0.9 for high output voltage applications. . Then the maximum input power can be given as: Pin = AN084 Rev. 1.0 7/9/2014 Pout η www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (1) 5 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Figure-4 shows the typical DC bus voltage waveform. The DC input capacitor Cin is usually set as 2μF/W for the universal input condition. For 230V single range application, the capacitance can be half the value. Vin VDC(max) DC input Voltage VDC(min) AC input Voltage T1 t Figure-4 Input Voltage Waveform From the waveform above, the DC input Voltage VDC can be got as: VDC ( Vac ,t ) = 2 ⋅ Vac 2 − 2 ⋅ Pin ⋅t Cin (2) By setting VAC=VDC, T1 where DC bus voltage reaches to its minimum value VDC(min) can be calculated as VDC(min) = VDC ( Vac(min) ,T1) (3) Then, the minimum average DC input voltage Vin(min) can be derived as: Vin(min) = 2 ⋅ Vac (min) + VDC(min) 2 (4) The maximum DC input voltage Vin(max) can be got as: Vin(max) = 2 ⋅ Vac(max) (5) According to the calculation above, the maximum voltage is 594VDC and the maximum voltage rating of electrolytic capacitor is usually 400V or 450V, so two electrolytic capacitors are needed for application with such high input voltage. The two electrolytic capacitors should stack as input filter. The capacitance of two stacked capacitors is equal to half value of each one. So the capacitance of each stacked capacitors should be double of the calculated capacitance. Also balancing resistors are needed in parallel with the capacitors. The structure of input capacitors is shown in Figure-5. AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 6 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Figure-5 Input Stack Capacitor Circuit Both C1 and C2 endure half of input DC voltage. The R1~R4 should be used with the same resistance to balance the C1, C2 voltage stress. And the R1~R4 is recommended to use the 1206 package considering safety requirement. Also, the R1~R4 value should be large enough for energy saving. For example, 20MΩ balancing resistor consumes about 18mW at 600VDC bus voltage. B. Determine the Startup Circuitry AC Input * Drain 5 4 Vcc 3 MP110 7 2 8 1 C1 Figure-6 MP110 Startup Circuit Figure-6 shows the startup circuit. When power is supplied, the internal high voltage current source (typical 2mA) charges C1 through Drain of MP110. Once VCC voltage reaches 11.7V, the internal high voltage current source (2mA) turns off and IC starts switching, then the auxiliary winding takes over the power supply. If VCC drops below 8.0V before the auxiliary winding takes over the power supply, the switching stops and the internal high voltage current source turns on again, which re-charges the VCC AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 7 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 external capacitor C1, another start-up procedure starts (see Figure-7). Vcc Regulation Occurs Here Auxiliary Winding Takes Charge 11.7 V 8.0 V Drain Switching Pulses Figure-7 Startup Waveform and VCC UVLO of MP110 C. Turns Ratio-N, Primary MOSFET and Secondary Rectifier Diode Selection Figure-8 shows the typical voltage waveform of the MP110 Drain-Source and secondary rectifier diode in a Flyback converter. From the waveform, the primary Drain-Source voltage rating Vds can be derived as, Vds = Vin(max) + N ⋅ (VO + VF ) + 60V Where VF is the forward voltage of the rectifier diode, 60V spike voltage is assumed here. secondary rectifier diode voltage rating Vka can be estimated as equation (7): Vka = AN084 Rev. 1.0 7/9/2014 Vin(max) N + VO www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (6) The (7) 8 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Vds Spike N*(VO+VF) Vin(max) Vka Vin(max) /N VO Figure-8 Voltage Waveforms of MP110 Drain-Source and Secondary Rectifier Diode From equation (6) and (7), the voltage rating for MP110 Drain-Source and secondary rectifier diode versus turns-ratio N can be calculated and their relationship is shown in Figure-9. Figure-9 Voltage Rating of MP110 Drain-Source and Secondary Rectifier Diode Generally, 10% voltage margin needs to be left for primary MOSFET and secondary rectifier diode. For example, in 90Vac~420Vac input, 12V output adapter application, the turn ratio N can be selected from 8-12 and 100V rectifier diode is preferred for better performance. N=9 or 10 is preferred to be selected considering MP110 and secondary rectifier diode voltage derating. AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 9 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 D. Determine Switching Frequency The switching frequency of MP110 is programmable and maximum switching frequency is 300kHz. Higher switching frequency means smaller transformer core and tighter PCB area, but brings larger switching loss. Figure-10 Turn-On and Turn-Off Loss Figure-10 shows the turn-on and turn-off loss during switching period. The large current spike during turn on is caused by the large parasitic capacitance of 900V integrated MOSFET and the transformer. So the turn-on loss is much larger than turn-off loss at high line for MP110. Suppose the turn-on loss in T0-T1 is EON and the turn-off loss in T2-T3 is EOFF, the total switching loss can be calculated as equation (8). (8) PS = (EON + EOFF ) ⋅ fS Where fS is the switching frequency. Conducted EMI should be other aspect to be considered. The conducted EMI swept frequency range is from 150kHz-30MHz, and doesn’t let 2nd harmonic fall in this range is a good choice. Generally, around 65kHz switching frequency is recommended for MP110 when the output power is about 5W or higher. Higher switching frequency can be set to achieve higher power density and tight dimension, if the output power is low. The switching frequency can be set simply by choosing the FSET resistor. The relationship of FSET resistor and switching frequency is shown as equation (9). fs = 1 200 × 10 −9 + 112.5 × 10 −12 R × FSET VFSET Hz (9) Where VFSET (typical 1.23V) is the reference voltage of FSET. MP110 also provides the frequency jittering function which can simplifies the EMI input filter design. MP110 has the optimized frequency jittering with ±4% frequency deviation and 256Ts carrier cycle, which can effectively improve EMI performance. AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 10 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 E. Current Sensing Resistor Design The peak current is sensed by a sensing resistor. The peak current limit increases as the load increases, and is controlled by FB voltage, as shown in Figure-11. Figure-11 Relationship of Current Sensing Voltage and Load The relation between peak current limit and FB voltage is, Ipeak ⋅ Rsense = VFB Idiv (10) Where Idiv is the FB current-set-point division ratio. The maximum peak current limit is internally set to be 0.96V, and in order to avoid the sub-harmonic oscillation in Continuous Conduction Mode (CCM), the slope compensation function is implemented in the chip. The primary side peak current can be set by choosing proper current sensing resistor. Figure-12 Slope Compensation Waveform Figure-12 shows the relationship of peak current sensing voltage and the primary side ON time when MP110 delivers the maximum power. When the sum of the sensing voltage and the slope compensation voltage reaches the internal peak current limit VCS (0.96V, typical), MP110 turns off the internal MOSFET. The maximum peak current limit is VCS and the slope compensation slew rate SRamp is 40mV/μs. Considering the margin, use 95% of maximum peak current sensing level as the peak current limit at full load. The voltage on sensing resistor can be derived as, Vsense =0.95 ⋅ 0.96V-SRamp ⋅ TON (11) Where TON should be the MP110 maximum ON time at low line. With a given power supply spec, the converter operation mode need to be selected firstly. Usually, BCM (Boundary Current Mode) is preferred for the low output power application. CCM is selected when the power level is high. The higher the power delivers, the deeper CCM should be adopted for higher AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 11 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 efficiency and better thermal performance. But it must be kept in mind that the deeper CCM means larger transformer core. If power supply is designed to operate in BCM at low line, it operates in DCM at high line. The magnetizing inductor current (the primary inductor current when primary side is turned on, and the current reflected to the primary side when secondary side diode on) and the Drain-Source voltage of MP110 is shown as Figure-13. Inductor Current (A) Iprimary Isecondary/N IPeak VDS Tsecond Low Line Inductor Current (A) Iprimary Isecondary/N IPeak VDS Tsecond High Line T Figure-13 Inductor Current and Voltage of MP110 Drain-Source at Different Line AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 12 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Since the primary side switching ON time decreases as the input voltage increases, the parameters should be designed at low line to guarantee the converter can deliver the required output power. Since N has been selected, so if the power supply is designed to operate in boundary current mode (BCM) at low line, the peak current can be calculated easily as equation (12). Ipeak _ BCM = 2 ⋅ Io N ⋅ (1 − D Vin _ min ) (12) Where D is the duty of the switching, it can be derived from equation (13). D Vin _ min = (Vo + VF ) ⋅ N Vin_ min + (Vo + VF ) ⋅ N (13) Where VF is the forward voltage drop of secondary side diode. The ON time at low line can be calculated according to equation (14). TON = D Vin _ min (14) fs Then the sensing voltage VSense and peak current Ipeak_BCM can be calculated based on equation (11), (13) and (14), and sensing resistor can be got by equation (15). RSense = VSense (15) Ipeak_BCM If the peak current set by current sensing resistor is larger than Ipeak_BCM, the power supply always works in DCM. Otherwise, the power supply may enter CCM as Figure-14 shows. Here, Kdepth is defined as the depth of CCM. K depth = ΔI Ipeak (16) IMosfet Ipeak ΔI Ivalley Figure-14 Primary Side Current in CCM AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 13 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 So peak current can be got as equation (17). Ipeak _ CCM = 2 ⋅ Io (1 − D) ⋅ (1 + K depth ) ⋅ N (17) If the CCM operation is adopted, please choose proper Kdepth firstly. Ipeak and Ivalley can be calculated then. And the current sensing resistor could be selected by equation (18). R sense = Vsense Ipeak _ CCM (18) Where Vsense is same as in equation (15). The current sensing resistor with the proper power rating should be chosen based on the power loss given in equation (19) and equation (20) when converter operates in DCM and CCM. Psense _ BCM = Ipeak 2 ⋅ D ⋅ R sense 3 ⎡⎛ I peak +Ivalley ⎞2 1 ⎤ 2 Psense _ CCM = ⎢⎜ ⎟ + (I peak −Ivalley ) ⎥ ⋅ D ⋅ Rsense 2 ⎢⎣⎝ ⎥⎦ ⎠ 12 (19) (20) F. Primary Side Inductance Lm Design The maximum power that a Flyback converter can deliver is related to the energy stored in the primary side inductance Lm as given in equation (21) and (22) for CCM and DCM respectively. po _ CCM 1 ⋅ Lm ⋅ (Ipeak 2 − Ivalley 2 ) ⋅ fs = 2 ηps (21) po _ DCM 1 ⋅ Lm ⋅ Ipeak 2 ⋅ fs = 2 ηps (22) Since Ipeak, Ivalley, fs and ηps have been determined at the beginning of the design procedure, Lm can be calculated. As mentioned in section E, due to the slope compensation, the peak current at low line is lower than that at high line. So usually the transformer inductance is designed at low line and full load condition. In order to avoid the influence by components parameters variation, 20% margin is usually reserved for maximum output power. As described in the previous section, the FB voltage reaches its maximum at low line and full load. When the output power is larger than the maximum power that converter can deliver, the FB voltage reaches 3.8V. The internal Over Load Protection (OLP) counter starts. MP110 enters OLP mode and shuts down its switching if the 8192 switching cycles elapse. When the fault disappears, the power supply resumes operation. The OLP delay can be got by the below equation. TDelay = AN084 Rev. 1.0 7/9/2014 8192 fs www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (23) 14 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 G. Input Over Voltage Protection Function MP110 has input over voltage protection function to avoid the input over voltage damage. It can be set as Figure-15. Bus Voltage R1 R2 R3 PRO R4 CPRO Figure-15 Input OVP Circuit The resistor divider can be set by the equation (24). VIN _ OVP ⋅ R4 = VPRO R1 + R2 + R3 + R4 (24) VPRO (3.1V typical) is protection threshold on PRO. The resistor should be with 1206 package from safety consideration. Generally speaking, each resistor with 1206 package can sustain 200V voltage and 4 resistors are needed if the maximum input voltage is 420Vac or even 440Vac. In order to achieve low no power consumption, total resistance of the resistor divider should be larger than 10MΩ. In order to filter the noise brought by the resistor divider on PRO, one ceramic capacitor around 1nF is needed to parallel with R4 and it should be placed near the PRO. The input line OVP function can be disabled by shorting the PRO to ground. AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 15 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 H. Transformer Design H-1. Transformer Core Selection An appropriate core for certain output power and operating frequency needs to be selected. Ferrite core is usually preferred for Flyback transformer. The core area product (AE*AW) which is the core magnetic cross-section area multiplied by window area available for winding, is widely used for an initial estimate of core size for a given application. A rough indication of the required AE*AW (cm4) is given by following equation [1]: AE ⋅ A W ⎛ Lm ⋅ Ipeak ⋅ Irms ⋅ 10 4 =⎜ ⎜ B ⋅K ⋅K ⋅ f ⎝ max u j s 4 ⎞ 3 4 ⎟⎟ cm ⎠ (25) Where Ku is winding factor which is usually 0.25~0.3 for an off-line transformer. Kj is the current-density coefficient (typically 400~450 for ferrite core). Ipeak and Irms is the maximum peak current and RMS current of the primary inductance, Bmax is the allowed maximum flux density in normal operation which is usually preset to be the saturation flux density of the core material (0.3T~0.35T). fs is the switching frequency at low line and full load condition. RMS current is given by following equation. ⎡⎛ I peak +Ivalley ⎞ 2⎤ 1 Irms = ⎢⎜ ⎟ + (I peak -Ivalley ) ⎥ ⋅ D 2 ⎢⎣⎝ ⎥⎦ ⎠ 12 2 (26) For power supply at DCM, Ivalley equals to 0. H-2. Primary and Secondary Winding Turns With a given core size, equation (27) defines a minimum value of NP for the transformer primary winding to prevent the core from saturation: Np = Lm ⋅ Ipeak AE ⋅ Bmax (27) Where: Lm is the primary side inductance of the transformer Bmax is the maximum allowable flux density AE is the effective cross sectional core Ipeak is the peak current in the primary side of the transformer The maximum allowable flux density Bmax should be smaller than the saturation flux density Bsat. Since Bsat decreases as the temperature increases, which should be considered in the design. Secondary winding turns Ns is a function of N and NP, which is given by equation (28). Ns = Np N (28) H-3. Wire Size Once all the winding turns are determined, the wire size should be properly chosen to minimize the winding conduction loss and leakage inductance. The winding loss depends on the RMS current value, the length and the width of wire, also the transformer structure. The wire size could be determined by the RMS current of the winding. For a Flyback converter, the RMS current on primary side is given by equation (26), and the RMS current on secondary side is given by equation (29). AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 16 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Isec_ rms ⎡⎛ I peak +Ivalley ⎞2 1 2⎤ = N ⋅ ⎢⎜ ⎟ + (I peak −Ivalley ) ⎥ ⋅ (1 − D) 2 ⎢⎣⎝ ⎥⎦ ⎠ 12 (29) For Flyback operated at DCM, Ivalley equals to 0. Then, the wire size required at primary and secondary side is got by equation (30) and equation (31). Spri = Ipri _ rms Ssec = (30) J Isec_ rms (31) J Here J is the current density of the wire which is 450A/cm2 typically. Due to the skin effect and proximity effect of the conductor, the diameter of the wire should be less than 2*Δd (Δd: skin effect depth): Δd = 1 ⋅ 10 3 (mm) π ⋅ fs ⋅ μ ⋅ σ (32) Where μ is the magnetic permeability of the conductor, which usually equals to the permeability of vacuum for most conductor, i.e. 4 π × 10 −7 H/m, σ is the conductivity of the wire (for copper, σ is typically 6 × 107 S/m at 0℃, σ will increases as temperature increases, which means the Δd will get smaller). If the required size of the winding is larger than Δd , multiple strands of thinner wire or Litz wire is usually adopted to minimize the AC resistance. The effective cross section area of multi-strands wire or Litz wire should be large enough to meet the the current density requirement. After the wire sizes have been determined, it is necessary to check whether the window area with selected core can accommodate the windings calculated in the previous steps. The window area required by each winding should be calculated respectively and added together, the area for inter-winding insulation, bobbin and spaces existing between the turns should also be taken into consideration. The fill factor, means the winding area to the whole window area of the core, should be well below 1 due to these inter-winding insulation and spaces between turns. It is recommended that a fill factor no greater than about 30% be used. For transformers with multiple outputs this factor may need to be reduced further. Based on these considerations, the total required window area is then compared to the available window area of a selected core. If the required window area is larger than the selected one, either wire size must be reduced, or a larger core must be chosen. Of course, reduction in wire size increases the copper loss of the transformer. H-4. Air Gap With the selected core and winding turns, the air gap of the core is given as equation (33): la = AN084 Rev. 1.0 7/9/2014 μ0 ⋅ Np 2 ⋅ A E Lm − lc μr www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (33) 17 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Where AE is the cross sectional area of the selected core, μ0 is the permeability of vacuum which equals 4π×10-7 H/m. Lm and NP is the primary winding inductance and turns respectively, lc is the core magnetic path length and μr is the relative magnetic permeability of the core material. For Ferrite core, μ r is very large, so la can be approximately calculated as equation (34). la = μ0 ⋅ Np 2 ⋅ A e Lm (34) I. RCD Snubber Design There is high voltage spike on the Drain due to leakage inductance of transformer when the MOSFET turns off. If the voltage is higher than voltage rating of MP110, the part may have avalanche damage. Therefore, the voltage spike should be suppressed to an acceptable level. The RCD snubber is usually adopted to suppress the voltage spike. The RCD clamp circuit and key waveforms are shown in Figure-16 and Figure-17 respectively. The RCD snubber circuit absorbs the energy stored in the leakage inductor when VDS exceeds Vin+N*(Vo+VF). It is assumed that the snubber capacitance is large enough thus its voltage is constant during one switching period. Figure-16 Flyback Converter with RCD Snubber AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 18 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 ID ipeak ts isn ISEC vds vsn VRO vin Figure-17 Relationship of Drain-Source Voltage and Current When the MOSFET turns off and VDS is charged to Vin+VRO, the secondary diode turns on at the same time. The primary current starts to charge Csn through the snubber diode (Dsn) The voltage stress of MOSFET is clamped to Vin+Vsn .Therefore, the voltage across Lk is Vsn-VRO. The slope of isn is given by equation (35). ⎛ V − VRO ⎞ disn = − ⎜ sn ⎟ dt Lk ⎝ ⎠ (35) Where isn is the current into the snubber circuit, Vsn is the voltage across the snubber capacitor Csn, VRO is the reflected output voltage and it is equal to N*(Vo+VF). Lk is the leakage inductance of the main transformer. The time ts is obtained by equation (36) . ts = Lk ⋅ Ipeak Vsn − VRO (36) Vsn should be large enough and it is generally set 1.5~2 times of VRO, otherwise the power loss caused by leakage current is too large. Once Vsn is determined, the power dissipated in the snubber circuit is obtained by equation (37). Psn = Vsn ⋅ AN084 Rev. 1.0 7/9/2014 Ipeak ⋅ t s 2 ⋅ fs = Vsn 1 ⋅ Lk ⋅ Ipeak 2 ⋅ ⋅ fs 2 Vsn − VRO www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (37) 19 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 On the other hand, since the power consumed in the snubber resistor (Rsn) is Vsn2/Rsn, the resistance is obtained by. R sn = Vsn 2 Vsn 1 ⋅ Lk ⋅ Ipeak 2 ⋅ ⋅ fs 2 Vsn − VRO (38) The snubber resistor with the proper rated power should be chosen based on the power loss. The RCD capacitor influences the voltage ripple of Vsn. Large capacitance leads to small voltage ripple. In general, 5~10% ripple is reasonable. Then the snubber capacitance can be calculated by the equation (39). Csn = Vsn ΔVsn ⋅ Rsn ⋅ fs (39) When the input voltage increases, the peak current decreases thus snubber capacitor voltage Vsn also decreases. The snubber capacitor voltage under high line input can be got by the equation (40). Vsn2 = VRO + VRO2 + 2 ⋅ R sn ⋅ Lk ⋅ fs ⋅ Ipeak 22 2 (40) If the converter operates in CCM in high line, the Ipeak2 in equation (40) can be got through equation (41), Ipeak 2 = Pin ⋅ (VDC _ max + VRO ) VDC _ max ⋅ VRO + VDC _ max ⋅ VRO 2 ⋅ Lm ⋅ fs ⋅ (VDC _ max + VRO ) (41) If the converter operates in DCM at high line, the Ipeak2 in equation (40) can be got through equation (42), Ipeak 2 = 2 ⋅ Pin fs ⋅ Lm (42) Usually the voltage spike caused by leakage inductance is lower than the calculated value due to the influence of RCD diode reverse recovery and parasitic capacitance, thus the snubber design usually needs to be tuned based on the bench test. Then the peak voltage on Drain is shown as Figure-18 and it can be calculated through equation (43). Vds _ max = VDC _ max + Vsn2 + Vspike (43) The Vspike is caused by the stray inductance and generally it is 10V-20V. Make sure the maximum Drain voltage has 10% margin of the breakdown voltage (900V) of MP110. The Drain-Source Voltage is calculated theoretically. RSN and CSN should be tuned on bench for better stress performance. AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 20 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Figure-18 Drain-Source Peak Voltage J. Output Diode Design The maximum voltage supplied on secondary side output diode can be calculated by equation (44). VD = Vin _ max N + Vo (44) Where Vin_max is the maximum input voltage, N is the turn ratio and Vo is the output voltage. Generally, the voltage rating of secondary side diode should leave ~20% margin and the output current should be 50% diode rated current considering thermal performance. The super-fast diode or Schottky diode is recommended for less power loss and better efficiency. K. Output Filters Design The ripple current of the output capacitor can be calculated based on equation (45). The ripple current should be smaller than the rated output capacitor RMS current. Icap _ rms = ID _ rms 2 − Io 2 (45) Where ID_RMS is the RMS current of secondary diode and is specified as equation (46) and equation (47) for DCM and CCM respectively. ID _ rms = N2 ⋅ Ipeak 2 ⋅ 1- D 3 ⎡⎛ I peak +Ivalley ⎞2 1 ⎤ 2 ID _ rms = N2 ⋅ ⎢⎜ ⎟ + (I peak −Ivalley ) ⎥ ⋅ (1- D) 2 ⎢⎣⎝ ⎥⎦ ⎠ 12 (46) (47) Where D is the primary side duty cycle, N is the turn ratio, Ipeak is the primary side current peak and Ivalley is the primary side valley current at CCM. The voltage ripple at the output can be estimated by: ΔVo = Io ⋅ D ⋅ Ts + (N ⋅ Ipeak − Io ) ⋅ RESR Co (48) Where Ts is switching period, Co is output filter capacitance, and RESR is the effective series resistance of output capacitor Co. If the electrolytic capacitor is used as the output capacitor, due to its high ESR and AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 21 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 ESL, a film capacitor or ceramic capacitor is usually adopted in parallel to provide a low impendence current path for high frequency current ripple. In order to further reduce the output voltage ripple, a small LC filter can be inserted between the output capacitor and output terminal. A lower corner frequency means better filter effect but may make system unstable. The corner frequency is usually set at around 1/5-1/10 of the switching frequency. L. Thermal Performance Check The total loss of the MP110 is divided into two portions, one is on the internal control circuit and the other is on the power MOSFET. The loss caused by integrated 900V MOSFET is dominant at high line or heavy load condition, so usually the thermal performance can be improved by reducing the MOSFET power loss. The power loss of the 900V MOSFET is mainly caused by turn-on process at high line and the turn-on loss is proportional to switching frequency. Thus the switching frequency can’t be set too high. The rule of thumb is that if the maximum input voltage is more than 400Vac and output power is equal or more than 5W, the switching frequency should be lower than 100kHz, and ~60kHz is recommended. In general, 50℃ case temperature rise is allowed. If the high switching frequency is necessary or the output power is too high, heat sinks can be adopted to meet the thermal requirement. Four different heat sinks (6 teeth) are listed in Table-1 and the thermal comparison is shown in Table-2. The test condition is: Vin=600Vdc, Vout=12.37V, Iout=0.405A, Pout=5W. . Table-1 Heatsink Dimension Length Tooth Tooth Thickness Height 1.5cm 1.0mm 4.0mm 1.3cm 1.5cm 1.0mm 4.0mm 3# Heatsink 1.3cm 1.5cm 1.0mm 5.5mm 4# Heatsink 1.0cm 1.5cm 1.0mm 5.5mm Length Width 1# Heatsink 2.0cm 2# Heatsink Tooth Hight Tooth Width Width Table-2 Thermal Performance w/i and w/o Heatsink Ambient Case Temperature Temperature Temperature Rise 1# Heatsink 85.1 120.2 35.1 2# Heatsink 85.1 124.3 39.2 3# Heatsink 85.7 121.3 35.6 4# Heatsink 85.1 124.2 39.1 30.1 114.2 84.1 85.0 OTP -- w/o Heatsink AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 22 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 M. PCB Layout The PCB layout has great relationship with the EMI, thermal and so on. Good layout can lead to good EMI performance and thermal performance. In this section one PCB layout is attached. Following guidance should be applied to optimize the PCB layout. 1) Minimize the power loop area. The power loop includes primary side main power loop( Input Capacitor-Transformer Primary Main Winding-Drain-Source-Sensing Resistor-Input Capacitor), RCD snubber loop(Transformer Primary Main Winding-Drain-RCD Diode-RCD Capacitor-Transformer Primary Main Winding), Vcc charge loop(Transformer auxiliary winding-Vcc Diode-Vcc CapTransformer auxiliary winding) and the secondary side main power loop(Transformer secondary winding-Output diode-Output cap-Transformer secondary winding). The four loops are marked in the figure with 1, 2, 3 and 4 respectively. 2) The GND of input power loop and control loop should be separated and connected at the negative terminal of input capacitor by one point. 3) The FB and Vcc decoupling capacitor is recommended to place near the chip. 4) Enlarge the Source area for better thermal performance. Drain area shouldn’t be too large due to it is jumping point and can influence the EMI performance. 5) The switching point should be placed far away from EMI filter. Or the switching point may couple noise to the input line so that the EMI filter loses some effect. 6) The three outputs should satisfy the insulation requirement. 7) If the heatsink is needed, connect the heatsink with primary side GND. (a) Bottom Layer (b) Top Layer Figure-19 Triple Outputs Flyback PCB Layout with MP110 AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 23 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 N. Design Flow Chart Figure-20 Flyback Design Flow Chart with MP110 AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 24 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 O. Experimental Verification z A detailed reference design for E-meter power with MP110 is shown in Figure-21 z The input voltage is 85Vac to 420Vac and three outputs, output1 is 13.5V/0.3A, output 2 is 8V/0.05A and output3 is 8V/0.05A. Figure-21 Schematic of E-Meter Power Design with MP110 . AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 25 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 The transformer used in this design has a turn ratio of 22:100:13:15:9:9 with 3.4mH primary inductance. The core selected is EE16. The wire structure is shown as Figure-22, Figure-23 and Table-3. Primary Secondary NC 10 N1 N4 9 1 N2 N3 2 A B 3 5 4 6 N5 N6 Figure-22 Transformer Connection Diagram 3mm wall 3mm wall 3T N5 1T N4 1T 1T N6 N3 1T N2 1T N1 1T Notes: ♦ One tape outside of each winding; ♦ 3mm wall to keep winding at the central of bobbin for better consistency Figure-23 Transformer Winding Diagram AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 26 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Table-3 Transformer Winding Detail Information Winding No. Tape Layer Number Start & End Winding Wire Φ(mm) Turns N1 1 1→NC 0.18mm * 2 22 N2 1 2→1 0.15mm * 1 120 N3 1 4→3 0.15mm * 1 13 N6 1 5→6 0.30mm * 1 TIW 15 N4 1 10→9 0.16mm * 1 TIW 9 N5 1 A→B 0.16mm* 1 TIW 9 To verify design procedure presented in this application note and the performance, a prototype based in Figure-21 is built and tested with specified input/output condition (Input: 85VAC~420VAC; Output1: 13.5V/0.3A, Output2: 8V/0.05A, Output3: 8V/0.05A). AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 27 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 The converter is designed to operate in BCM at 85Vac input and full load while in DCM at high line. Figure-24 and Figure-25 show the current sensing voltage and Drain voltage waveform of primary MOSFET. Figure-24 Drain Voltage and Current of MOSFET at Low Line Input (85Vac) VDS VCS Figure-25 Drain Voltage and Current of MOSFET at High Line Input (420Vac) AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 28 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Figure-26 shows Burst Mode function of the controller at light load. The MP110 skips switching cycles when the FB voltage decreases lower than the threshold VBURL—0.5V. Once the FB voltage increases above the threshold VBURH—0.7V, the switching resumes. The FB voltage falls and rises repeatedly. Burst mode operation alternately enables and disables switching cycles of the MOSFET thereby reducing switching loss in the no load or light load conditions. Figure-26 Burst Mode Function of MP110 When output power exceeds the maximum designed output power, feedback loop loses control. Then MP110 enters Over Load Protection (OLP) after counting 8192 switching cycles, Figure-27 shows OLP process. Figure-27 Over Load Protection of MP110 AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 29 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Figure-28 shows the measured efficiency. From the efficiency curve, the efficiency is still high at light load condition due to decreased switching frequency. Also the power consumption at no load is given in Table-4. Due to the burst mode operation, the power loss at no load condition is below 0.2W, even at high line input. Efficiency 80 75 70 η(%) 65 60 55 50 230VAC 300VAC 45 40 35 30 0 1 2 3 Load 4 5 Figure-28 Measured Efficiency of the Flyback Converter Table-4 No Load Loss at Different Line Voltage Input voltage (Vac, RMS) 90 175 265 355 420 Power loss (mW) 115 117 140 175 198 Also conducted EMI test results of Fylback converter complies with EN55022 with 10dB margin. Neutral Wire Line Wire 230Vac/50Hz 230Vac/50Hz 120 1 MHz 10 MHz 120 110 110 100 100 90 90 80 80 1 MHz 10 MHz R 70 70 EN55022Q EN55022Q 60 60 EN55022A EN55022A 50 50 40 40 30 30 20 20 10 10 0 0 150kHz 30MHz 150kHz 30MHz Figure-29 Conducted EMI of the Flyback Converter AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 30 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 The maximum case temperature of MP110 is about 75℃ while the ambient temperature is 28℃. The temperature rise is lower than 50℃. TOP Top Bottom Figure-30 Thermal Performance of the Flyback Converter at Low Line (85Vac), Ta=28℃ Top Bottom Figure-31 Thermal Performance of the Flyback Converter at High Line (420Vac), Ta=28℃ AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 31 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 4. BUCK CONVERTER DESIGN PROCEDURE MP110 can also be configured as Buck converter. Due to Buck converter is much simpler than Flyback converter and if there is no isolation requirement, Buck converter may be a better choice. For the Buck converter configured by MP110, Vcc voltage is supplied by output voltage, so it is recommended that the output voltage must be higher than Vcc lower level at which the regulator switch off (VCCL, 9.0V maximum) and lower than Vcc OVP level (VOVP, 22.5V minimum). If the output voltage is little higher than VOVP, a zener diode is needed. A. Predetermine the Input and Output Specifications -Input AC voltage range: Vac(min), Vac(max), for example 85Vac~265Vac RMS -DC bus voltage range: Vin(max), Vin(min) -Output: Vout, Iout(min), Iout(max), Pout -Estimated efficiency: η. It is used to estimate the power conversion efficiency to calculate the maximum input power. Generally, η is set to be 0.7-0.75 for low output voltage applications and 0.75-0.8 for high output voltage applications. Then the maximum input power can be given as: Pin = Pout η (49) The input capacitor selection procedure is similar as we depicted in section 3.A. B. Determine Switching Frequency and Operation Mode The thermal of MP110 is mainly caused by the power loss of internal 900V MOSFET. We take two examples for reference and provide the switching frequency design guidance. The output voltage of application 1 is 12V and the output voltage of application 2 is 24V. The output power of both cases is 5W. The conduction vs. inductance under different switching frequency condition is shown as Figure-32(a). The conclusion can be drawn from Figure-32(a) that when the output voltage is low (12V), the critical inductance at 220Vac line voltage which makes Buck converter operates in BCM is ~0.46mH. The conduction loss is large when the Buck converter operates in DCM or BCM. So make sure Buck converter works in CCM. While when output voltage is high (24V), the critical inductance is ~1.8mH and conduction loss can be acceptable when Buck converter operates in light DCM. The switching loss is hard to calculate precisely due to it has great relationship with freewheel diode. Large reverse recovery time means high switching loss, especially when the converter operates in CCM. Ultra fast diode is recommended here. When the converter works in DCM, the switching loss isn’t the dominant. So the switching frequency can be pushed higher for small inductor and tight PCB area. Figure-32(b) shows the conduction loss comparison with different switching frequency for case 2. Higher switching frequency means the lower conduction loss. AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 32 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 (a) Conduction Loss Comparison with Output Voltage (b) Conduction Loss Comparison with Different Switching Frequency Figure-32 Conductance Loss Comparison In a word, the CCM is preferred for low voltage/high current application and DCM is preferred for high voltage/low current application. The switching frequency is correspondingly low in CCM considering switching loss. The Table-5 can be taken as reference for ~5W Buck converter design with MP110. Table-5 Frequency and Inductance Selection for Different Application Output Spec 12V/0.42A 16V/0.31A 24V/0.21A Operation Mode CCM@220Vac Light DCM@220Vac Light DCM@220Vac Switching Frequency (kHz) 25-30 40 70-80 Inductance (mH) 1-3.3 0.5-0.58 0.5-0.65 C. Inductor and Sensing Resistor Design AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 33 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Since MP110 operates in PWM mode with internally fixed maximum peak current limit, the maximum output power is determined by the sensing resistor and the inductor. So, it is important to select an appropriate inductor based on the desired output power. The way to calculate the maximum output power capability is described as below. Different inductance leads to different operation mode. Figure-33 and Figure-34 shows the different operation conditions when the converter delivers maximum power. Figure-33 Abnormal Operation Modes Figure-34 Normal Operation Modes Figure-33 shows two abnormal operation modes due to improper inductor selection. The inductor of the converter is so small, such as tens of μH, that it makes the current slew rate too fast. As a result, within tLEB2 (Leading edge blanking time of SCP, 600ns typical, in order to avoid the premature termination of the switching pulse due to the parasitic capacitance), the current of MOSFET is larger than the SCP threshold. Thus SCP is triggered and the converter can not work normally, just as Figure-33(a) shows. With a larger inductance, the internal MOSFET current is lower than the SCP threshold within tLEB2, the SCP is not triggered. But the inductor value is also too small which makes the peak current can be higher than Ipk (Peak current limitation) in the tLEB1 (Leading edge blanking time of peak current limitation, 650ns typical). Then the peak current under this condition can be obtained as: Ipk = AN084 Rev. 1.0 7/9/2014 (Vin − Vo − Von ) ⋅ TLEB1 L www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (50) 34 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Where Von is the voltage drop on Drain-Source of MP110 when internal 900V MOSFET turns on. And the maximum power is calculated as: Pmax = (Vin − Von − Vf ) ⋅ Vo 1 2 ⋅ L ⋅ Ipk ⋅ fs ⋅ 2 (Vin − Vo − Von ) ⋅ (Vo − Vf ) (51) Where Von is same as in equation (50) and Vf is the forward drop voltage of freewheel diode. The inductor is also too small that the peak current is not controlled by peak current limitation under full load. This current waveform is shown in Figure-33(b) and it is not recommended. Figure-34 shows the three normal working modes. The converter can work properly if the ON time is larger than tLEB1. L ⋅ Ipk t on = Vin − Vo − Von (52) The ON time of freewheel diode can be got by equation (53). t off = L ⋅ Ipk Vo − Vf (53) When the sum of ON time and OFF time is less than the switching period, the regulator runs in DCM, while when the sum of ON time and OFF time is equal to the switching period, the regulator runs in BCM. The waveforms are shown in Figure-34 (a) and Figure-34 (b) respectively. With the output current increasing, the operation mode will be CCM, just as shown in Figure-34 (c). The maximum output can be got when the regulator operates in DCM by equation (57), PDCM = Ipk Ton + Toff ⋅ ⋅ Vo 2 Ts Ton = Ipk ⋅ L Vin − Vo − Von Toff = PDCM _ max = Ipk ⋅ L Vo − Vf (Vin − Von − Vf ) ⋅ Vo 1 2 ⋅ L ⋅ Ipk ⋅ fs ⋅ 2 (Vin − Vo − Von ) ⋅ (Vo - Vf ) (54) (55) (56) (57) Also, the maximum output power of BCM is the same as regulator operates in DCM. If the converter works in CCM at heavy load conditions, the ripple current can be got: ΔI = AN084 Rev. 1.0 7/9/2014 Vo − Vf ⋅ Toff L www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (58) 35 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 The average output current under this condition is given as equation (59): Io _ max = Ipk − 1 ⋅ ΔI 2 (59) And the maximum power can be calculated as equation (60): Pmax = Vo ⋅ Io _ max (60) D. Freewheel Diode The maximum reverse block voltage of freewheel diode must be higher than the maximum input voltage. For the application of universal input voltage, a diode with 600V reverse block voltage is needed. And the current rating of the diode can be determined by the RMS current. IDCM_RMS = Ipk ⋅ ICCM _ RMS = (Io2 + Ipk ⋅ L 1 ----DCM ⋅ 3 (Vo − Vf ) ⋅ Ts Vo − Vf ΔI2 ) ⋅ (1 − ) ----CCM 12 Vin − Von − Vf (61) (62) Where ΔI is the current ripple of inductor, it is equal to 2*(Ipk - Io). The reverse recovery of freewheeling diode affects the efficiency and the circuit operation. So an ultra fast diode is recommended. For DCM, reverse recovery time should be less than 75ns, such as EGC10JH from ZOWIE. For CCM, an ultra fast diode should be used, and the reverse recovery time should be less than 35ns, such as UGC10JH. E. Output Capacitor Design The output capacitor is required to maintain the DC output voltage. The output voltage ripple can be estimated by equation (63) and equation (64): VDCM _ ripple I = o fs ⋅ Co VCCM _ ripple = 2 ⎛I −I ⎞ ⋅ ⎜ pk o ⎟ + Ipk ⋅ RESR ----DCM ⎜ I ⎟ ⎝ pk ⎠ ΔI + ΔI ⋅ RESR ----CCM 8 ⋅ fs ⋅ Co (63) (64) Where fs is switching frequency, RESR is ESR of output capacitor. To lower the output voltage ripple, Ceramic, tantalum or low ESR electrolytic capacitors are recommended. At the output, a dummy load is also required to maintain the output regulation under no-load condition. This can ensure sufficient energy to charge the VCC capacitor, and to detect the output voltage. Normally a 1mA dummy load is needed and can be adjusted according the regulation. Increasing the dummy load improves load regulation but deteriorates the efficiency and no-load consumption. If the user cares nothing about the output regulation under no-load condition, a Zener diode is recommended for lower no-load consumption. AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 36 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 F. Vcc Power Supply and Power Feedback Circuit Design The Vcc Power Supply and feedback circuit of Buck converter with MP110 is shown as Figure-35. The Vcc capacitor is directly charged through the red path when freewheel diode conducts. If the output voltage is higher than the rated voltage of Zener diode, Zener diode breaks down and then the FB voltage is regulated by the transistor Q1. Vout Vout D1 10 D1 Zener1 R1 Zener1 Vcc Vcc FB FB NS NS Q1 22μF Q1 1nF 1K 22μF 1nF Zener2 200 1K 200 PGND (a) PGND (b) PGND Figure-35 Vcc Power Supply and Feedback Circuit of Buck Circuit with MP110 F-1. VCC Charge Diode Selection The diode D1 should have the same voltage rating as the freewheel diode. The current of this diode is very small, so fast and slow diodes such as FR10X and 1N400X can be used. However, in order to obtain a better regulation, charge diode and freewheel diode should have the same forward voltage drop. F-2. VCC Capacitor Selection The MP110 consumes milli-amperes current when it is in operation. In order to make sure the Vcc voltage doesn’t drop below Vcc off threshold before the output voltage setup, Equation (65) should be satisfied. ICC ⋅ TStart < CVcc ⋅ (VCCH − VCCL ) (65) Where ICC is the IC consumes current and typically is 1-2mA. TStart is the startup time. VCCH and VCCL is Vcc ON and OFF threshold. Then the Vcc capacitor can be got. Generally, 10μF to 47μF is commended for VCC capacitor. Also a 0.1μF ceramic is commended to parallel with this capacitor. F-3. Zener Diode Selection The output voltage reference is implemented by the Zener breakdown voltage. Generally, the voltage rating of Zener diode (Zener 1) should be selected as equation (66). VZener = VO + Vbe (66) VO is output voltage and Vbe is the base-emitter drop voltage of the transistor, the typical value is 0.7V. If the output voltage is little higher than VCC OVP voltage, a Zener diode (Zener 2) is needed to protect the part enters OVP. The voltage on Vcc must be higher than low level when operation current is maximum and lower than VCC OVP level when operation current is minimum. The following formula should be satisfied. AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 37 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 VZener < VOVP (67) VO > VCCL + ICC _ max ⋅ R1 (68) G. Thermal Performance Check MP110 has an internal OTP function. When the junction temperature of IC increases to 150℃, it triggers over temperature protection. Please avoid MP110 enters OTP during normal operation. For example, the maximum allowed junction temperature is Tb (Normally 125℃). And the maximum ambient temperature for normal application is Ta. So the maximum junction temperature rise should not be bigger than ΔT= Tb - Ta. The junction-to-ambient thermal resistance θJA is 68℃/W. The maximum power loss of IC is: Pmax_ loss = Tb − Ta θJA (69) The power loss of MP110 mainly caused by internal 900V MOSFET. The conduction loss of MOSFET is easy to calculate and the result is close to the real value. Figure-36 DCM and CCM Operation Current of MP110 The MOSFET current under DCM and CCM is shown as Figure-36. The duty cycle when Buck converter operates in DCM and CCM can be calculated as: DDCM = DCCM = Ipk ⋅ L (Vin − Von ) ⋅ Ts Vo − Vf Vin − Von − Vf (70) (71) The RMS value of current in MOSFET can be obtained as: IRMS _ DCM = Ipk ⋅ AN084 Rev. 1.0 7/9/2014 DDCM 3 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. (72) 38 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 IRMS _ CCM = (Io2 + ΔI2 ) ⋅ DCCM 12 (73) The conduction loss of MOSFET is: PMOS _ con = IRMS 2 ⋅ RON (74) Please note that the RON is ON resistor of MOSFET at its operation junction temperature. As depicted in section 4.B, the switching loss of Buck converter has great relationship with reverse recovery of freewheel diode. So the switching loss is hard to calculate accurately. It is better to estimate the loss by capturing relative voltage and current waveforms. Figure-37 Switching Loss of Buck Converter at High Line Normally conduction loss is dominant at low line and switching loss is dominant at high line. Please check the loss pointedly. There should be a tradeoff between loss and switching frequency. The power loss of internal controller can be calculated as: PIC = VCC ⋅ ICC (75) Where ICC is the operation current under full load condition. AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 39 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 H. Design Flow Chart Start Given the Input spec, Vo, Io spec for each output, the estimate efficiency of the circuit get the total output power Select the input cap Typically 2-3uF per Watt Get the minimum and maximum input DC voltage Determine the operation mode to get the inductor and sensing resistor Get the freewheel diode Get the output capacitor Select the feedback circuit parameters Determine if the heatsink is needed The design is finished Figure-38 Buck Converter Design Flow Chart with MP110 I. Experimental Verification AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 40 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 A Buck converter using MP110 as a design example has been built and tested (Input: 85VAC~265VAC; Output: 12.5V/0.4A). The key components value in the circuit is calculated based on the above section and the circuit is shown in Figure-39. D1 1N4007 RV1 NC CX1 NC L2 3.3mH Vout R2 2.2 D2 1N4007 PGND C1 10uF/400V D4 1N4007 Vout Source R3 5.1 R1 NC L 85~265VAC Drain L1 1mH F1 10/1W D5 STTH1R06 C2 10uF/400V C3 C4 390uF/25V 0.1uF/25V R17 12.5V/400mA 10K D3 1N4007 N GND Vcc GND FB D7 BZT52C12 C7 R8 1K R7 200 5 VCC FSET 7 8 PGND Drain Source Pro GND FB 4 3 C6 0.1uF 2 1 R5 390K R4 2.2 D6 Vout U1 MP110-P Vcc C8 1nF Source Q1 Drain NS C5 47uF R6 NS FB PGND Figure-39 Buck Converter with MP110 AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 41 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 The converter is designed to operate in CCM both at low line and high line. At light load, MP110 enters switch skipping mode for better efficiency and when the load increases, MP110 operates in PWM. Figure-40 and Figure-41 show the Drain-Source current and voltage waveforms. VDS IDS VDS IDS Figure-40 Operation Waveforms when the Buck Converter Operates at Low Line (85Vac) VDS VDS IDS IDS Figure-41 Operation Waveforms When the Buck Converter Operates at High Line (265Vac) AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 42 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 Figure-42 shows the measured efficiency. From the efficiency curve, the efficiency is still high at light load condition due to decreased switching frequency. Also the power consumption at no load is given in Table-6. Due to the burst mode operation, the power loss at no load condition is very small, even at high line input. Efficiency Efficiency vs. Load Current 84% 82% 80% 78% 76% 74% 72% 70% 68% Vin=115Vac Vin=230Vac 0 0.1 0.2 Load Current (A) 0.3 0.4 Figure-42 Measured Efficiency of Buck Converter Table-6 No Load Loss at Different Line Voltage Input voltage (Vac, RMS) Power loss (mW) 90 115 230 265 48.3 50.8 59.7 61.1 It can be predicted that the output voltage at no load or light load condition is higher than it at heavy load condition. The output voltage has about 0.8V variation compared between no load and full load condition. Output Voltage (V) Line Regulation 13.5 13.3 13.1 12.9 12.7 12.5 12.3 12.1 11.9 11.7 11.5 No Load Full Load 50 100 150 200 250 300 Input Voltage (Vac) Figure-43 Line Regulation of Buck Converter The Buck converter is not recommended to be used in high output power applications, because its AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 43 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 primary side RMS current is larger than that of a Flyback converter, and also it has larger turn-on loss due to reverse recovery of freewheel diode. Figure-44 shows the thermal performance of MP110 used in 5W Buck design with 30kHz switching frequency. The case temperature rise is nearly 65℃. (a) Vin=85Vac (b) Vin=265Vac Figure-44 Thermal Performance of Buck Converter, Ta=30℃ AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 44 AN084 –SWITCHING MODE POWER SUPPLY DESIGN WITH MP110 5. REFERENCES [1]. Lloyd H. Dixon, “Magnetics Design for Switching Power Supplies,” in Unitrode Magnetics Design Handbook, 1990. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. AN084 Rev. 1.0 7/9/2014 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2014 MPS. All Rights Reserved. 45