M61314SP I2C BUS Controlled Video Pre-amp for High Resolution Color Display REJ03F0200-0200 Rev.2.00 Sep 14, 2006 Description M61314SP is semiconductor integrated circuit for CRT display monitor. It includes OSD blanking, OSD mixing, retrace blanking, video detector, sync sepa, wide band amplifier. Brightness control, main/sub contrast, OSD level, 4ch D/A OUT, video response adjust can be controlled by I2C BUS. Features • Frequency band width: RGB OSD • Input: RGB OSD OSD BLK Retrace BLK Clamp pulse Output: RGB OSD Sync OUT 180 MHz (3 VP-P at −3 dB) 80 MHz 0.7 VP-P (typ.) 3.5 V to 5 V (positive) 3.5 V to 5 V (positive) 2.5 V to 5 V (positive) 2.5 V to 5 V (positive) 5.0 VP-P (at brightness less than 2 VDC) 4 VP-P (at brightness less than 2 VDC) 5 VP-P Recommended Operating Conditions Supply voltage range: 11.50 V to 12.50 V (V3, V29) 4.75 V to 5.25 V (V11) Rated supply voltage: 12.00 V (V3, V29) 5.00 V (V11) Application Example CRT display monitor Rev.2.00 Sep 14, 2006 page 1 of 9 M61314SP Block Diagram Ret. BLK IN 17 OSD R R IN VCC 12 V 2 Clamp Sub contrast CP Sub Cont (8 bit) Main contrast 3 Retrace blanking Amp OSD Mix CP Clamp F/B 30 R OUT 29 VCC 12 V OSD G G IN CP Main contrast Sub contrast Clamp 4 Retrace blanking Amp OSD Mix 28 G OUT Sub Cont (8 bit) 6 CP Clamp F/B 27 OSD B B IN 7 Main contrast Clamp Sub contrast CP Sub Cont (8 bit) OSD Mix OSD level 7 bit Main contrast 8 bit Video Det Retrace blanking Amp CP Clamp F/B 1 bit SW BRT 8 bit Video Det. OUT 10 SonG IN R Sub Cont 8 bit 5 Sync Sepa Sync Sepa. 9 OUT G Sub Cont 8 bit 1 bit SW 26 B OUT DAC BUS I/F B Sub Cont 8 bit 11 VCC 5 V (DIGITAL) 19 SDA 20 SCL 25 NC 18 1 8 Clamp Pulse IN Rev.2.00 Sep 14, 2006 page 2 of 9 31 ABL IN 13 14 15 12 OSD OSD OSD OSD R G B BLK IN IN IN IN 16 21 22 23 24 32 DAC output for cut-off Adj NC M61314SP Pin Arrangement M61314SP GND 1 32 NC (GND) R IN 2 31 ABL IN VCC1 (12 V) 3 30 R OUT G IN 4 29 VCC2 (12 V) SonG IN 5 28 G OUT GND1 6 27 GND4 B IN 7 26 B OUT GND2 8 25 NC (GND) Sync Sepa. OUT 9 24 D/A OUT4 Video Det. OUT 10 23 D/A OUT3 VCC3 (5 V) 11 22 D/A OUT2 OSD BLK IN 12 21 D/A OUT1 OSD R IN 13 20 SCL OSD G IN 14 19 SDA OSD B IN 15 18 Clamp Pulse IN GND3 16 17 Ret. BLK IN (Top view) Outline: PRDP0032BA-A (32P4B) Rev.2.00 Sep 14, 2006 page 3 of 9 M61314SP Absolute Maximum Ratings (Ta = 25°C) Item Supply voltage (pin 3, 29) Symbol VCC12 Ratings 13.0 Unit V Supply voltage (pin 11) Power dissipation VCC5 Pd 6.0 2358 V mW Ambient temperature Storage temperature Topr Tstg −20 to +75 −40 to +150 °C °C Recommended supply 12 Recommended supply 5 Vopr12 Vopr5 12.0 5.0 V V Voltage range 12 Voltage range 5 Vopr'12 Vopr'5 11.5 to 12.5 4.75 to 5.25 V V Thermal Derating Power Dissipation Pd (mW) 2800 2400 2358 2000 1600 1415 1200 800 400 0 −25 0 25 50 75 100 125 Ambient Temperature Ta (°C) Rev.2.00 Sep 14, 2006 page 4 of 9 150 M61314SP BUS Control Table (1) Slave address: D7 D6 D5 D4 D3 D2 D1 R/W 1 0 0 0 1 0 0 0 = 88H (2) Slave receiver format: Normal mode S 8 bit Slave address A 8 bit Sub address 8 bit A Data byte A A 8 bit Data byte (Sub address = 0XH) A P Auto increment mode S 8 bit Slave address 8 bit A Data (Sub address = 0 (X + 1) H) A 8 bit Sub address (0XH) + 10H 8 bit Data (Sub address = 0 (X + 2) H) A Note: S: Start condition, A: Acknowledge, P: Stop condition (3) Pre-Amp Block sub address byte and data byte format Data Byte (Top: Byte Format, Under: Start Condition) Bit Sub Add. D7 D6 D5 D4 D3 D2 D1 D0 Main contrast 8 00H A07 0 A06 0 A05 0 A04 0 A03 0 A02 0 A01 0 A00 1 Brightness control 8 01H A17 0 A16 0 A15 0 A14 0 A13 0 A12 0 A11 0 A10 1 Sub contrast R 8 02H A27 0 A26 0 A25 0 A24 0 A23 0 A22 0 A21 0 A20 1 Sub contrast G 8 03H A37 0 A36 0 A35 0 A34 0 A33 0 A32 0 A31 0 A30 1 Sub contrast B 8 04H A47 0 A46 0 A45 0 A44 0 A43 0 A42 0 A41 0 A40 1 OSD level 7 05H A56 0 A55 0 A54 0 A53 0 A52 0 A51 0 A50 1 D/A OUT1 8 06H A67 0 A66 0 A65 0 A64 0 A63 0 A62 0 A61 0 A60 1 D/A OUT2 8 07H A77 0 A76 0 A75 0 A74 0 A73 0 A72 0 A71 0 A70 1 D/A OUT3 8 08H A87 0 A86 0 A85 0 A84 0 A83 0 A82 0 A81 0 A80 1 D/A OUT4 8 09H A97 0 A96 0 A95 0 A94 0 A93 0 A92 0 A91 0 A90 1 Sharpness control 4 0AH AA3 0 AA2 0 AA1 0 AA0 1 Sync Sepa SW 1 AA4 0 Video Det SW 1 AA5 0 Test mode 2 AA7 0 AA6 0 Function Note: pre-data Subadd. 0AH Sync Sepa SW AA4 0: Sync Sepa ON Video Det SW AA5 0: Video Det ON Always set up as AA6 and AA7 in 0 2 For I C data, please transfer in the period of vertical. Rev.2.00 Sep 14, 2006 page 5 of 9 1: Sync Sepa OFF 1: Video Det OFF M61314SP I2C BUS Control Section SDA, SCL Characteristics Symbol Min. Max. Unit Min. input LOW voltage Max. input HIGH voltage Item VIL VIH −0.5 3.0 1.5 5.5 V V SCL clock frequency Time the bus must be free before a new transmission can start fSCL tBUF 0 1.3 400 kHz µs Hold time start condition. After this period the first clock pulse is generated The LOW period of the clock tHD:STA tLOW 0.6 1.3 µs µs The HIGH period of the clock Set-up time for start condition (Only relevant for a repeated start condition) tHIGH tSU:STA 0.6 0.6 µs µs Hold time DATA Set-up time DATA tHD:DAT tSU:DAT 0 100 0.9 µs ns Rise time of both SDA and SCL lines Fall time of both SDA and SCL lines tr tf 20+0.1Cb 20+0.1Cb 300 300 ns ns Set-up time for stop condition tSU:STO 0.6 µs Timing Chart tr, tf tBUF VIH SDA VIL tHD: STA tSU: DAT tHD: DAT tSU: STA tSU: STO VIH SCL VIL tLOW S Rev.2.00 Sep 14, 2006 page 6 of 9 tHIGH S P S M61314SP Typical Characteristics Sub Contrast Control Characteristics 6 6 5 5 Output Amplitude (VP-P) Output Amplitude (VP-P) Main Contrast Control Characteristics 4 3 2 1 2 1 Main contrast: Max ABL: 5V FFH Main Contrast Control Data Sub Contrast Control Data Brightness Control Characteristics ABL Characteristics 6 6 5 5 4 3 2 1 0 00H 4 3 2 1 Main contrast: Max Sub contrast: Max 0 FFH 0 1 2 3 4 5 Brightness Control Data ABL Control Voltage (VDC) OSD Adjust Control Characteristics D/A OUT Control Characteristics 6 6 5 5 Output DC Voltage (VDC) Output Amplitude (VP-P) 3 0 00H FFH Output Amplitude (VP-P) Output DC Voltage (VDC) 0 00H Sub contrast: Max ABL: 5V 4 4 3 2 1 0 00H 7FH OSD Adjust Control Data Rev.2.00 Sep 14, 2006 page 7 of 9 4 3 2 1 0 00H FFH D/A OUT Control Data M61314SP Application Example CRT 110 V Cut off Adj 12 V DAC OUT × 4 3k 3k 3k SCL 0.01 µ ABL IN 0 to 5 VDC + 47 µ SDA 100 µH 0.01 µ 0.01 µ 100 0.01 µ 0.01 µ Clamp Pulse IN 0.01 µ 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 BLK IN (for retrace) M61314SP + + 8 9 10 0.01 µ 7 11 12 13 14 15 16 OSD B IN 50 k OSD G IN 1µ 0.01 µ 1k 75 OSD R IN 75 + 75 6 3.3 µ + 5 0.01 µ 4 3.3 µ + 3 0.01 µ 2 3.3 µ 1 47 µ + 0.01 µ 47 µ R IN 12 V G IN SONG IN Rev.2.00 Sep 14, 2006 page 8 of 9 B IN Sync Video 5 V Sepa. Det. OUT OUT OSD BLK IN M61314SP Package Dimensions RENESAS Code PRDP0032BA-A Previous Code 32P4B MASS[Typ.] 2.2g 17 1 16 D L A1 A A2 *2 c *1 E 32 e1 JEITA Package Code P-SDIP32-8.9x28-1.78 SEATING PLANE e *3 b 3 bp *3 b2 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. Reference Symbol e1 D E A A1 A2 bp b2 b3 c e L Rev.2.00 Sep 14, 2006 page 9 of 9 Dimension in Millimeters Min Nom Max 9.86 10.16 10.46 27.8 28.0 28.2 8.75 8.9 9.05 5.08 0.51 3.8 0.35 0.45 0.55 0.63 0.73 1.03 0.9 1.0 1.3 0.22 0.27 0.34 0° 15° 1.528 1.778 2.028 3.0 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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