R1LV0416C-I Series Wide Temperature Range Version 4 M SRAM (256-kword × 16-bit) REJ03C0105-0100Z Rev. 1.00 Aug.05.2003 Description The R1LV0416C-I is a 4-Mbit static RAM organized 256-kword × 16-bit. R1LV0416C-I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). The R1LV0416C-I Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has packaged in 44-pin TSOP II. Features • Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V • Fast access time: 55/70 ns (max) • Power dissipation: Active: 5.0 mW/MHz (typ)(VCC = 2.5 V) : 6.0 mW/MHz (typ) (VCC = 3.0 V) Standby: 1.25 µW (typ) (VCC = 2.5 V) : 1.5 µW (typ) (VCC = 3.0 V) • Completely static memory. No clock or timing strobe required • Equal access and cycle times • Common data input and output. Three state output • Battery backup operation. 2 chip selection for battery backup • Temperature range: −40 to +85°C Rev.1.00, Aug.05.2003, page 1 of 18 R1LV0416C-I Series Ordering Information Type No. Access time Package R1LV0416CSB-5SI 55 ns 400-mil 44-pin plastic TSOP II (44P3W-H) R1LV0416CSB-7LI 70 ns Rev.1.00, Aug.05.2003, page 2 of 18 R1LV0416C-I Series Pin Arrangement 44-pin TSOP A4 A3 A2 A1 A0 CS1# I/O0 I/O1 I/O2 I/O3 V CC V SS I/O4 I/O5 I/O6 I/O7 WE# A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 (Top view) Pin Description Pin name Function A0 to A17 Address input I/O0 to I/O15 Data input/output CS1# (CS1) Chip select 1 CS2 Chip select 2 OE# (OE) Output enable WE# (WE) Write enable LB# (LB) Lower byte select UB# (UB) Upper byte select VCC Power supply VSS Ground Rev.1.00, Aug.05.2003, page 3 of 18 A5 A6 A7 OE# UB# LB# I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 CS2 A8 A9 A10 A11 A12 R1LV0416C-I Series Block Diagram LSB A12 A11 A10 A9 A8 A13 A14 A15 A16 A17 MSB A7 V CC V SS Row decoder I/O0 • • • • • Memory matrix 2,048 x 2,048 Column I/O • • Input data control Column decoder I/O15 LSB A4 A3 A2 A1 A5 A6 A0 MSB • • CS2 CS1# LB# UB# WE# OE# Rev.1.00, Aug.05.2003, page 4 of 18 Control logic • • R1LV0416C-I Series Operation Table CS1# CS2 WE# OE# UB# LB# I/O0 to I/O7 I/O8 to I/O15 Operation H × × × × × High-Z High-Z Standby × L × × × × High-Z High-Z Standby × × × × H H High-Z High-Z Standby L H H L L L Dout Dout Read L H H L H L Dout High-Z Lower byte read L H H L L H High-Z Dout Upper byte read L H L × L L Din Din Write L H L × H L Din High-Z Lower byte write L H L × L H High-Z Din Upper byte write L H H H × × High-Z High-Z Output disable Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Symbol Value Unit Power supply voltage relative to VSS VCC −0.5 to +4.6 Terminal voltage on any pin relative to VSS VT −0.5* to VCC + 0.3* V Power dissipation PT 0.7 W Operating temperature Topr −40 to +85 °C Storage temperature range Tstg −65 to +150 °C Storage temperature range under bias Tbias −40 to +85 °C 1 V 2 Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +7.0 V. DC Operating Conditions (Ta = −40 to +85°C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 2.2 2.5/3.0 3.6 V VSS 0 0 0 V 2.0 VCC + 0.3 V Note Input high voltage VCC = 2.2 V to 2.7 V VIH VCC = 2.7 V to 3.6 V VIH 2.2 VCC + 0.3 V Input low voltage VCC = 2.2 V to 2.7 V VIL −0.2 0.4 V 1 VCC = 2.7 V to 3.6 V VIL −0.3 0.6 V 1 Note: 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns. Rev.1.00, Aug.05.2003, page 5 of 18 R1LV0416C-I Series DC Characteristics 1 Parameter Symbol Min Input leakage current |ILI| 1 µA Vin = VSS to VCC Output leakage current |ILO| 1 µA CS1# = VIH or CS2 = VIL or OE# = VIH or WE# = VIL or LB# = UB# = VIH, VI/O = VSS to VCC Operating current ICC 5 20 mA CS1# = VIL, CS2 = VIH, Others = VIH/VIL, II/O = 0 mA Average operating current ICC1 8 25 mA Min. cycle, duty = 100%, II/O = 0 mA, CS1# = VIL, CS2 = VIH, Others = VIH/VIL ICC2 2 5 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS1# ≤ 0.2 V, CS2 ≥ VCC − 0.2 V VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V ISB 0.1 0.3 ISB1 Standby current Standby current to +85°C to +70°C to +40°C −40°C to +25°C Output high voltage ISB1 ISB1 ISB1 Typ* Max Unit Test conditions CS2 = VIL µA Vin ≥ 0 V 3 µA (1) 0 V ≤ CS2 ≤ 0.2 V or 2 µA (2) CS1# ≥ VCC − 0.2 V, 3 µA CS2 ≥ VCC − 0.2 V or 2 µA 20* 10* 20* 10* 0.7* 0.7* mA 2 2 10* 3 3* 2 0.5* 3 2 10* (3) LB# = UB# ≥ VCC − 0.2 V, µA CS2 ≥ VCC − 0.2 V, µA CS1# ≤ 0.2 V 0.5* 3* µA VCC =2.2 V to 2.7 V VOH 2.0 — — V IOH = −0.5 mA VCC =2.7 V to 3.6 V VOH 2.4 — — V IOH = −1 mA VCC =2.2 V to 3.6 V VOH2 3 3 VCC − 0.2 — — V IOH = −100 µA Output low voltage VCC =2.2 V to 2.7 V VOL — — 0.4 V IOL = 0.5 mA VCC =2.7 V to 3.6 V VOL — — 0.4 V IOL = 2 mA VCC =2.2 V to 3.6 V VOL2 — — 0.2 V IOL = 100 µA Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. 2. L version. (−7LI) 3. SL version. (−5SI) Rev.1.00, Aug.05.2003, page 6 of 18 R1LV0416C-I Series Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Symbol Min Typ Max Unit Test conditions Note Input capacitance Cin 8 pF Vin = 0 V 1 Input/output capacitance CI/O 10 pF VI/O = 0 V 1 Note: 1. This parameter is sampled and not 100% tested. Rev.1.00, Aug.05.2003, page 7 of 18 R1LV0416C-I Series AC Characteristics (Ta = −40 to +85°C, VCC = 2.2 V to 3.6 V, unless otherwise noted.) Test Conditions • Input pulse levels: VIL = 0.4 V, VIH = 2.2 V (VCC = 2.2 V to 2.7 V) : VIL = 0.4 V, VIH = 2.4 V (VCC = 2.7 V to 3.6 V) • Input rise and fall time: 5 ns • Input/output timing reference levels: 1.1 V (VCC = 2.2 V to 2.7 V) : 1.4 V (VCC = 2.7 V to 3.6 V) • Output load: See figures (Including scope and jig) VTM 1.4 V R1 RL=500 Ω Dout R1 = 3070 Ω 30pF R2 Output load (A) (VCC = 2.2 V to 2.7 V) Rev.1.00, Aug.05.2003, page 8 of 18 R2 = 3150 Ω VTM = 2.3 V Dout 50pF Output load (B) (VCC = 2.7 V to 3.6 V) R1LV0416C-I Series Read Cycle R1LV0416C-I -5 -7 Parameter Symbol Min Max Min Max Unit Read cycle time tRC 55 70 ns Address access time tAA 55 70 ns Chip select access time tASC1 55 70 ns tASC2 55 70 ns Output enable to output valid tOE 35 40 ns Output hold from address change tOH 10 10 ns LB#, UB# access time tBA 55 70 ns Chip select to output in low-Z tCLZ1 10 10 ns tCLZ2 10 10 ns LB#, UB# disable to low-Z tBLZ 5 5 ns Output enable to output in low-Z tOLZ 5 5 ns Chip deselect to output in high-Z tCHZ1 0 20 0 25 ns tCHZ2 0 20 0 25 ns LB#, UB# disable to high-Z tBHZ 0 20 0 25 ns Output disable to output in high-Z tOHZ 0 20 0 25 ns Rev.1.00, Aug.05.2003, page 9 of 18 Notes 2 1, 2 R1LV0416C-I Series Write Cycle R1LV0416C-I -5 -7 Parameter Symbol Min Max Min Max Unit Notes Write cycle time tWC 55 70 ns Address valid to end of write tAW 50 60 ns Chip selection to end of write tCW 50 60 ns 5 Write pulse width tWP 40 50 ns 4 LB#, UB# valid to end of write tBW 50 55 ns Address setup time tAS 0 0 ns 6 Write recovery time tWR 0 0 ns 7 Data to write time overlap tDW 25 30 ns Data hold from write time tDH 0 0 ns Output active from end of write tOW 5 5 ns 2 Output disable to output in high-Z tOHZ 0 20 0 25 ns 1, 2 Write to output in high-Z tWHZ 0 20 0 25 ns 1, 2 Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write. 5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write. 6. tAS is measured from the address valid to the beginning of write. 7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. Rev.1.00, Aug.05.2003, page 10 of 18 R1LV0416C-I Series Timing Waveform Read Timing Waveform (WE# = VIH) t RC Address Valid address tAA tACS1 CS1# tCLZ1*2, 3 CS2 tCHZ1*1, 2, 3 tACS2 tCLZ2*2, 3 tCHZ2*1, 2, 3 tBHZ*1, 2, 3 tBA LB#, UB# tBLZ*2, 3 tOHZ*1, 2, 3 tOE OE# tOLZ*2, 3 Dout High impedance Rev.1.00, Aug.05.2003, page 11 of 18 tOH Valid data R1LV0416C-I Series Write Timing Waveform (1) (WE# Clock) tWC Valid address Address tWR*7 tCW*5 CS1# tCW*5 CS2 tBW LB#, UB# tAW tWP*4 WE# tAS*6 tDW tDH Valid data Din tWHZ*1, 2 tOW*2 High impedance Dout Rev.1.00, Aug.05.2003, page 12 of 18 R1LV0416C-I Series Write Timing Waveform (2) (CS# Clock, OE# = VIH) tWC Valid address Address tAW tAS*6 tWR*7 tCW*5 CS1# tCW*5 CS2 tBW LB#, UB# tWP*4 WE# tDW Valid data Din High impedance Dout Rev.1.00, Aug.05.2003, page 13 of 18 tDH R1LV0416C-I Series Write Timing Waveform (3) (LB#, UB# Clock, OE# = VIH) tWC Valid address Address tAW tCW*5 tWR*7 CS1# tCW*5 CS2 tAS*6 tBW LB#, UB# tWP*4 WE# tDW Valid data Din High impedance Dout Rev.1.00, Aug.05.2003, page 14 of 18 tDH R1LV0416C-I Series Low VCC Data Retention Characteristics (Ta = −40 to +85°C) 4 3 Parameter Symbol Min Typ* Max Unit Test conditions* VCC for data retention VDR Data retention current to +85°C ICCDR* 2 V Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1# ≥ VCC − 0.2 V or (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V 1 20 µA 2 10 1 20 2 10 1 0.7 10 VCC = 3.0 V, Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ VCC − 0.2 V, CS1# ≥ VCC − 0.2 V or (3) LB# = UB# ≥ VCC − 0.2 V, CS2 ≥ VCC − 0.2 V, CS1# ≤ 0.2 V 2 ICCDR* 0.7 3 1 −40°C to +25°C ICCDR* 0.5 10 2 ICCDR* 0.5 3 tCDR 0 ns ns ICCDR* to +70°C ICCDR* ICCDR* to +40°C Chip deselect to data retention time Operation recovery time ICCDR* tR 5 tRC* µA µA µA See retention waveform Notes: 1. This characteristic is guaranteed only for L version. 2. This characteristic is guaranteed only for SL version. 3. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#, I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC − 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. 5. tRC = read cycle time. Low VCC Data Retention Timing Waveform (1) (CS1# Controlled) (VCC = 2.2 V to 2.7 V) t CDR Data retention mode V CC 2.2 V V DR 2.0 V CS1# 0V Rev.1.00, Aug.05.2003, page 15 of 18 CS1# ≥ VCC – 0.2 V tR R1LV0416C-I Series Low VCC Data Retention Timing Waveform (2) (CS1# Controlled) (VCC = 2.7 V to 3.6 V) t CDR Data retention mode tR V CC 2.7 V 2.2 V V DR CS1# ≥ VCC – 0.2 V CS1# 0V Low VCC Data Retention Timing Waveform (3) (CS2 Controlled) (VCC = 2.2 V to 2.7 V) t CDR Data retention mode tR V CC 2.2 V CS2 V DR 0.4 V 0 V < CS2 < 0.2 V 0V Low VCC Data Retention Timing Waveform (4) (CS2 Controlled) (VCC = 2.7 V to 3.6 V) t CDR Data retention mode V CC 2.7 V CS2 V DR 0.6 V 0V Rev.1.00, Aug.05.2003, page 16 of 18 0 V < CS2 < 0.2 V tR R1LV0416C-I Series Low VCC Data Retention Timing Waveform (5) (LB#, UB# Controlled) (VCC = 2.2 V to 2.7 V) t CDR Data retention mode tR V CC 2.2 V V DR 2.0 V LB#, UB# ≥ VCC – 0.2 V LB#, UB# 0V Low VCC Data Retention Timing Waveform (6) (LB#, UB# Controlled) (VCC = 2.7 V to 3.6 V) t CDR Data retention mode V CC 2.7 V 2.2 V V DR LB#, UB# 0V Rev.1.00, Aug.05.2003, page 17 of 18 LB#, UB# ≥ VCC – 0.2 V tR R1LV0416C-I Series Sales Strategic Planning Div. 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Renesas Technology Corporation, All rights reserved. Printed in Japan. Colophon 0.0 Rev.1.00, Aug.05.2003, page 18 of 18 R1LV0416C-I Series Revision Record Rev. Date Contents of Modification 1.00 Aug. 05, 2003 Initial issue Rev.1.00, Aug.05.2003, page 19 of 18 Drawn by Approved by