MAX3612ETM+

19-5050; Rev 1; 6/10
EVALUATION KIT AVAILABLE
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
The MAX3612 is a high-performance, precision phaselocked loop (PLL) clock generator optimized for nextgeneration high-speed Ethernet applications that
demand low-jitter clock generation and distribution for
robust high-speed data transmission. The device features subpicosecond jitter generation, excellent powersupply noise rejection, and pin-programmable LVDS/
LVPECL output interfaces. The MAX3612 provides nine
differential outputs divided into three banks. The frequency and output interface of each output bank can be
individually programmed, making this device an ideal
replacement for multiple crystal oscillators and clock distribution ICs on a system board, saving cost and space.
This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN
package and operates from -40°C to +85°C.
Applications
Features
S Inputs
Crystal Interface: 25MHz, 31.25MHz
LVCMOS Input: 25MHz, 31.25MHz, 125MHz, 156.25MHz
Differential Input: 25MHz, 31.25MHz, 125MHz, 156.25MHz
S Outputs
LVDS/LVPECL Outputs: 125MHz, 156.25MHz, 312.5MHz
S Three Individual Output Banks
Pin-Programmable Dividers
Pin-Programmable Output Interface
S Low Phase Jitter
0.34psRMS (12kHz to 20MHz)
0.14psRMS (1.875MHz to 20MHz)
S Excellent Power-Supply Noise Rejection
S Operating Temperature Range: -40NC to +85NC
S +3.3V Supply
Ordering Information
Ethernet Switch/Router
Typical Application Circuits and Pin Configuration appear at
end of data sheet.
PART
TEMP RANGE
PIN-PACKAGE
MAX3612ETM+
-40NC to +85NC
48 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Functional Diagram
LVPECL/LVDS
QA0
QA0
LVPECL/LVDS
MAX3612
QA1
LVPECL/LVDS
QA2
QA2
XOUT
LVPECL/LVDS
XO
LVPECL/LVDS
LVCMOS
QA3
QA3
XIN
CIN
QA1
QA4
PLL, DIVIDERS, MUXES
VCO
QA4
LVPECL/LVDS
QB0
QB0
LVPECL/LVDS
DIN
DIN
QB1
QB1
LVPECL/LVDS
QB2
QB2
LVPECL/LVDS
QC
QC
_
1
MAX3612
General Description
MAX3612
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (VCC, VCCA, VCCQA,
VCCQB, VCCQC).................................................-0.3V to +4.0V
Voltage Range at CIN, IN_SEL, DM, DF, PLL_BP,
DA, DB, DC, QA_CTRL1, QA_CTRL2,
QB_CTRL, QC_CTRL, RES[6:0]............. -0.3V to (VCC + 0.3V)
Voltage Range at DIN, DIN......... (VCC - 2.35V) to (VCC - 0.35V)
Voltage Range at QA[4:0], QA[4:0], QB[2:0],
QB[2:0], QC, QC when LVDS Output.... -0.3V to (VCC + 0.3V)
Current into QA[4:0], QA[4:0], QB[2:0], QB[2:0],
QC, QC when LVPECL Output...................................... -56mA
Voltage Range at XIN............................................-0.3V to +1.2V
Voltage Range at XOUT..............................-0.3V to (VCC - 0.6V)
Continuous Power Dissipation (TA = +70NC)
48-Pin TQFN (derate 40mW/NC above +70NC)...........3200mW
Operating Junction Temperature Range.......... -55NC to +150NC
Storage Temperature Range............................. -65NC to +160NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted. Signal applied
to CIN or DIN/DIN only when selected as the reference clock.) (Note 1)
PARAMETER
Supply Current with PLL
Enabled (Note 2)
SYMBOL
ICC
Supply Current with PLL
Bypassed (Note 2)
CONDITIONS
MIN
TYP
MAX
Configured with LVPECL outputs
150
200
Configured with LVDS outputs
270
360
Configured with LVPECL outputs
100
Configured with LVDS outputs
220
UNITS
mA
mA
LVCMOS/LVTTL CONTROL INPUTS (IN_SEL, DM, DF, DA, DB, DC, PLL_BP, QA_CTRL1, QA_CTRL2, QB_CTRL,
QC_CTRL)
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH
VIN = VCC
Input Low Current
IIL
VIN = 0V
2.0
V
0.8
80
-80
V
FA
FA
LVCMOS/LVTTL CLOCK INPUT (CIN)
Reference Clock Input
Frequency
fREF
Input Amplitude Range
Internally AC-coupled (Note 3)
Input High Current
IIH
VIN = VCC
Input Low Current
IIL
VIN = 0V
Reference Clock Input DutyCycle Distortion
15
160
MHz
1.2
3.6
VP-P
80
-80
40
Input Capacitance
Input Bias Voltage
Input Differential Voltage Swing
VCMI
15
VCC 1.8
%
pF
350
VCC 1.3
MHz
V
150
1800
mVP-P
Single-Ended Voltage Range
VCC 2.0
VCC 0.7
V
Input Differential Impedance
80
Differential Input Capacitance
2
60
1.5
DIFFERENTIAL CLOCK INPUT (DIN, DIN) (Note 4)
Differential Input Frequency
fREF
FA
FA
100
1.5
120
I
pF
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted. Signal applied
to CIN or DIN/DIN only when selected as the reference clock.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
LVDS OUTPUTS (QA[4:0], QA[4:0], QB[2:0], QB[2:0], QC, QC) (Note 5)
Output High Voltage
VOH
Output Low Voltage
VOL
0.925
Differential Output Voltage
|VOD|
250
Change in Magnitude
of Differential Output for
Complementary States
Output Offset Voltage
Change in Magnitude of
Output Offset Voltage for
Complementary States
1.125
D|VOS|
Differential Output Impedance
80
Output Current
Output Current When Disabled
3
Short to ground
6
PLL enabled
Output Duty-Cycle Distortion
100
Short together
1.475
V
400
mV
25
mV
1.3
V
25
mV
140
I
mA
10
VQ_ = VQ_ = 0V to VCC
20% to 80%
Output Rise/Fall Time
UNITS
V
D|VOD|
VOS
MAX
48
PLL bypassed (Note 6)
FA
160
240
50
52
50
ps
%
LVPECL OUTPUTS (QA[4:0], QA[4:0], QB[2:0], QB[2:0], QC, QC) (Note 7)
Output High Voltage
VOH
VCC 1.13
VCC 0.98
VCC 0.83
V
Output Low Voltage
VOL
VCC 1.85
VCC 1.70
VCC 1.55
V
0.5
0.7
0.9
VP-P
Output-Voltage Swing
(Single-Ended)
Output Current When Disabled
VO = 0V to VCC
20% to 80%, differential load = 100I
Output Rise/Fall Time
PLL enabled
Output Duty-Cycle Distortion
10
48
PLL bypassed (Note 6)
FA
140
240
50
52
50
ps
%
PLL SPECIFICATIONS
VCO Frequency Range
625
fVCO
PLL Jitter Transfer Bandwidth
Integrated Phase Jitter at
156.25MHz Output
MHz
130
RJRMS
25MHz crystal
input
12kHz to 20MHz
0.34
1.875MHz to 20MHz
0.14
kHz
1.0
psRMS
25MHz LVCMOS or differential input
(Note 8)
0.34
Supply-Noise Induced Phase
Spur
(Note 9)
-56
dBc
Determinisitic Jitter Induced by
Power-Supply Noise
(Note 9)
6
psP-P
3
MAX3612
ELECTRICAL CHARACTERISTICS (continued)
MAX3612
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40°C to +85°C. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted. Signal applied
to CIN or DIN/DIN only when selected as the reference clock.) (Note 1)
PARAMETER
Nonharmonic and Subharmonic
Spurs
SSB Phase Noise at 312.5MHz
SSB Phase Noise at 156.25MHz
SSB Phase Noise at 125MHz
SYMBOL
CONDITIONS
MIN
TYP
(Note 10)
-70
fOFFSET = 1kHz
-115
fOFFSET = 10kHz
-116
fOFFSET = 100kHz
-122
fOFFSET = 1MHz
-139
fOFFSET R 10MHz
-149
fOFFSET = 1kHz
-122
fOFFSET = 10kHz
-123
fOFFSET = 100kHz
-129
fOFFSET = 1MHz
-145
fOFFSET R 10MHz
-152
fOFFSET = 1kHz
-123
fOFFSET = 10kHz
-124
fOFFSET = 100kHz
-130
fOFFSET = 1MHz
-147
fOFFSET R 10MHz
-153
MAX
UNITS
dBc
dBc/
Hz
dBc/
Hz
dBc/
Hz
Note 1: A series resistor of up to 10.5I is allowed between VCC and VCCA for filtering supply noise when system power-supply
tolerance is VCC = 3.3V Q5%. See Figure 2.
Note 2: Measured with all outputs enabled and unloaded.
Note 3: CIN can be AC- or DC-coupled. See Figure 7. Input high voltage must be ≤ VCC to +0.3V.
Note 4: DIN can be AC- or DC-coupled. See Figure 9.
Note 5: Measured with 100I differential load.
Note 6: Measured with crystal input, or with 50% duty cycle LVCMOS, or differential input.
Note 7: Measured with output termination of 50I to VCC - 2V or Thevenin equivalent.
Note 8: Measured using LVCMOS/LVTTL input with slew rate R 1.0V/ns, or differential input with slew rate R 0.5V/ns.
Note 9: Measured at 156.25MHz output with 200kHz, 50mVP-P sinusoidal signal on the supply using the crystal input and
the power-supply filter shown in Figure 2. See the Typical Operating Characteristics for other supply noise frequencies. Deterministic jitter is calculated from the measured power-supply-induced spurs. For more information, refer to
Application Note 4461: HFAN-04.5.5: Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers.
Note 10: Measured with all outputs enabled and all three banks at different frequencies.
4
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
PLL BYPASS, ALL OUTPUTS LOADED
250
PLL NORMAL, ALL OUTPUTS UNLOADED
200
150
400
100
50
PLL BYPASS, ALL OUTPUTS UNLOADED
0
-40
-15
10
35
60
350
PLL NORMAL
300
250
200
150
450
PLL BYPASS
350
250
50
0
0
10
35
60
QA[2:0] ENABLED
150
50
-15
QA[4:3] AND QA[2:0] ENABLED
200
100
-40
QA[4:3], QA[2:0], AND QB[2:0] ENABLED
300
100
85
QA[4:3], QA[2:0], QB[2:0], AND QC ENABLED
400
85
ALL OUTPUTS DISABLED
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT vs. TEMPERATURE
(LVDS OUTPUTS)
DIFFERENTIAL OUTPUT AT 312.5MHz
(LVPECL)
DIFFERENTIAL OUTPUT AT 156.25MHz
(LVPECL)
300
QA[4:3], QA[2:0], QB[2:0], AND QC ENABLED
MAX3612 toc05
MAX3612 toc06
MAX3612 toc04
350
SUPPLY CURRENT (mA)
500
SUPPLY CURRENT (mA)
350
300
450
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
400
SUPPLY CURRENT vs. TEMPERATURE
(LVPECL OUTPUTS, ALL LOADED)
MAX3612 toc02
PLL NORMAL, ALL OUTPUTS LOADED
450
500
MAX3612 toc01
500
SUPPLY CURRENT vs. TEMPERATURE
(LVDS OUTPUTS, ALL ENABLED)
MAX3612 toc03
SUPPLY CURRENT vs. TEMPERATURE
(LVPECL OUTPUTS, ALL ENABLED)
250
QA[4:3], QA[2:0], AND QB[2:0] ENABLED
200
200mV/div
QA[4:3] AND QA[2:0] ENABLED
150
200mV/div
QA[2:0] ENABLED
100
50
ALL OUTPUTS DISABLED
0
-40
-15
10
35
60
85
500ps/div
1ns/div
DIFFERENTIAL OUTPUT SWING
vs. OUTPUT FREQUENCY
DIFFERENTIAL OUPUT SWING
vs. TEMPERATURE
DIFFERENTIAL OUTPUT SWING (mVP-P)
2000
100mV/div
1800
LVPECL
1600
1400
1200
LVDS
1000
800
600
400
200
1800
LVPECL
1600
1400
1200
LVDS
1000
800
600
400
200
0
0
1.2ns/div
2000
MAX3612 toc09
MAX3612 toc07
DIFFERENTIAL OUTPUT SWING (mVP-P)
DIFFERENTIAL OUTPUT AT 125MHz
(LVDS)
MAX3612 toc08
TEMPERATURE (°C)
10
100
OUTPUT FREQUENCY (MHz)
1000
-40
-15
10
35
60
85
TEMPERATURE (°C)
5
MAX3612
Typical Operating Characteristics
(VCC = 3.3V, TA = +25NC, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25NC, unless otherwise noted.)
DUTY-CYCLE DISTORTION
vs. TEMPERATURE
200
150
100
LVPECL
0
35
60
50.0
49.9
LVPECL
49.8
-80
49.7
-120
-130
-140
-150
49.5
-160
-40
-15
10
35
60
85
10k
1k
100k
1M
10M
100M
PHASE NOISE AT 156.25MHz
PHASE NOISE AT 125MHz
INTEGRATED PHASE JITTER (12kHz TO 20MHz)
vs. TEMPERATURE
-100
-110
-120
-130
PHASE JITTER = 0.36psRMS
INTEGRATED 12kHz TO 20MHz
-70
-80
-90
-100
-110
-120
-130
-140
-140
-150
-150
-160
0.60
INTEGRATED PHASE JITTER (psRMS)
-60
100k
1M
10M
100M
OUTPUT FREQUENCY = 156.25MHz
0.55
0.50
0.45
LVPECL
0.40
0.35
0.30
LVDS
0.25
0.20
-160
10k
MAX3612 toc15
OUTPUT FREQUENCY (MHz)
-90
1k
10k
100k
1M
10M
-40
100M
-15
10
35
60
85
OUTPUT FREQUENCY (MHz)
TEMPERATURE (°C)
JITTER TRANSFER
SPURS INDUCED BY POWER-SUPPLY NOISE
vs. NOISE FREQUENCY
DETERMINISTIC JITTER INDUCED BY POWERSUPPLY NOISE vs. NOISE FREQUENCY
0
MAX3612 toc16
0
-5
SPUR AMPLITUDE (dBc)
-10
-10
-15
-20
-25
-30
-35
fC = 156.25MHz
NOISE = 50mVP-P
-20
-30
LVPECL
-40
-50
-60
LVDS
-70
-40
-45
-80
-50
-90
10k
100k
1M
JITTER FREQUENCY (Hz)
10M
30
25
MAX3612 toc18
OUTPUT FREQUENCY (MHz)
5
1k
-110
TEMPERATURE (°C)
PHASE JITTER = 0.34psRMS
INTEGRATED 12kHz TO 20MHz
1k
-90
-100
49.6
85
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
50.1
PHASE JITTER = 0.32psRMS
INTEGRATED 12kHz TO 20MHz
TEMPERATURE (°C)
-80
6
LVDS
50.2
-70
DETERMINISTIC JITTER (psP-P)
-70
10
50.3
MAX3612 toc14
-60
-15
MAX3612 toc13
-40
MAX3612 toc11
50.4
50
-60
PHASE NOISE (dBc/Hz)
LVDS
PHASE NOISE AT 312.5MHz
MAX3612 toc17
RISE/FALL TIME (ps)
250
50.5
DUTY-CYCLE DISTORTION (%)
MAX3612 toc10
300
MAX3612 toc12
RISE/FALL TIME vs. TEMPERATURE
(20% TO 80%)
JITTER TRANSFER (dB)
MAX3612
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
fC = 156.25MHz
NOISE = 50mVP-P
20
15
LVPECL
10
5
LVDS
0
10
100
NOISE FREQUENCY (kHz)
1000
10
100
NOISE FREQUENCY (kHz)
1000
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
PIN
NAME
FUNCTION
1
DM
LVCMOS/LVTTL Input. Control for input divider M. See Table 3.
2
XIN
Crystal Oscillator Input
3
XOUT
4, 20
VCC
5
IN_SEL
6
PLL_BP
7
RES0
8
DF
Crystal Oscillator Output
Positive Power Supply. Connect to +3.3V.
LVCMOS/LVTTL Input. Three-level control for input mux. See Table 1.
LVCMOS/LVTTL Input. Three-level control for PLL bypass mode. See Table 2.
Reserved. Connect to GND for normal operation.
LVCMOS/LVTTL Input. Control for feedback divider F. See Table 4.
9
QC_CTRL
10
VCCA
Power Supply for Internal Voltage-Controlled Oscillators (VCOs). See Figure 3.
11
RES1
Reserved. Connect to GND for normal operation.
12
RES2
Reserved. Connect to VCC for normal operation.
13
RES3
Reserved. Connect to GND for normal operation.
14
DB
15
RES4
16
DA
17
RES5
MAX3612
Pin Description
LVCMOS/LVTTL Input. Three-level control input for C-bank output interface. See Table 8.
LVCMOS/LVTTL Input. Three-level controls for output divider B. See Table 5.
Reserved. Connect to GND for normal operation.
LVCMOS/LVTTL Input. Three-level controls for output divider A. See Table 5.
Reserved. Connect to GND for normal operation.
18
DC
19
QA_CTRL2
LVCMOS/LVTTL Input. Three-level controls for output divider C. See Table 5.
21
RES6
22, 23
24
QC, QC
VCCQC
Power Supply for C-Bank Differential Output. Connect to +3.3V.
25, 36
VCCQA
Power Supply for A-Bank Differential Outputs. Connect to +3.3V.
26, 27
QA4, QA4
A-Bank Differential Output. Configured as LVPECL, LVDS, or high-Z with the QA_CTRL2 pin.
28, 29
QA3, QA3
A-Bank Differential Output. Configured as LVPECL, LVDS, or high-Z with the QA_CTRL2 pin.
30, 31
QA2, QA2
A-Bank Differential Output. Configured as LVPECL, LVDS, or high-Z with the QA_CTRL1 pin.
32, 33
QA1, QA1
A-Bank Differential Output. Configured as LVPECL, LVDS, or high-Z with the QA_CTRL1 pin.
34, 35
A-Bank Differential Output. Configured as LVPECL, LVDS, or high-Z with the QA_CTRL1 pin.
37
QA0, QA0
VCCQB
38, 39
QB0, QB0
B-Bank Differential Output. Configured as LVPECL, LVDS, or high-Z with the QB_CTRL pin.
40, 41
QB1, QB1
B-Bank Differential Output. Configured as LVPECL, LVDS, or high-Z with the QB_CTRL pin.
42, 43
B-Bank Differential Output. Configured as LVPECL, LVDS, or high-Z with the QB_CTRL pin.
44
QB2, QB2
QA_CTRL1
45
QB_CTRL
LVCMOS/LVTTL Input. Three-level control for B-bank output interface. See Table 7.
46, 47
DIN, DIN
Differential Clock Input. Operates up to 350MHz. This input can accept DC-coupled LVPECL signals, and is internally biased to accept AC-coupled LVDS, CML, and LVPECL signals.
48
CIN
LVCMOS Clock Input. Operates up to 160MHz.
—
EP
Exposed Pad. Connect to supply ground for proper electrical and thermal performance.
LVCMOS/LVTTL Input. Three-level control for QA[4:3] output interface. See Table 6.
Reserved. Connect to GND for normal operation.
C-Bank Differential Output. Configured as LVPECL, LVDS, or high-Z with the QC_CTRL pin.
Power Supply for B-Bank Differential Outputs. Connect to +3.3V.
LVCMOS/LVTTL Input. Three-level control for QA[2:0] output interface. See Table 6.
7
MAX3612
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
Detailed Description
The frequency and output interface of each output bank
can be individually programmed. A PLL bypass mode
is also available for system testing or clock distribution.
The MAX3612 is a low-jitter clock generator optimized
for Ethernet applications. It consists of a selectable
reference clock (on-chip crystal oscillator, LVCMOS
input, or differential input), PLL with on-chip VCO, pinprogrammable dividers and muxes, and three banks of
clock outputs. See Figure 1. The output banks include
nine pin-programmable LVDS/LVPECL output buffers.
IN_SEL
VCC
DM
Crystal Oscillator
The on-chip crystal oscillator provides the low-frequency
reference clock for the PLL. This oscillator requires an
external crystal connected between XIN and XOUT.
See the Crystal Selection and Layout section for more
VCCA
DA
PLL_BP
VCCQA
QA_CTRL1
QA0
QA0
XOUT
CRYSTAL
OSCILLATOR
QA1
1
0
XIN
÷M
PFD
CP
VCO
÷A
QA1
QA2
0/NC
LVCMOS
CIN
QA2
625MHz
NC
QA3
QA3
DIN
DIN
QA4
÷F
QA4
1
QA_CTRL2
VCCQB
QB_CTRL
QB0
MAX3612
QB0
QB1
1
÷B
QB1
QB2
0/NC
QB2
DIVIDER A: 2, 4, 5
DIVIDER B: 2, 4, 5
DIVIDER C: 2, 4, 5
DIVIDER F: 20, 25
DIVIDER M: 1, 5
QC_CTRL
1/NC
÷C
EP
Figure 1. Detailed Functional Diagram
8
DF
DB
DC
QC
QC
0
VCCQC
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
LVCMOS Clock Input
An LVCMOS-compatible clock source can be connected
to CIN to serve as the PLL reference clock. The input is
internally biased to allow AC- or DC-coupling (see the
Applications Information section). It is designed to operate from 15MHz to 160MHz. No signal should be applied
to CIN if not used.
Differential Clock Input
A differential clock source can be connected to DIN
to serve as the PLL reference clock. This input operates from 15MHz to 350MHz and contains an internal
100ω differential termination. This input can accept
DC-coupled LVPECL signals, and is internally biased to
accept AC-coupled LVDS, CML, and LVPECL signals
(see the Applications Information section). No signal
should be applied to DIN if not used.
Phase-Locked Loop (PLL)
The PLL takes the signal from the crystal oscillator,
LVCMOS clock input, or differential clock input and
synthesizes a low-jitter, high-frequency clock. The PLL
contains a phase-frequency detector (PFD), a charge
pump (CP), and a low-phase noise VCO. The VCO output is connected to the PFD input through a feedback
divider. The PFD compares the reference frequency to
the divided-down VCO output and generates a control
signal that keeps the VCO locked to the reference clock.
The high-frequency VCO output clock is sent to the output dividers. To minimize noise-induced jitter, the VCO
supply (VCCA) is isolated from the core logic and output
buffer supplies.
Dividers and Muxes
The dividers and muxes are set with three-level control
inputs. Divider settings and routing information are given
in Tables 1 to 9.
Table 1. PLL Input
IN_SEL
INPUT
0
Crystal Input. XO circuit is disabled when not selected.
1
Differential Input. No signal should be applied to DIN if not selected.
NC
LVCMOS Input. No signal should be applied to CIN if not selected.
Table 2. PLL Bypass
PLL_BP
PLL OPERATION
0
PLL Enabled for Normal Operation. All outputs from the A-, B-, and C-banks are derived from the VCO.
1
PLL Bypassed. Selected input passes directly to the outputs. The VCO is disabled to minimize power consumption and intermodulation spurs. Used for system testing or clock distribution.
NC
The outputs from A-bank and B-bank are derived from the VCO, but the C-bank output is directly driven from the
input signal for purposes of daisy chaining.
Table 3. Input Divider M
Table 4. PLL Feedback Divider F
DM
M DIVIDER RATIO
DF
F DIVIDER RATIO
0
÷1
0
÷25
1
÷5
1
÷20
NC
Not allowed
NC
Not allowed
Note: When the on-chip XO is selected (IN_SEL = 0), the setting DM = 0 is required.
9
MAX3612
information. The XIN and XOUT pins can be left open if
not used.
MAX3612
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
LVDS/LVPECL Clock Outputs
Table 5. Output Divider A, B, C
DA/DB/DC
A, B, C DIVIDER RATIO
0
÷4
1
÷5
NC
÷2
Table 6. A-Bank Output Interface
QA_CTRL1
QA[2:0] OUTPUT
0
QA[2:0] = LVDS
1
QA[2:0] = LVPECL
NC
QA[2:0] disabled to high impedance
QA_CTRL2
QA[4:3] OUTPUT
0
QA[4:3] = LVDS
1
QA[4:3] = LVPECL
NC
QA[4:3] disabled to high impedance
The differential clock outputs (QA[4:0], QB[2:0], QC)
operate up to 350MHz and have a pin-programmable
LVDS/LVPECL output interface. See Tables 6 to 8. When
configured as LVDS, the buffers are designed to drive
transmission lines with a 100ω differential termination.
When configured as LVPECL, the buffers are designed
to drive transmission lines terminated with 50ω to
VCC - 2V. Unused output banks can be disabled to high
impedance and unused outputs can be left open.
Internal Reset
During power-on, a power-on reset (POR) signal is generated to synchronize all dividers. A reset signal is also
generated if any control pin is changed. Outputs within a
bank are phase aligned, but outputs bank-to-bank may
not be phase aligned.
Applications Information
Table 7. B-Bank Output Interface
QB_CTRL
QB[2:0] OUTPUT
0
QB[2:0] = LVDS
1
QB[2:0] = LVPECL
NC
QB[2:0] disabled to high impedance
Table 8. C-Bank Output Interface
QC_CTRL
QC OUTPUT
0
QC = LVDS
1
QC = LVPECL
NC
QC disabled to high impedance
Output Frequency Configuration
Table 9 provides the divider ratios for typical configurations.
Power-Supply Filtering
The MAX3612 is a mixed analog/digital IC. The PLL
contains analog circuitry susceptible to random noise.
To take full advantage of on-board filtering and noise
attenuation, in addition to excellent on-chip power-supply rejection, this part provides a separate power-supply
pin, VCCA, for the VCO circuitry. Figure 2 illustrates the
recommended power-supply filter network for VCCA.
The purpose of this design technique is to ensure clean
input power supply to the VCO circuitry and to improve
Table 9. Divider Configurations
INPUT
FREQUENCY
(MHz)
25
31.25
125
156.25
10
INPUT
DIVIDER
M
÷1
÷5
FEEDBACK
DIVIDER
F
VCO FREQUENCY
(MHz)
÷25
÷20
÷25
÷20
625
OUTPUT
DIVIDERS
A, B, C
OUTPUT
FREQUENCY
(MHz)
÷2
312.5
÷4
156.25
÷5
125
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
Ground Connection
The 48-pin TQFN package features an exposed pad
(EP), which provides a low resistance thermal path for
heat removal from the IC and also the electrical ground.
For proper operation, the EP must be connected to the
circuit board ground plane with multiple vias.
+3.3V ±5%
VCC
0.1µF
10.5Ω
MAX3612
VCCA
0.1µF
10µF
Crystal Selection and Layout
The MAX3612 features an integrated on-chip crystal
oscillator to minimize system implementation cost.
The crystal oscillator is designed to drive a fundamental
mode, AT-cut crystal resonator. See Table 10 for recommended crystal specifications. See Figure 3 for the crystal equivalent circuit and Figure 4 for the recommended
external capacitor connections. The crystal, trace, and
two external capacitors should be placed on the board
as close as possible to the XIN and XOUT pins to reduce
crosstalk of active signals into the oscillator.
The total load capacitance for the crystal is a combination of external and on-chip capacitance. The layout
shown in Figure 5 gives approximately 1.7pF of trace
plus footprint capacitance per side of the crystal.
Note the ground plane is removed under the crystal to
minimize capacitance. There is approximately 2.5pF of
on-chip capacitance between XIN and XOUT. With an
external 27pF capacitor connected to XIN and a 33pF
external capacitor connected to XOUT, the total load
capacitance for the crystal is approximately 18pF. The
XIN and XOUT pins can be left open if not used.
Figure 2. Power-Supply Filter
Table 10. Crystal Selection Parameters
PARAMETER
SYMBOL
MIN
TYP
fOSC
25
Shunt Capacitance
C0
2.0
Load Capacitance
CL
18
Equivalent Series Resistance (ESR)
RS
10
Crystal Oscillation Frequency
MAX
MHz
7.0
pF
pF
Maximum Crystal Drive Level
XTAL
UNITS
50
I
200
FW
27pF
XIN
CRYSTAL
(CL = 18pF)
C0
RS
LS
Figure 3. Crystal Equivalent Circuit
CS
MAX3612
XOUT
33pF
Figure 4. Crystal, Capacitor Connections
11
MAX3612
the overall immunity to power-supply noise. This network requires that the power supply is +3.3V ±5%.
Decoupling capacitors should be used on all other supply pins for best performance. All supply connections
should be driven from the same source.
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
MAX3612
Interfacing with LVCMOS Input
The equivalent LVCMOS input circuit for CIN is given in
Figure 6. This input is internally biased to allow AC- or
DC-coupling, and has 180kI input impedance. See
Figure 7 for the interface circuit. No signal should be
applied to CIN if not used.
Interfacing with Differential Input
The equivalent input circuit for DIN is given in Figure 8.
This input operates up to 350MHz and contains an
internal 100I differential termination as well as a 35I
common-mode termination. The common-mode termination ensures good signal integrity when connected to a
source with large common-mode signals. The input can
accept DC-coupled LVPECL signals, and is internally
biased to accept AC-coupled LVDS, CML, and LVPECL
signals (Figure 9). No signal should be applied to DIN if
not used.
Figure 5. Crystal Layout
1.4V
VCC
VCC
180kΩ
CIN
VCC
ESD
STRUCTURES
ESD
STRUCTURES
DIN
Figure 6. Equivalent CIN Circuit
50Ω
20kΩ
10Ω
VCC
VCC - 1.3V
16pF
50Ω
DC-COUPLED
MAX3612
DIN
CIN
XO
ESD
STRUCTURES
Figure 8. Equivalent DIN Circuit
AC-COUPLED
MAX3612
0.1µF
XO
Figure 7. Interface to CIN
12
CIN
20kΩ
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
MAX3612
150Ω
+3.3V
+3.3V
DIN
Z = 50Ω
LVPECL
100Ω
LVPECL
DIN
Z = 50Ω
The equivalent LVPECL output circuit is given in Figure 10.
These outputs are designed to drive a pair of 50ω transmission lines terminated with 50ω to VTT = VCC - 2V. If a
separate termination voltage (VTT) is not available, other
terminations methods can be used such as those shown
in Figure 11. For more information on LVPECL terminations and how to interface with other logic families, refer
to Application Note 291: HFAN-01.0: Introduction to
LVDS, PECL, and CML.
150Ω
VCC_ _
LVPECL SOURCE DRIVING MAX3612
DIFFERENTIAL INPUT AC-COUPLED
+3.3V
MAX3612
150Ω
0.1µF
Z = 50Ω
LVPECL
0.1µF
Z = 50Ω
Q_ _
+3.3V
DIN
100Ω
LVPECL
Q_ _
DIN
150Ω
ESD
STRUCTURES
LVDS OR CML SOURCE DRIVING MAX3612
DIFFERENTIAL INPUT AC-COUPLED
Figure 10. Equivalent LVPECL Output Circuit
MAX3612
VDD
0.1µF
Z = 50Ω
LVDS OR
CML
0.1µF
Z = 50Ω
+3.3V
DIN
100Ω
LVPECL
DIN
Figure 9. Interfacing to DIN
13
MAX3612
Interfacing with LVPECL Outputs
LVPECL SOURCE DRIVING MAX3612
DIFFERENTIAL INPUT DC-COUPLED
MAX3612
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
DC-COUPLED LVPECL DRIVING THEVENIN EQUIVALENT TERMINATION
+3.3V
+3.3V
+3.3V
130Ω
MAX3612
Q_ _
+3.3V
130Ω
Z = 50Ω
LVPECL
LVPECL
Q_ _
Z = 50Ω
82Ω
82Ω
AC-COUPLED LVPECL DRIVING INTERNAL 100Ω DIFFERENTIAL TERMINATION
+3.3V
VDD
150Ω
MAX3612
Q_ _
0.1µF
Z = 50Ω
LVPECL
100Ω
0.1µF
Q_ _
LVPECL
Z = 50Ω
150Ω
AC-COUPLED LVPECL DRIVING EXTERNAL 50Ω WITH COMMON-MODE TERMINATION
+3.3V
VDD
150Ω
MAX3612
Q_ _
0.1µF
Z = 50Ω
LVPECL
LVPECL
0.1µF
Q_ _
Z = 50Ω
150Ω
50Ω
0.1µF
Figure 11. Interface to LVPECL Outputs
14
50Ω
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
Interfacing with LVDS Outputs
VCC
50Ω
Q_ _
The equivalent LVDS output circuit is given in Figure 12.
These outputs provide 100ω differential output impedance designed to drive a 100ω differential transmission
line terminated with a 100ω differential load. Example
interface circuits are shown in Figure 13. For more information on LVDS terminations and how to interface with
other logic families, refer to Application Note 291: HFAN01.0: Introduction to LVDS, PECL, and CML.
50Ω
Q_ _
ESD
STRUCTURES
• A
n uninterrupted ground plane should be positioned
beneath the clock outputs. The ground plane under
the crystal should be removed to minimize capacitance.
Figure 12. Equivalent LVDS Output Circuit
DC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT
+3.3V
MAX3612
Layout Considerations
The inputs and outputs are the most critical paths for
the MAX3612; great care should be taken to minimize
discontinuities on the transmission lines. Here are some
suggestions for maximizing the performance of the
MAX3612:
+3.3V
• S
upply decoupling capacitors should be placed close
to the supply pins, preferably on the same side of the
board as the MAX3612.
• T
ake care to isolate input traces from the MAX3612
outputs.
Q_ _
Z = 50Ω
LVDS
LVDS*
Q_ _
Z = 50Ω
• T
he crystal, trace, and two external capacitors should
be placed on the board as close as possible to the
XIN and XOUT pins to reduce crosstalk of active signals into the oscillator.
• M
aintain 100ω differential (or 50ω single-ended) transmission line impedance into and out of the part.
• P
rovide space between differential output pairs to
reduce crosstalk, especially if the outputs are operating at different frequencies.
AC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT
+3.3V
MAX3612
VDD
Q_ _
LVDS
Q_ _
• U
se multilayer boards with an uninterrupted ground
plane to minimize EMI and crosstalk.
Refer to the MAX3612 evaluation kit for more information.
0.1µF
Chip Information
Z = 50Ω
LVDS*
0.1µF
PROCESS: BiCMOS
Z = 50Ω
*100Ω DIFFERENTIAL INPUT IMPEDANCE ASSUMED.
Figure 13. Interface to LVDS Outputs
15
MAX3612
VREG
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
QA0
QA1
QA1
QA2
QA2
QA3
QA3
QA4
QA4
VCCQA
36
QA0
VCCQA
TOP VIEW
35
34
33
32
31
30
29
28
27
26
25
VCCQB
37
24
VCCQC
QB0
38
23
QC
QB0
39
22
QC
QB1
40
21
RES6
QB1
41
20
VCC
QB2
42
19
QA_CTRL2
QB2
43
18
DC
QA_CTRL1
44
17
RES5
QB_CTRL
45
16
DA
46
15
RES4
14
DB
13
RES3
4
5
6
7
8
9
10
11
12
DF
QC_CTRL
VCCA
RES1
RES2
3
RES0
2
PLL_BP
1
VCC
48
IN_SEL
47
CIN
XOUT
DIN
*EP
+
XIN
DIN
MAX3612
DM
MAX3612
Pin Configuration
THIN QFN
(7mm × 7mm × 0.8mm)
*THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION.
16
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
+3.3V
10.5Ω
10µF
0.1µF
0.1µF
VCCA
27pF
VCC
0.1µF
VCCQA
VCCQB
0.1µF
0.1µF
150Ω
VCCQC
312.5MHz
LVPECL
Z = 50Ω
QA[4:0]
XIN
0.1µF
25MHz
XOUT
NC
CIN
NC
DIN
NC
DIN
100Ω
0.1µF
Z = 50Ω
QA[4:0]
33pF
ASIC WITH LVPECL
TERMINATION
150Ω
IN_SEL
MAX3612
PLL_BP
QB[2:0]
156.25MHz
LVDS
Z = 50Ω
ASIC WITH LVDS
TERMINATION
100Ω
DM
DF
NC
+3.3V
QB[2:0]
Z = 50Ω
QC
125MHz
LVDS
Z = 50Ω
DA
DB
DC
RES[1:0]
ASIC WITH LVDS
TERMINATION
100Ω
RES2
RES[6:3]
QC
Z = 50Ω
QA_CTRL1
QA_CTRL2
QB_CTRL
QC_CTRL
EP
17
MAX3612
Typical Application Circuits
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
MAX3612
Typical Application Circuits (continued)
CLOCK GENERATOR FOR ETHERNET
XIN
25MHz
MAX3612
XOUT
QA[4:0]
312.5MHz
LVPECL OR LVDS
BACKPLANE
TRANSCEIVER
QB[2:0]
156.25MHz
LVPECL OR LVDS
10GbE PHY
QC
125MHz
LVPECL OR LVDS
1GbE PHY
CLOCK GENERATOR FOR ETHERNET WITH DAISY CHAIN
XIN
25MHz
MAX3612
XOUT
QA[4:0]
312.5MHz
LVPECL OR LVDS
BACKPLANE
TRANSCEIVER
QB[2:0]
312.5MHz
LVPECL OR LVDS
BACKPLANE
TRANSCEIVER
QA[4:0]
156.25MHz
LVPECL OR LVDS
10GbE PHY
QB[2:0]
125MHz
LVPECL OR LVDS
1GbE PHY
QC
125MHz
LVPECL OR LVDS
1GbE PHY
QC
156.25MHz LVPECL
DIN
MAX3612
Package Information
For the latest package outline information and land patterns, go to http://www.microsemi.com . Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
18
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
48 TQFN-EP
T4877+4
21-0144
90-0130
Low-Jitter Clock Generator
with Nine LVDS/LVPECL Outputs
REVISION
NUMBER
REVISION
DATE
0
11/09
Initial release
6/10
Added the lead and soldering temperatures to the Absolute Maximum Ratings section; changed the descriptions in the Pin Description table for RES2 (connect to
VCC) and RES6 (connect to GND); replaced Figure 5 with customer board layout;
revised the RES pin connections to match the Pin Description descriptions in the
Typical Application Circuits; updated the package code and added the land pattern
no. to the Package Information table
1
DESCRIPTION
PAGES
CHANGED
—
2, 7, 12, 17, 18
19
MAX3612
Revision History
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