SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996 D D EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Flat (W), and DIP (J,N) Packages SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, OR PW PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND description The ’AC74 are dual positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q 1D 1CLR NC VCC 2CLR SN54AC74 . . . FK PACKAGE (TOP VIEW) 1CLK NC 1PRE NC 1Q 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2D NC 2CLK NC 2PRE 1Q GND NC 2Q 2Q The SN54AC74 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74AC74 is characterized for operation from –40°C to 85°C. 4 NC – No internal connection FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H† H† H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 † This configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996 logic symbol† 1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 4 2 1 5 S 3 1Q C1 1D 6 1Q R 10 9 11 2Q 12 8 13 2Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, PW, and W packages. logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . 1.25 W DB package . . . . . . . . . . . . . . . . . . . 0.5 W N package . . . . . . . . . . . . . . . . . . . . 1.1 W PW package . . . . . . . . . . . . . . . . . . . 0.5 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. recommended operating conditions (see Note 3) VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V SN54AC74 SN74AC74 MIN MAX MIN MAX 2 6 2 6 2.1 2.1 3.15 3.15 3.85 3.85 VIL Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH High-level output current IOL ∆t/∆v VCC = 4.5 V VCC = 5.5 V Low-level output current 0.9 1.35 0 VCC VCC –12 –12 –24 –24 VCC = 5.5 V VCC = 3 V –24 –24 12 12 VCC = 4.5 V VCC = 5.5 V 24 24 24 24 Input transition rise or fall rate • DALLAS, TEXAS 75265 V 1.65 0 VCC = 3 V VCC = 4.5 V TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. POST OFFICE BOX 655303 0.9 1.65 V V 1.35 VCC VCC UNIT V V mA mA 0 8 0 8 ns/V –55 125 –40 85 °C 3 SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –50 µA IOH = –12 mA VOH IOH = –24 24 mA IOH = –50 mA† IOH = –75 mA† IOL = 24 mA IOL = 50 mA† IOL = 75 mA† II Control pins ICC Ci SN74AC74 MIN MIN MAX 3V 2.9 4.49 2.9 2.9 4.5 V 4.4 5.49 4.4 4.4 5.5 V 5.4 5.49 5.4 5.4 3V 2.56 2.4 2.46 4.5 V 3.86 3.7 3.76 5.5 V 4.86 4.7 4.76 3.85 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 5.5 V 0.001 0.1 0.1 0.1 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 V 1.65 1.65 55V 5.5 5.5 V 5V UNIT V 3V 5.5 V IO = 0 MAX 3.85 5.5 V VI = VCC or GND VI = VCC or GND, VI = VCC or GND SN54AC74 5.5 V IOL = 12 mA Data pins TA = 25°C TYP MAX 5.5 V IOL = 50 µA VOL MIN ±0.1 ±1 ±1 ±0.1 ±1 ±1 2 40 20 3 µA µA pF † Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. " timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock 4 Clock frequency tw Pulse duration tsu Set p time, Setup time data before CLK↑ th Hold time, data after CLK↑ 0 100 SN54AC74 SN74AC74 MIN MAX MIN MAX 0 100 0 100 PRE or CLR low 5.5 8 7 CLK 5.5 8 7 Data 4 5 4.5 PRE or CLR inactive 0 0.5 0 0.5 0.5 0.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz ns ns ns SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996 " timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency 0 tw Pulse duration tsu Set p time, Setup time data before CLK↑ th Hold time, data after CLK↑ 140 SN54AC74 SN74AC74 MIN MAX MIN MAX 0 140 0 140 PRE or CLR low 4.5 5.5 5 CLK 4.5 5.5 5 Data 3 4 3 PRE or CLR inactive 0 0.5 0 0.5 0.5 0.5 UNIT MHz ns ns ns " switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q TA = 25°C MIN TYP MAX SN54AC74 SN74AC74 MIN MAX MIN 70 MAX 100 125 3.5 8 12 1 13 2.5 95 13 4 10.5 12 1 14 3.5 13.5 4.5 8 13.5 1 17.5 4 16 3.5 8 14 1 13.5 3.5 14.5 UNIT MHz ns ns " switching characteristics over recommended operating free-air temperature range, VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q TA = 25°C MIN TYP MAX SN54AC74 SN74AC74 MIN MIN MAX 95 MAX 140 160 125 2.5 6 9 1 9.5 2 10 3 8 9.5 1 10.5 2.5 10.5 3.5 6 10 1 12 3 10.5 2.5 6 10 1 10 2.5 10.5 UNIT MHz ns ns operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP 45 UNIT pF 5 SN54AC74, SN74AC74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS521C – AUGUST 1995 – REVISED SEPTEMBER 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open TEST S1 tPLH/tPHL Open 500 Ω CL = 50 pF (see Note A) tw LOAD CIRCUIT VCC VCC 50% VCC Input 0V VOLTAGE WAVEFORMS tPHL tPLH 50% VCC VOH 50% VCC VOL VCC 50% VCC Timing Input 0V tPLH tPHL Out-of-Phase Output 50% VCC 50% VCC 0V In-Phase Output 50% VCC Input 50% VCC VOH 50% VCC VOL th tsu Data Input VCC 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 v 2.5 ns, tf v 2.5 ns. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated