HD74AC195 4-bit Parallel-Access Shift Register REJ03D0260–0200Z (Previous ADE-205-380 (Z)) Rev.2.00 Jul.16.2004 Description This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q0 towards Q3. Parallel loading is accomplished by applying the four bits of data, and taking the PE Input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the CP input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the PE input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or toggle flip-flop as shown in the function table. Features • Shift Right and Parallel Load Capability • J-K (D-Type) Inputs to First Stage • Complement Output from Last Stage • Asynchronous Master Reset • Outputs Source/Sink 24 mA • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74AC195FPEL SOP-16 pin (JEITA) FP-16DAV FP EL (2,000 pcs/reel) HD74AC195RPEL SOP-16 pin (JEDEC) FP-16DNV RP EL (2,500 pcs/reel) Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code. Rev.2.00, Jul.16.2004, page 1 of 7 HD74AC195 Pin Arrangement MR 1 16 VCC J 2 15 Q0 K 3 14 Q1 D0 4 13 Q2 D1 5 12 Q3 D2 6 11 Q3 D3 7 10 CP GND 8 9 PE (Top view) Logic Symbol PE D0 D1 D2 D3 J CP Q3 K MR Rev.2.00, Jul.16.2004, page 2 of 7 Q0 Q1 Q2 Q3 HD74AC195 Pin Names CP D0 to D3 PE MR J, K Q0 to Q3, Q3 Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Parallel Enable Input Asynchronous Master Reset J-K or D Type Serial Inputs Outputs Timing Diagram CP MR J K PE H D0 L D1 H D2 L D3 Q0 Q1 Q2 Q3 Serial Shift Clear Serial Shift Load Mode Select-Function Table Inputs MR Operating Modes Asynchronous Reset L Shift, Set First Stage Shift, Reset First Stage Shift, Toggle First Stage Shift, Retain First Stage PE CP X Outputs K J Dn Q0 Q1 Q2 Q3 Q3 X X X X L L L L H H H H H H L H L X X H L q0 q0 q1 q1 q2 q2 q2 q2 H H H H H L L H X X q0 q0 q0 q0 q1 q1 q2 q2 q2 q2 Parallel Load H L X X dn d0 d1 d2 d3 d3 H : HIGH Voltage Level L : LOW Voltage Level X : Immaterial Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH transition. : LOW-to-HIGH clock transition. Rev.2.00, Jul.16.2004, page 3 of 7 HD74AC195 Logic Diagram K D3 D2 D1 VCC J D0 VCC PE CP MR Q3 Q3 Q2 Q1 Q0 Absolute Maximum Ratings Item Symbol Ratings Unit Condition Supply voltage DC input diode current VCC IIK –0.5 to 7 –20 V mA VI 20 –0.5 to Vcc+0.5 mA V VI = Vcc+0.5V DC input voltage DC output diode current IOK –50 50 mA mA VO = –0.5V VO = Vcc+0.5V DC output voltage DC output source or sink current VO IO –0.5 to Vcc+0.5 ±50 V mA DC VCC or ground current per output pin Storage temperature ICC, IGND Tstg ±50 –65 to +150 mA °C VI = –0.5V Recommended Operating Conditions Supply voltage Item Symbol VCC 2 to 6 V Input and output voltage Operating temperature VI, VO Ta 0 to VCC –40 to +85 V °C Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC tr, tf 8 ns/V Rev.2.00, Jul.16.2004, page 4 of 7 Ratings Unit Condition VCC = 3.0V VCC = 4.5 V VCC = 5.5 V HD74AC195 DC Characteristics Item Input Voltage Symbol VIH VIL Output voltage VOH VOL Ta = 25°°C Vcc (V) 3.0 min. 2.1 typ. 1.5 max. — Ta = –40 to +85°°C min. max. 2.1 — 4.5 5.5 3.15 3.85 2.25 2.75 — — 3.15 3.85 — — 3.0 4.5 — — 1.50 2.25 0.9 1.35 — — 0.9 1.35 5.5 3.0 — 2.9 2.75 2.99 1.65 — — 2.9 1.65 — 4.5 5.5 4.4 5.4 4.49 5.49 — — 4.4 5.4 — — 3.0 4.5 2.58 3.94 — — — — 2.48 3.80 — — 5.5 3.0 4.94 — — 0.002 — 0.1 4.80 — — 0.1 4.5 5.5 — — 0.001 0.001 0.1 0.1 — — 0.1 0.1 3.0 4.5 — — — — 0.32 0.32 — — 0.37 0.37 Unit V Condition VOUT = 0.1 V or VCC –0.1 V VOUT = 0.1 V or VCC –0.1 V V VIN = VIL or VIH IOUT = –50 µA VIN = VIL or VIH IOH = –12 mA IOH = –24 mA IOH = –24 mA VIN = VIL or VIH IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA IOL = 24 mA Input leakage current IIN 5.5 5.5 — — — — 0.32 ±0.1 — — 0.37 ±1.0 µA VIN = VCC or GND IOL = 24 mA Dynamic output current* IOLD IOHD 5.5 5.5 — — — — — — 86 –75 — — mA mA VOLD = 1.1 V VOHD = 3.85 V Quiescent supply current ICC 5.5 — — 8.0 — 80 µA VIN = VCC or ground *Maximum test duration 2.0 ms, one output loaded at a time. AC Characteristics Item Symbol VCC (V)*1 Ta = +25°C CL = 50 pF Min Typ Max Ta = –40°C to +85°C CL = 50 pF Min Max Unit Maximum clock frequency fmax 3.3 5.0 75 100 — — — — 65 85 — — MHz Propagation delay CP to Qn or Q3 tPLH 3.3 5.0 1.0 1.0 9.0 5.5 13.0 10.0 1.0 1.0 15.0 11.5 ns Propagation delay CP to Qn or Q2 tPHL 3.3 5.0 1.0 1.0 9.0 6.5 13.0 10.0 1.0 1.0 15.0 11.5 ns Propagation delay MR to Q2 tPLH 3.3 5.0 1.0 1.0 7.5 5.5 10.5 8.0 1.0 1.0 12.0 9.5 ns Propagaion delay MR to Qn tPHL 3.3 5.0 1.0 1.0 6.0 5.0 9.0 7.0 1.0 1.0 10.5 8.0 ns Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Rev.2.00, Jul.16.2004, page 5 of 7 HD74AC195 AC Operating Requirements Ta = +25°C CL = 50 pF Item Setup time, HIGH or LOW Symbol VCC (V)*1 Typ tsu 3.3 3.0 J, K or Dn to CP Hold time, HIGH or LOW th 5.0 3.3 J, K or Dn to CP Setup time, HIGH or LOW Ta = –40°C to +85°C CL = 50 pF Guaranteed Minimum 5.5 7.0 ns Unit 2.0 –0.5 4.0 2.0 5.0 3.5 ns 0.5 3.5 1.5 5.0 2.0 7.0 ns tsu 5.0 3.3 PE to CP Hold time, HIGH or LOW th 5.0 3.3 2.5 –2.0 4.0 0.0 5.0 0.0 ns PE to CP Recovery time trec 5.0 3.3 –1.5 –1.5 0.0 0.5 0.0 0.5 ns MR to CP Pulse width tw 5.0 3.3 –1.0 –3.0 0.5 5.5 0.5 7.0 ns 5.0 –3.0 4.5 5.0 Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Input capacitance Power dissipation capacitance Rev.2.00, Jul.16.2004, page 6 of 7 Symbol CIN CPD Typ 4.5 125 Unit pF pF Condition VCC = 5.5 V VCC = 5.0 V HD74AC195 Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.40 ± 0.06 0.20 7.80 +– 0.30 1.15 0 ˚ – 8˚ 0.10 ± 0.10 0.80 Max *0.20 ± 0.05 2.20 Max 5.5 16 0.70 ± 0.20 0.15 0.12 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-16DAV — Conforms 0.24 g As of January, 2003 Unit: mm 9.9 10.3 Max 9 1 8 0.635 Max *0.40 ± 0.06 0.15 *0.20 ± 0.05 1.27 0.11 0.14 +– 0.04 1.75 Max 3.95 16 0.10 6.10 +– 0.30 1.08 0˚ – 8˚ + 0.67 0.60 – 0.20 0.25 M *Ni/Pd/Au plating Rev.2.00, Jul.16.2004, page 7 of 7 Package Code JEDEC JEITA Mass (reference value) FP-16DNV Conforms Conforms 0.15 g Sales Strategic Planning Div. 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