HD74LV2GT123A Retriggerable Monostable Multivibrator / CMOS Logic Level Shifter REJ03D0004-0300Z Rev.3.00 Oct.22.2003 Description The HD74LV2GT123A features output pulse duration control by three methods. In the first method, the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high. The basic pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. Once triggered, the basic pulse duration can be extended by retriggering the gated low level active (A) or high level active (B) input. Pulse duration can be reduced by taking CLR low. The output pulse equation is simply : tWQ = Cext • Rext. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • Control input is TTL compatible input level. Supply voltage range : 3.0 to 5.5 V Operating temperature range : –40 to +85°C • Logic-level translate function 3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V) 1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V) • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) • Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) • All the logical inputs have hysteresis voltage for the slow transition. • Ordering Information Part Name Package Type Package Code Package Taping Abbreviation Abbreviation (Quantity) HD74LV2GT123AUSE SSOP-8 pin TTP-8DBV US Rev.3.00, Oct.22.2003, page 1 of 1 E (3,000 pcs / Reel) HD74LV2GT123A Outline and Article Indication • HD74LV2GT123A Index band Lot No. Y M W T 2 3 Y : Year code (the last digit of year) M : Month code W : Week code SSOP–8 Marking Function Table Inputs CLR A B Output Q L X X L H H X L H X L L H L ↑ H ↓ H ↑ L H H : High level L : Low level X : Immaterial ↑ : Low to high transition ↓ : High to low transition : High level pulse Rev.3.00, Oct.22.2003, page 2 of 13 HD74LV2GT123A Pin Arrangement A 1 8 VCC B 2 7 Rext / Cext CLR 3 6 Cext GND 4 5 Q (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 Symbol Ratings Unit VCC –0.5 to 7.0 V VI –0.5 to 7.0 V VO –0.5 to VCC + 0.5 V –0.5 to 7.0 Test Conditions Output : H or L VCC : OFF Input clamp current IIK –20 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±25 mA VO = 0 to VCC Continuous current through VCC or GND ICC or IGND ±50 mA Maximum power dissipation *3 at Ta = 25°C (in still air) PT 200 mW Storage temperature Tstg –65 to 150 °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.3.00, Oct.22.2003, page 3 of 13 HD74LV2GT123A Recommended Operating Conditions Item Symbol Min Typ Max Unit Supply voltage range VCC 3.0 — 5.5 V Input voltage range VI 0 — 5.5 V Output voltage range VO 0 — VCC V Output current IOH — — –6 mA — — –12 VCC = 4.5 to 5.5 V — — 6 VCC = 3.0 to 3.6 V — — 12 VCC = 4.5 to 5.5 V 0 — 100 0 — 20 — IOL Input transition rise or fall rate ∆t / ∆v ns / V VCC = 3.0 to 3.6 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V External timing resistance Rext 1 — External capacitance Cext — Unlimited — F Supply transition rise rate ∆t / ∆VCC 1 — — ms / V –40 — 85 °C Cext Rext/ Cext Operating free-air temperature Ta Conditions kΩ VCC = 4.5 to 5.5 V Note: Unused or floating inputs must be held high or low. Logic Diagram A B Q CLR CLR Rev.3.00, Oct.22.2003, page 4 of 13 Q HD74LV2GT123A Electrical Characteristic • Ta = –40 to 85°C Item Symbol VCC (V) * Input voltage VIH VIL Hysteresis voltage Output voltage VH VOH VOL Min Typ Max Unit 3.0 to 3.6 1.5 — — V 4.5 to 5.5 2.0 — — 3.0 to 3.6 — — 0.6 4.5 to 5.5 — — 0.8 3.3 — 0.10 — 5.0 — 0.15 — V V Test condition VT+ – VT– IOH = –50 µA Min to Max VCC–0.1 — — 3.0 2.48 — — IOH = –6 mA 4.5 3.8 — — IOH = –12 mA Min to Max — — 0.1 IOL = 50 µA 3.0 — — 0.44 IOL = 6 mA 4.5 — — 0.55 IOL = 12 mA Input current IIN 0 to 5.5 — — ±1 µA VIN = 5.5 V or GND Input current Rext / Cext IIN 5.5 — — ±2.5 µA VIN = VCC or GND Quiescent supply current ICC 5.5 — — 10 µA VIN = VCC or GND, IO = 0 ICC–T 5.5 — — 1.5 mA One input VIN = 3.4 V, other input VCC or GND ∆ICC 4.5 — — 650 µA 5.5 — — 975 VIN = VCC or GND Rext / Cext = 0.5VCC Output leakage current IOFF 0 — — 5 µA VIN or VO = 0 to 5.5 V Input capacitance 5.0 — 3.0 — pF VIN = VCC or GND Active state supply current CIN Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.3.00, Oct.22.2003, page 5 of 13 HD74LV2GT123A Switching Characteristics • VCC = 3.3 ± 0.3 V Ta = 25°C Test Ta = –40 to 85°C FROM TO Item Symbol Min Typ Max Min Max Unit Conditions (Input) Propagation delay time tPLH — 10.0 21.0 1.0 24.0 ns — 11.5 24.5 1.0 27.5 — 8.0 16.0 1.0 18.5 — 9.5 19.5 1.0 22.0 — 10.0 22.5 1.0 26.0 — 11.5 26.0 1.0 29.5 — 150 240 — 300 ns CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ 90 100 110 90 110 µs CL = 50 pF, Cext = 0.01 µF, Rext = 10 kΩ 0.9 1.0 1.1 0.9 1.1 ms CL = 50 pF, Cext = 0.1 µF, Rext = 10 kΩ 5.0 — — 5.0 — ns A, B or CLR — 30 — — — ns A or B (Rext = 1 kΩ, Cext = 100 pF) — 1.2 — — — µs A or B (Rext = 1 kΩ, Cext = 0.01 µF) tPHL tPLH Output pulse width Pulse width twQ tw Retrigger time trr CL = 15 pF (Output) A or B Q CLR Q CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CLR Q (Trigger) • VCC = 5.0 ± 0.5 V Ta = 25°C Test Ta = –40 to 85°C FROM TO Item Symbol Min Typ Max Min Max Unit Conditions (Input) Propagation delay time tPLH — 7.3 12.0 1.0 14.0 ns — 8.5 14.0 1.0 16.0 — 5.9 9.4 1.0 11.0 — 7.5 11.4 1.0 13.0 — 7.3 12.9 1.0 15.0 — 8.7 14.9 1.0 17.0 — 140 200 — 240 ns CL = 50 pF, Cext = 28 pF, Rext = 2 kΩ 90 100 110 90 110 µs CL = 50 pF, Cext = 0.01 µF, Rext = 10 kΩ 0.9 1.0 1.1 0.9 1.1 ms CL = 50 pF, Cext = 0.1 µF, Rext = 10 kΩ 5.0 — — 5.0 — ns A, B or CLR — 20 — — — ns A or B (Rext = 1 kΩ, Cext = 100 pF) — 0.95 — — — µs A or B (Rext = 1 kΩ, Cext = 0.01 µF) tPHL tPLH Output pulse width Pulse width twQ tw Retrigger time trr Rev.3.00, Oct.22.2003, page 6 of 13 CL = 15 pF (Output) A or B Q CLR Q CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF CLR Q (Trigger) HD74LV2GT123A Operating Characteristics • CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 5.0 31.0 — pF f = 10 MHz — Test Circuit VCC Cext – Input See Function Table VCC Rext Cext = 28 pF or 100 pF or 0.01 µF or 0.1 µF Rext = 1 kΩ or 2 kΩ or 5 kΩ or 10 kΩ + Cext Rext/ Cext A VCC Q B Output C L = 15 pF or 50 pF CLR GND Note : C L includes the probe and jig capacitance. Rev.3.00, Oct.22.2003, page 7 of 13 HD74LV2GT123A Timing Diagram t rr A B CLR Rext/ Cext Q tw tw t w +t rr Caution in use In order to prevent any malfunctions due to noise, connect a high frequency performance capacitor between Vcc and GND, and keep the wiring between the External components and Cext, Rext/Cext pins as short as possible. Large values of Cext may cause problems when powering down the HD74LV2GT123A because of the amount of energy stored in the capacitor. When a system containing this device is powered down, the capacitor may discharge from Vcc through the protection diodes at pin 7 pin. Current through the input protection diodes must be limited to 20 mA; therefore, the turn-off time of the Vcc power supply must not be faster than t = Vcc • Cext/(20 mA). For example, if Vcc = 5 V and Cext = 22 µF, the Vcc supply must turn off no faster than t = (5 V) • (22 µF)/ 20 mA = 5.5 ms. This is usually not a problem because power supplies are heavily filtered and cannot discharge at this rate. When a more rapid decrease of Vcc to zero volts occurs, the HD74LV2GT123A may sustain damage. To avoid this possibility, use an external calmping diode. The input pins for unused circuit should be used under conditions to fix the outputs to avoid malfunction caused by noises. Also, it's recommended that Rext / Cext terminals are open and external parts are not connected to. Rev.3.00, Oct.22.2003, page 8 of 13 HD74LV2GT123A • Waveform – 1 Input A tf VI 90% Vref 10% GND tr VI 90% Vref Input B 10% GND tf tr 90% Vref Input CLR 10% tr 90% Vref 10% 90% Vref 10% VI GND t w (L) t PLH (trigger) t PHL VOH Output Q 50% 50% VOL Rev.3.00, Oct.22.2003, page 9 of 13 HD74LV2GT123A • Waveform – 2 Input A tf tr 90% Vref tr 90% Vref 10% 10% 90% Vref 10% t w (H) Input B GND t w (L) tr tf VI tf 90% Vref 90% Vref 10% 10% t w (L) VI 90% Vref 10% t w (H) GND VOH Output Q 50% 50% VOL t w (out) • Waveform – 3 Input A tf tf tr 90% Vref 90% 10% VI 90% Vref 10% 10% t rr tf tr Input B 90% Vref tr 90% 10% GND 90% Vref 10% 10% VI GND VOH Output Q 50% 50% VOL t w (out) + t rr INPUTS VCC (V) VI Vref tr / tf 3.3±0.3 2.5 V ≤ 3.0 ns 50% ≤ 3.0 ns 1.5 V 5.0±0.5 3V Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω. 2. The output are measured one at a time with one transition per measurement. Rev.3.00, Oct.22.2003, page 10 of 13 HD74LV2GT123A Application Data Vcc = 5.0 V Output pulse width tWQ (µs) 10000.0 1000.0 100.0 10.0 Rext 1 kΩ 10 kΩ 100 kΩ 1 MΩ 1.0 0.1 10 2 10 3 10 4 Timing capacitance 10 5 10 6 10 7 Cext (pF) Vcc = 3.3 V Output pulse width tWQ (µs) 10000.0 1000.0 100.0 10.0 Rext 1 kΩ 10 kΩ 100 kΩ 1 MΩ 1.0 0.1 10 2 10 3 10 4 Timing capacitance Rev.3.00, Oct.22.2003, page 11 of 13 10 5 Cext (pF) 10 6 10 7 HD74LV2GT123A Rext = 2 kΩ 1.4 Coefficient of output pulse width K Cext 1000 pF 10000 pF 100000 pF 1000000 pF 1.3 1.2 1.1 1.0 0.9 0.8 3.0 3.5 4.0 4.5 Supply voltage 5.0 5.5 6.0 VCC (V) Rext = 10kΩ 1.4 K Cext 1000pF 10000pF 100000pF 1000000pF Coefficient of output pulse width 1.3 1.2 1.1 1.0 0.9 0.8 3.0 3.5 4.0 Supply voltage Rev.3.00, Oct.22.2003, page 12 of 13 4.5 VCC (V) 5.0 5.5 6.0 HD74LV2GT123A Package Dimensions 2.0 ± 0.2 1.5 ± 0.2 + 0.1 (0.17) 8 − 0.2 − 0.05 Package Code JEDEC JEITA Mass (reference value) Rev.3.00, Oct.22.2003, page 13 of 13 + 0.1 0.13 − 0.05 0 − 0.1 0.7 ± 0.1 (0.4) 2.3 ± 0.1 (0.5) (0.5) (0.5) 3.1 ± 0.3 (0.4) Unit: mm TTP–8DBV 0.010 g Sales Strategic Planning Div. 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