HD74LV2GT125A Dual Bus Buffer with 3–state Output / CMOS Logic Level Shifter REJ03D0148–0200Z (Previous ADE-205-676A (Z)) Rev.2.00 Oct.23.2003 Description The HD74LV2GT125A has dual bus buffer with 3–state output in an 8 pin package. Output is disabled when the associated output enable (OE) input is high. To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. The input protection circuitry on this device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high-voltage power supply. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • TTL compatible input level. Supply voltage range : 3.0 to 5.5 V Operating temperature range : –40 to +85°C • Logic-level translate function 3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V) 1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V) • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z) • Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) • All the logical input has hysteresis voltage for the slow transition. • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV2GT125AUSE SSOP-8 pin TTP-8DBV US E (3,000 pcs/reel) Rev.2.00, Oct.23.2003, page 1 of 1 HD74LV2GT125A Outline and Article Indication • HD74LV2GT125A Index band Lot No. Y M W T 2 5 SSOP-8 Marking Function Table Inputs OE A Output Y L H H L L L H X Z H : High level L : Low level X : Immaterial Z : High impedance Rev.2.00, Oct.23.2003, page 2 of 8 Y : Year code (the last digit of year) M : Month code W : Week code HD74LV2GT125A Pin Arrangement OE1 1 8 VCC A1 2 7 OE2 Y2 3 6 Y1 GND 4 5 A2 (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage range *1 Output voltage range *1, 2 Symbol Ratings Unit Test Conditions VCC –0.5 to 7.0 V VI –0.5 to 7.0 V VO –0.5 to VCC + 0.5 V –0.5 to 7.0 Output : H or L VCC : OFF or output : Z Input clamp current IIK –20 mA VI < 0 Output clamp current IOK ±50 mA VO < 0 or VO > VCC Continuous output current IO ±25 mA VO = 0 to VCC Continuous current through VCC or GND ICC or IGND ±50 mA Maximum power dissipation *3 at Ta = 25°C (in still air) PT 200 mW Storage temperature Tstg –65 to 150 °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.2.00, Oct.23.2003, page 3 of 8 HD74LV2GT125A Recommended Operating Conditions Item Symbol Ratings Unit Supply voltage VCC 3.0 to 5.5 V Input voltage VIN 0 to 5.5 V Output voltage VOUT 0 to VCC V 0 to 5.5 Test Conditions Output : Z Operating temperature Topr –40 to +85 Input rise / fall time tr, tf 0 to 100 (VCC = 3.0 to 3.6 V) ns °C 0 to 20 (VCC = 4.5 to 5.5 V) Electrical Characteristics • Ta = –40 to 85°C Item Symbol VCC (V) * Min Typ Max Unit Test condition Input voltage VIH 3.0 to 3.6 1.5 — — V 4.5 to 5.5 2.0 — — 3.0 to 3.6 — — 0.6 4.5 to 5.5 — — 0.8 3.3 — 0.10 — 5.0 — 0.15 — Min to Max VCC–0.1 — — 3.0 2.48 — — IOH = –6 mA 4.5 3.8 — — IOH = –12 mA Min to Max — — 0.1 IOL = 50 µA 3.0 — — 0.44 IOL = 6 mA 4.5 — — 0.55 IOL = 12 mA VIL Hysteresis voltage Output voltage VH VOH VOL V VT+ – VT– V IOH = –50 µA Input current IIN 0 to 5.5 — — ±1 µA VIN = 5.5 V or GND Off state output current IOZ Min to Max — — ±5 µA VO = 5.5 V or GND Quiescent supply current ICC 5.5 — — 10 µA VIN = VCC or GND, IO = 0 ∆ICC 5.5 — — 1.5 mA One input VIN = 3.4 V, other input VCC or GND Output leakage current IOFF 0 — — 5 µA VO = 5.5 V Input capacitance CIN 5.0 — 3.0 — pF VIN = VCC or GND Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Rev.2.00, Oct.23.2003, page 4 of 8 HD74LV2GT125A Switching Characteristics • VCC = 3.3 ± 0.3 V Ta = 25°C Test Ta = –40 to 85°C FROM Item Symbol Min Typ Max Min Max Unit Conditions (Input) Propagation delay time tPLH tPHL — 4.5 9.0 1.0 10.5 ns — 6.0 11.5 1.0 13.0 Enable time tZH tZL — 4.5 9.0 1.0 10.5 — 6.0 11.5 1.0 13.0 tHZ tLZ — 4.0 10.0 1.0 11.5 — 5.5 13.5 1.0 15.0 Disable time CL = 15 pF TO (Output) A Y OE Y OE Y FROM TO CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF • VCC = 5.0 ± 0.5 V Ta = 25°C Test Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Conditions (Input) (Output) Propagation delay time tPLH tPHL — 3.4 5.5 1.0 6.5 ns A Y — 4.3 7.5 1.0 8.5 Enable time tZH tZL — 3.4 5.1 1.0 6.0 OE Y — 4.4 7.1 1.0 8.0 tHZ tLZ — 3.2 6.8 1.0 8.0 OE Y — 4.0 8.8 1.0 10.0 Disable time CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF ns CL = 15 pF CL = 50 pF Operating Characteristics • CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 5.0 11.5 — pF f = 10 MHz Rev.2.00, Oct.23.2003, page 5 of 8 — HD74LV2GT125A Test Circuit VCC Pulse Generator Z OUT = 50 Ω See Function Table Input VCC Output 1k Ω S1 CL = 15 or 50 pF TEST t PLH / t PHL t ZH/ t HZ t ZL / t LZ Note: 1. C L includes probe and jig capacitance. Rev.2.00, Oct.23.2003, page 6 of 8 OPEN See under table GND *1 S1 OPEN GND VCC HD74LV2GT125A • Waveforms – 1 tr tf VI 90 % Vref 90 % Vref Input A 10 % 10 % GND t PHL t PLH VOH Output Y 50% 50% VOL • Waveforms – 2 tf tr 90 % Vref Input OE VI 90 % Vref 10 % t ZL 10 % GND t LZ VCC 50% Waveform – A VOL + 0.3 V t ZH Waveform – B t HZ VOH – 0.3 V 50% VOL VOH GND INPUTS VCC (V) VI 3.3±0.3 2.5 V ≤ 3.0 ns 50% ≤ 3.0 ns 1.5 V 5.0±0.5 Notes: Vref tr / tf 3V 1. Input waveform : PRR ≤ 1 MHz, Zo = 50 Ω. 2. Waveform – A is for an output with internal conditions such that the output is low except when disabled by the output control. 3. Waveform – B is for an output with internal conditions such that the output is high except when disabled by the output control. Rev.2.00, Oct.23.2003, page 7 of 8 HD74LV2GT125A Package Dimensions 2.0 ± 0.2 1.5 ± 0.2 + 0.1 (0.17) 8 − 0.2 − 0.05 Package Code JEDEC JEITA Mass (reference value) Rev.2.00, Oct.23.2003, page 8 of 8 + 0.1 0.13 − 0.05 0 − 0.1 0.7 ± 0.1 (0.4) 2.3 ± 0.1 (0.5) (0.5) (0.5) 3.1 ± 0.3 (0.4) Unit: mm TTP–8DBV 0.010 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. 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