PYRAMID P4C1048L-70SC

P4C1048L
LOW POWER 512K x 8
CMOS STATIC RAM
FEATURES
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
—32-Pin TSOP II
VCC Current
— Operating: 35mA
— CMOS Standby: 100µA
Access Times
—45/55/70/100 ns
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
DESCRIPTION
The P4C1048L is a 4 Megabit low power CMOS static
RAM organized as 512K x 8. The CMOS memory requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 45 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
locations are specified on address pins A0 to A18. Reading is accomplished by device selection (CE low) and
output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either CE is HIGH or
WE is LOW.
The P4C1048L device provides asynchronous operation with matching access and cycle times. Memory
The P4C1048L is packaged in a 32-pin 445 mil plastic
SOP, 32-pin TSOP II, or 600 mil plastic or ceramic sidebrazed DIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P600, C10),
SOP (S12), TSOP II (T4)
TOP VIEW
Document # SRAM129 REV D
Revised July 2007
1
P4C1048L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Supply Voltage
Commercial (0°C to 70°C)
4.5V ≤ VCC ≤ 5.5V
Industrial (-40°C to 85°C)
4.5V ≤ VCC ≤ 5.5V
Military (-55°C to 125°C)
4.5V ≤ VCC ≤ 5.5V
MAXIMUM RATINGS(a)
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings
only. Functional operation of the device is not implied at these or any other conditions in excess of those given in
the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely
affect device reliability.
Symbol
Parameter
Min
Max
Unit
Supply Voltage with Respect to GND
-0.5
7.0
V
Terminal Voltage with Respect to GND (up to 7.0V)
-0.5
VCC + 0.5
V
TA
Operating Ambient Temperature
-55
125
°C
STG
Storage Temperature
-65
150
°C
IOUT
Output Current into Low Outputs
25
mA
ILAT
Latch-up Current
VCC
VTERM
>200
mA
CAPACITANCES(d)
(VCC = 5.0V, TA = 25°C, f = 1.0 MHz)
Symbol
Parameter
Test Conditions
Max
Unit
CIN
Input Capacitance
VIN = 0V
6
pF
COUT
Output Capacitance
VOUT = 0V
8
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter
Temperature Range
Commercial
ICC
Dynamic Operating Current Industrial
Military
*
-45
-55
-70
-100
20
20
20
20
25
25
25
25
35
35
35
35
Unit
mA
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e. CE and WE ≤ VIL (max), OE is high. Switching
inputs are 0V and 3V.
Notes:
a. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability.
b. Extended temperature operation guaranteed with 400 linear feet per minute of air flow.
c. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
d. This parameter is sampled and not 100% tested.
Document # SRAM129 REV D
Page 2 of 12
P4C1048L
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(b)
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
VHC
CMOS Input High Voltage
VLC
CMOS Input Low Voltage
VOL
Output Low Voltage
(TTL Load)
IOL = +2.1 mA, VCC = Min.
VOH
Output High Voltage
(TTL Load)
IOH = –1 mA, VCC = Min.
ILI
Input Leakage Current
0.8
–0.5(c)
VCC –0.2 VCC +0.5
–0.5(c)
VCC = Max.
VIN = GND to VCC
VCC = Max.,
ILO
Output Leakage Current
P4C1048L
Unit
Min
Max
VCC +0.5 V
2.2
Test Conditions
CE = VIH,
V
V
0.2
V
0.4
V
2.4
V
Mil.
–10
+10
Ind./Com’l.
–5
+5
Mil.
–10
+10
Ind./Com’l.
–5
+5
___
5
___
3
Mil.
___
100
Ind./Com’l.
___
30
µA
µA
VOUT = GND to VCC
ISB
ISB1
CE ≥ VIH
Standby Power Supply
Current (TTL Input Levels) VCC= Max,
f = Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE ≥ VHC
VCC= Max,
Mil.
Ind./Com’l.
mA
µA
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
N/A = Not Applicable
Document # SRAM129 REV D
Page 3 of 12
P4C1048L
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
Parameter
Min
-45
Max
45
Min
-55
Max
55
Min
-70
Max
Unit
100
ns
tRC
Read Cycle Time
tAA
Address Access Time
45
55
70
100
ns
tAC
Chip Enable Access
Time
45
55
70
100
ns
tOH
Output Hold from
Address Change
5
5
5
5
ns
tLZ
Chip Enable to
Output in Low Z
10
10
10
10
ns
tHZ
Chip Disable to
Output in High Z
18
20
25
35
ns
tOE
Output Enable Low
to Data Valid
22
25
35
45
ns
tOLZ
Output Enable Low to
Low Z
tOHZ
Output Enable High
to High Z
tPU
Chip Enable to Power
Up Time
tPD
Chip Disable to
Power Down Time
5
70
-100
Min
Max
5
5
20
18
0
0
45
25
0
55
ns
5
35
ns
0
70
ns
100
ns
OE CONTROLLED)(1)
READ CYCLE NO. 1 (OE
Document # SRAM129 REV D
Page 4 of 12
P4C1048L
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
CE CONTROLLED)
READ CYCLE NO. 3 (CE
Notes:
1. WE is HIGH for READ cycle.
2. CE and OE are LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE transition LOW.
Document # SRAM129 REV D
4. Transition is measured ± 200 mV from steady state voltage prior to change,
with loading as specified in Figure 1. This parameter is sampled and not
100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
Page 5 of 12
P4C1048L
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-45
Min Max
-55
Min
Max
-70
-100
Min Max
Symbol
Parameter
tWC
Write Cycle Time
45
55
70
100
ns
tCW
Chip Enable Time
to End of Write
35
40
60
75
ns
35
40
60
75
ns
0
0
0
0
ns
Min
Max
Unit
tAS
Address Valid to
End of Write
Address Set-up
Time
tWP
Write Pulse Width
35
40
50
60
ns
tAH
Address Hold
Time
0
0
0
0
ns
tDW
Data Valid to End
of Write
25
30
35
45
ns
tDH
Data Hold Time
0
0
0
0
ns
tWZ
Write Enable to
Output in High Z
tOW
Output Active from
End of Write
tAW
18
5
20
5
25
5
35
5
ns
ns
WE CONTROLLED)(6,7)
WRITE CYCLE NO. 1 (WE
Notes:
6. CE and WE are LOW for WRITE cycle.
7. OE is LOW for this WRITE cycle to show tWZ and tOW.
8. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
Document # SRAM129 REV D
Page 6 of 12
P4C1048L
CE CONTROLLED)(6)
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE
AC TEST CONDITIONS
TRUTH TABLE
CE OE WE
GND to 3.0V
Mode
Standby
Input Timing Reference Level
3ns
1.5V
DOUT Disabled
L
Output Timing Reference Level
1.5V
Read
L
See Fig. 1 and 2
Write
L
Input Pulse Levels
Input Rise and Fall Times
Output Load
Figure 1. Output Load
H
I/O
Power
X
High Z
H
H
High Z
L
X
H
DOUT
DIN
Standby
Active
Active
X
L
Active
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the high speed of the P4C1048L, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the VCC and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between VCC and ground.
Document # SRAM129 REV D
To avoid signal reflections, proper termination must be used; for example,
a 50Ω test environment should be terminated into a 50Ω load with 1.77V
(Thevenin Voltage) at the comparator input, and a 589Ω resistor must be
used in series with DOUT to match 639Ω (Thevenin Resistance).
Page 7 of 12
P4C1048L
DATA RETENTION
Symbol
VDR
Parameter
VCC for Data Retention
Test Conditions
Min
Max
Unit
CE ≥ VCC -0.2V,
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
2.0
5.5
V
VDR = 2.0V
ICCDR
Data Retention Current
VDR = 3.0V
tCDR
Chip Deselect to Data
Retention Time
tR
Operating Recovery Time
Comm/Ind
20
Military
200
Comm/Ind
30
Military
300
See Retention Waveform
µA
µA
0
ns
tRC
ns
1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 - 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V
LOW VCC DATA RETENTION WAVEFORM
Document # SRAM129 REV D
Page 8 of 12
P4C1048L
ORDERING INFORMATION
SELECTION GUIDE
The P4C1048L is available in the following temperature, speed and package options.
Speed (ns)
Temperature
Range
Commercial
Package
Plastic DIP (600 mil)
55
70
100
-45PC
-55PC
-100PC
-100CWC
-45CWC
-55CWC
-70PC
-70CWC
Plastic SOP (445 mil)
-45SC
-55SC
-70SC
-100SC
TSOP II
-45TC
-55TC
-70TC
-100TC
Plastic DIP (600 mil)
-45PI
-55PI
-100PI
-100CWI
Side Brazed DIP (600 mil)
Industrial
45
-45CWI
-55CWI
-70PI
-70CWI
Plastic SOP (445 mil)
-45SI
-55SI
-70SI
-100SI
TSOP II
-45TI
-55TI
-70TI
-100TI
Military
Side Brazed DIP (600 mil)
N/A
N/A
-70CWM
-100CWM
Military
Processed*
Side Brazed DIP (600 mil)
N/A
N/A
-70CWMB
-100CWMB
Side Brazed DIP (600 mil)
* Military temperature range with MIL-STD-883 Class B processing.
Document # SRAM129 REV D
Page 9 of 12
P4C1048L
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
Pkg #
# Pins
Symbol
A
A1
A2
B
C
D
e
E
H
L
L1
α
C10
SIDEBRAZED DUAL IN-LINE PACKAGE
32 (600 mil)
Min
Max
0.225
0.014
0.026
0.045
0.065
0.008
0.018
1.680
0.510
0.620
0.600 BSC
0.100 BSC
0.125
0.200
0.015
0.070
0.005
0.005
-
S12
SOIC/SOP SMALL OUTLINE IC PACKAGES
32 (445 Mil)
Min
Max
0.118
0.004
0.101
0.111
0.014
0.020
0.006
0.012
0.793
0.817
0.050 BSC
0.440
0.450
0.546
0.566
0.023
0.039
0.047
0.063
0°
4°
Document # SRAM129 REV D
Page 10 of 12
P4C1048L
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
Pkg #
# Pins
Symbol
A
A2
b
D
E
e
HD
P600
PLASTIC DUAL IN-LINE PACKAGE
32 (600 mil)
Min
Max
0.160
0.200
0.015
0.014
0.023
0.045
0.070
0.006
0.014
1.600
1.700
0.526
0.548
0.590
0.610
0.100 BSC
0.600 BSC
0.120
0.150
0°
15°
T4
TSOP II PACKAGE
32
Min
Max
0.037
0.041
0.047
0.012
0.020
0.395
0.405
0.820
0.831
0.050 BSC
0.455
0.471
Document # SRAM129 REV D
Page 11 of 12
P4C1048L
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM129
P4C1048L LOW POWER 512K x 8 CMOS STATIC RAM
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
Oct-05
JDB
New Data Sheet
A
Nov-06
JDB
Minor corrections to DC Electrical Characteristics and Data Retention
tables
B
Dec-06
JDB
Update SOIC/SOP package drawing.
C
May-07
JDB
Added 45/55 ns and PDIP
D
Jul-07
JDB
Corrected error in selection guide; added TSOP II package
Document # SRAM129 REV D
DESCRIPTION OF CHANGE
Page 12 of 12