P3C1024L ULTRA Low Power 128K x 8 CMOS Static RAM VCC Current (Commercial/Industrial) — Operating: 10mA/12mA — CMOS Standby: 10µA/10µA Three-State Outputs Access Times —55/70 (Commercial or Industrial) Advanced CMOS Technology Single 3.3 Volts ± 0.3V Power Supply Packages —32-Pin 445 mil SOP —32-Pin TSOP Easy Memory Expansion Using CE1, CE2 and OE Inputs Fully TTL Compatible Inputs and Outputs Automatic Power Down Common Data I/O DESCRIPTION The P3C1024L is a 1,048,576-bit low power CMOS static RAM organized as 128Kx8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 3.3V ± 0.3V tolerance power supply. Access times of 55 ns and 70 ns are availale. CMOS is utilized to reduce power consumption to a low level. locations are specified on address pins A0 to A16. Reading is accomplished by device selection (CE1 low and CE2 high) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE1 or OE is HIGH or WE or CE2 is LOW. The P3C1024L device provides asynchronous operation with matching access and cycle times. Memory The P3C1024L is packaged in a 32-pin TSOP and 445 mil SOP. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION SOP (S12) TOP VIEW See end of datasheet for TSOP pin configuration. Document # SRAM132 REV A Revised February 2009 P3C1024L - ULTRA LOW POWER 128K X 8 CMOS STATIC RAM RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Supply Voltage Commercial (0°C to 70°C) 3.0V ≤ VCC ≤ 3.6V Industrial (-40°C to 85°C) MAXIMUM RATINGS(1) Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Sym Parameter Min Max Unit Supply Voltage with Respect to GND -0.3 3.9 V Terminal Voltage with Respect to GND -0.3 VCC + 0.3 V TA Operating Ambient Temperature -55 125 °C STG Storage Temperature -65 150 °C IOUT Output Current into Low Outputs 20 mA ILAT Latch-up Current VCC VTERM > 200 mA DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter Test Conditions Min VOH Output High Voltage (I/O0 - I/O7) IOH = –1mA, VCC = 3.0V 2.4 VOL Output Low Voltage (I/O0 - I/O7) IOL = 2.1mA, VCC = 3.0V VIH Input High Voltage VIL Input Low Voltage ILI Input Leakage Current GND ≤ VIN ≤ VCC ILO Output Leakage Current GND ≤ VOUT ≤ VCC, CE1 ≥ VIH or CE2 ≤ VIL ISB VCC Current TTL Standby Current (TTL Input Levels) ISB1 VCC Current CMOS Standby Current (CMOS Input Levels) Document # SRAM132 REV A VCC = 3.6V, IOUT = 0 mA CE1 = VIH or CE2 = VIL VCC = 3.6V, IOUT = 0 mA CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V Max Unit V 0.4 V 2.2 VCC + 0.3 V -0.3 0.8 V IND -2 +2 COM -1 +1 IND -2 +2 COM -1 +1 µA µA 3 mA 10 µA Page 2 P3C1024L - ULTRA LOW POWER 128K X 8 CMOS STATIC RAM CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0 MHz) Symbol CIN COUT Parameter Test Conditions Max Unit VIN=0V 8 pF VOUT=0V 9 pF Input Capacitance Output Capacitance POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol ICC Parameter Dynamic Operating Current Temperature Range -55 -70 Unit Commercial 10 8 mA Industrial 12 10 mA *Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e., CE2 ≥ VIH (min), CE1 and WE ≤ VIL (max), OE is high. Switching inputs are 0V and 3V. AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) -55 -70 Symbol Parameter tRC Read Cycle Time tAA Address Access Time 55 70 ns tAC Chip Enable Access Time 55 70 ns tOH Output Hold from Address Change 10 10 ns tLZ Chip Enable to Output in Low Z 10 10 ns tHZ Chip Disable to Output in High Z 20 25 ns tOE Output Enable Low to Data Valid 25 35 ns tOLZ Output Enable Low to Low Z tOHZ Output Enable High to High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down Time Document # SRAM132 REV A Min Max 55 Min Max 70 5 ns 5 20 0 ns 25 0 55 Unit ns ns 70 ns Page 3 P3C1024L - ULTRA LOW POWER 128K X 8 CMOS STATIC RAM READ CYCLE NO. 1 (OE CONTROLLED)(1) READ CYCLE NO. 2 (ADDRESS CONTROLLED) READ CYCLE NO. 3 (CE CONTROLLED) Notes: 1.WE is HIGH for READ cycle. 2.CE1 and OE is LOW, and CE2 is HIGH for READ cycle. 3.ADDRESS must be valid prior to, or coincident with later of CE1 transition LOW or CE2 transition HIGH. Document # SRAM132 REV A 4.Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 5.READ Cycle Time is measured from the last valid address to the first transitioning address. Page 4 P3C1024L - ULTRA LOW POWER 128K X 8 CMOS STATIC RAM AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter -55 Min -70 Max Min Max Unit tWC Write Cycle Time 55 70 ns tCW Chip Enable Time to End of Write 40 60 ns tAW Address Valid to End of Write 40 60 ns tAS Address Set-up Time 0 0 ns tWP Write Pulse Width 40 50 ns tAH Address Hold Time 0 0 ns tDW Data Valid to End of Write 25 30 ns tDH Data Hold Time 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 20 10 25 10 ns ns WRITE CYCLE NO. 1 (WE CONTROLLED)(6) Notes: 6. CE1 and WE are LOW and CE2 is HIGH for WRITE cycle. 7. OE is LOW for this WRITE cycle to show twz and tow. 8. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high impedance state. 9. Write Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM132 REV A Page 5 P3C1024L - ULTRA LOW POWER 128K X 8 CMOS STATIC RAM TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6) AC TEST CONDITIONS TRUTH TABLE Input Pulse Levels GND to 3.0V Mode Input Rise and Fall Times 3ns Standby H X X X High Z Standby Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Standby X L X X High Z Standby Output Load See Fig. 1 and 2 DOUT Disabled L H H H High Z Active Read L H L H DOUT Active Write L H X L DIN Active Figure 1. Output Load CE1 CE2 OE WE I/O Power Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the high speed of the P3C1024L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor is also required between VCC and ground. Document # SRAM132 REV A To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.75V (Thevenin Voltage) at the comparator input, and a 595Ω resistor must be used in series with DOUT to match 645Ω (Thevenin Resistance). Page 6 P3C1024L - ULTRA LOW POWER 128K X 8 CMOS STATIC RAM DATA RETENTION Symbol Parameter Test Conditions Min 2.0 VDR VCC for Data Retention CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V, VIN ≥ VCC -0.2V or VIN ≤ 0.2V ICCDR (1) Data Retention Current VDR = 2.0V Chip Deselect to Data Retention Time See Retention Waveform tCDR tR Operating Recovery Time(2) Max Unit V 10 µA 0 ns 100 µA 1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V LOW VCC DATA RETENTION WAVEFORM 1 (CE1 CONTROLLED) LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED) Document # SRAM132 REV A Page 7 P3C1024L - ULTRA LOW POWER 128K X 8 CMOS STATIC RAM ORDERING INFORMATION SELECTION GUIDE The P3C1024L is available in the following temperature, speed and package options. Temperature Range Commercial Industrial Package Speed -55 -70 Plastic SOP (445 mil) -55SC -70SC TSOP -55TC -70TC Plastic SOP (445 mil) -55SI -70SI TSOP -55TI -70TI TSOP PIN CONFIGURATION Document # SRAM132 REV A Page 8 P3C1024L - ULTRA LOW POWER 128K X 8 CMOS STATIC RAM # Pins SOIC/SOP SMALL OUTLINE IC PACKAGE S12 Pkg # 32 (445 Mil) Symbol Min Max A - 0.118 A1 0.004 - A2 0.101 0.111 b 0.014 0.020 C 0.006 0.012 D 0.793 0.817 e 0.050 BSC E 0.440 0.450 H 0.546 0.566 L 0.023 0.039 L1 0.047 0.063 α 0° 4° Pkg # T3 # Pins 32 TSOP THIN SMALL OUTLINE PACKAGE (8 x 20 mm) Symbol Min Max A - 0.048 A2 0.037 0.042 b 0.006 0.011 D 0.720 0.729 E 0.307 0.323 e 0.50 mm BSC HD 0.779 0.796 Document # SRAM132 REV A Page 9 P3C1024L - ULTRA LOW POWER 128K X 8 CMOS STATIC RAM REVISIONS DOCUMENT NUMBER SRAM 132 DOCUMENT TITLE P3C1024L ULTRA LOW POWER 128K x 8 CMOS STATIC RAM REV ISSUE DATE ORIGINATOR OR April 2006 JDB New Data Sheet A Feb 2009 JDB Updated SOIC/SOP package drawing, new datasheet format Document # SRAM132 REV A DESCRIPTION OF CHANGE Page 10