P4C107 ULTRA HIGH SPEED 1M x 1 STATIC CMOS RAM FEATURES Full CMOS High Speed (Equal Access and Cycle Times) – 10/12/15 ns (Commercial) – 12/15/20 ns (Industrial) Single 5V±10% Power Supply Separate Data I/O Three-State Output Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 28-Pin 400 mil SOJ DESCRIPTION The P4C107 is a 1Mx1-bit ultra high-speed static RAM. The CMOS memories require no clocks or refreshing and have equal access and cycle times. The RAM operates from a single 5V ± 10% tolerance power supply. Data integrity is maintained for supply voltages down to 2.0V, typically drawing 50µA. Functional Block Diagram Access times as fast as 10 nanoseconds are available, greatly enhancing system speeds. The P4C107 is available in a 28-pin 400 mil SOJ. Pin Configuration SOJ (J7) Document # SRAM139 REV OR Revised April 2010 P4C107 - ULTRA HIGH SPEED 1M X 1 STATIC CMOS RAM Maximum Ratings(1) Sym Parameter RECOMMENDED OPERATING CONDITIONS Value Unit V Grade(2) VCC Power Supply Pin with Respect to GND -0.5 to +6 VTERM Terminal Voltage with Respect to GND (up to 6.0V) -0.5 to VCC + 0.5 V TA Operating Temperature -55 to +125 °C TBIAS Temperature Under Bias -55 to +125 °C TSTG Storage Temperature -65 to +150 °C Sym Parameter Commercial Industrial Ambient Temp GND VCC 0°C to +70°C 0V 5.0V ± 10% -40°C to +85°C 0V 5.0V ± 10% CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) PT Power Dissipation 1.0 W CIN Input Capacitance IOUT DC Output Current 50 mA COUT Output Capacitance Conditions Typ Unit VIN=0V 7 pF VOUT=0V 10 pF DC ELECTRICAL CHARACTERISTICS (Over Recommended Operating Temperature & Supply Voltage)(2) Sym Parameter Test Conditions Min Max Unit VIH Input High Voltage 2.2 VCC + 0.5 V VIL Input Low Voltage -0.5(3) 0.8 V VOL Output Low Voltage (TTL Load) IOL = +8 mA, VCC = Min 0.4 V VOH Output High Voltage (TTL Load) IOH = -4 mA, VCC = Min 2.4 ILI Input Leakage Current VCC = Max, VIN = GND to VCC -5 +5 µA ILO Output Leakage Current VCC = Max, CE = VIH, VOUT = GND to VCC -5 +5 µA ICC Operating Supply Current VCC = Max, IOUT=0 mA, f=Max 150 mA ISB Standby Power Supply Current (TTL Input Levels) CE ≥ VIH, VCC = Max, f = Max, Outputs Open 50 mA ISB1 Standby Power Supply Current (CMOS Input Levels) CE ≥ VHC, VCC = Max, f = 0, Outputs Open VIN ≤ VLC or VIN ≥ VHC 3 mA V N/A = Not applicable Document # SRAM139 REV OR Page 2 P4C107 - ULTRA HIGH SPEED 1M X 1 STATIC CMOS RAM AC ELECTRICAL CHARACTERISTICS—READ CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym Parameter -10 Min -12 Max 10 Min -15 Max 12 Min -20 Max Max Read Cycle Time tAA Address Access Time 10 12 15 20 ns tAC Chip Enable Access Time 10 12 15 20 ns tOH Output Hold from Address Change 3 3 3 3 ns tLZ Chip Enable to Output in Low Z 3 3 3 3 ns tHZ Chip Disable to Output in High Z tPU Chip Enable to Power Up Time tPD Chip Disable to Power Down 0 6 0 10 20 Unit tRC 5 15 Min 7 0 12 ns 8 0 15 ns ns 20 ns TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)(5,6) TIMING WAVEFORM OF READ CYCLE NO. 2 (CE CONTROLLED)(5,7,8) Document # SRAM139 REV OR Page 3 P4C107 - ULTRA HIGH SPEED 1M X 1 STATIC CMOS RAM AC CHARACTERISTICS—WRITE CYCLE (VCC = 5V ± 10%, All Temperature Ranges)(2) Sym Parameter -10 Min -12 Max Min -15 Max Min -20 Max Min Max Unit tWC Write Cycle Time 10 12 15 20 ns tCW Chip Enable Time to End of Write 7 10 12 15 ns tAW Address Valid to End of Write 7 10 12 15 ns tAS Address Setup Time 0 0 0 0 ns tWP Write Pulse Width 7 10 12 15 ns tAH Address Hold Time 0 0 0 0 ns tDW Data Valid to End of Write 6 7 8 10 ns tDH Data Hold Time 0 0 0 0 ns tWZ Write Enable to Output in High Z tOW Output Active from End of Write 6 0 7 0 8 0 9 0 ns ns TIMING WAVEFORM OF WRITE Cycle No. 1 (WE Controlled)(10,11) Notes: 1.Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Maximum rating conditions for extended periods may affect reliability. 2.Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3.Transient inputs with VIL and IIL not more negative than –3.0V and –100mA, respectively, are permissible for pulse widths up to 20 ns. Document # SRAM139 REV OR 4.This parameter is sampled and not 100% tested. 5.WE is HIGH for READ cycle. 6.CE is LOW and OE is LOW for READ cycle. 7.ADDRESS must be valid prior to, or coincident with CE transition LOW. 8.Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 9.Read Cycle Time is measured from the last valid address to the first transitioning address. Page 4 P4C107 - ULTRA HIGH SPEED 1M X 1 STATIC CMOS RAM Timing Waveform of Write Cycle No. 2 (CE Controlled)(10) AC TEST CONDITIONS Input Pulse Levels TRUTH TABLE GND to 3.0V Mode CE WE I/O Power Input Rise and Fall Times 3ns Standby H X High Z Standby Input Timing Reference Level 1.5V Read L H DOUT Active Output Timing Reference Level 1.5V Write L L High Z Active Output Load See Figures 1 and 2 Figure 1. Output Load Figure 2. Thevenin Equivalent * including scope and test fixture. Note: Because of the ultra-high speed of the P4C107, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 µF high frequency capacitor Notes: 10. CE and WE must be LOW for WRITE cycle. 11. OE is LOW for this WRITE cycle to show tWZ and tOW. 12. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state Document # SRAM139 REV OR is also required between VCC and ground. To avoid signal reflections, proper termination must be used; for example, a 50Ω test environment should be terminated into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with DOUT to match 166Ω (Thevenin Resistance). 13. Write Cycle Time is measured from the last valid address to the first transitioning address. Page 5 P4C107 - ULTRA HIGH SPEED 1M X 1 STATIC CMOS RAM ORDERING INFORMATION Document # SRAM139 REV OR Page 6 P4C107 - ULTRA HIGH SPEED 1M X 1 STATIC CMOS RAM SOJ SMALL OUTLINE IC PACKAGE J7 Pkg # # Pins 28 (400 mil) Symbol Min Max A 0.128 0.148 A1 0.082 - b 0.013 0.019 C 0.007 0.013 D 0.720 0.730 e 0.050 BSC E 0.395 0.405 E1 0.435 0.445 E2 0.360 0.380 Q 0.025 - Document # SRAM139 REV OR Page 7 P4C107 - ULTRA HIGH SPEED 1M X 1 STATIC CMOS RAM REVISIONS DOCUMENT NUMBER SRAM139 DOCUMENT TITLE P4C107 - ULTRA HIGH SPEED 1M X 1 STATIC CMOS RAM REV ISSUE DATE ORIGINATOR OR Apr-2010 JDB Document # SRAM139 REV OR DESCRIPTION OF CHANGE New Data Sheet Page 8