P93U422 HIGH SPEED 256 x 4 STATIC CMOS RAM FEATURES CMOS for Low Power – 440 mW (Commercial) – 495 mW (Military) Universal 256 x 4 Static RAM One part, the P93U422, replaces the following bipolar and CMOS parts: – 93422, 93422A – 93L422, 93L422A 5V Power Supply ±10% for both commercial and military temperature ranges Separate I/O Fast Access Time – 35 ns Commercial and Military Fully static operation with equal access and cycle times Available in the following packages: – PDIP, CERDIP, Side Brazed DIP – CERPACK – LCC – SOIC Resistant to single event upset and latchup due to advanced process and design improvements DESCRIPTION active HIGH chip select two (CS 2) as well as 3-state outputs. The P93U422 is a 1,024-bit high-speed Static RAM with a 256 x 4 organization. The P93U422 is a universal device designed to replace the entire 93 and 93L 256 x 4 static RAM families. The memory requires no clocks or refreshing and has equal access and cycle times. Inputs and outputs are fully TTL compatible. Operation is from a single 5 Volt supply. Easy memory expansion is provided by an active LOW chip select one (CS 1) and FUNCTIONAL BLOCK DIAGRAM In addition to high performance, the device features latchup protection, single event and upset protection. The P93U422 is offered in several packages: 22-pin 400 mil DIP (plastic and ceramic), 24-pin 300 mil SOIC, 24-pin square LCC and 24-pin CERPACK. Devices are offered in both commercial and military temperature ranges. PIN CONFIGURATIONS SOIC (S4) CERPACK (F3) DIP (P3-1, C3-1, D3-1) LCC (L4) Document # SRAM102 REV A 1 Revised October 2005 P93U422 MAXIMUM RATINGS(1) Symbol Parameter Value Unit VCC Power Supply Pin with Respect to GND – 0.5 to +7 V VTERM Terminal Voltage with Respect to GND (up to 7.0V) – 0.5 to VCC +0.5 V TA Operating Temperature – 55 to +125 °C Symbol RECOMMENDED OPERATING CONDITIONS Parameter Value Unit TBIAS Temperature Under Bias – 55 to +125 °C TSTG Storage Temperature – 65 to +150 °C I OUT DC Output Current 20 mA CAPACITANCES(4) (VCC = 5.0V, TA = 25°C, f = 1.0MHz) Grade(2) Commercial Military Ambient Temp Gnd Vcc Symbol Parameter Conditions Typ. Unit 0°C to 70°C 0V 5.0V ±10% CIN Input Capacitance VIN = 0V 5 pF –55°C to 125°C 0V 5.0V ±10% COUT Output Capacitance VOUT = 0V 7 pF DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage(2) Symbol Parameter Test Conditions VOH Output High Voltage VCC = Min., VIN = VIH or VIL, IOH = –5.2 mA VOL Output Low Voltage VCC = Min., VIN = VIH or VIL, IOL = 8.0 mA VIH Input High Level VIL Input Low Level IIL Input Low Current VIN = 0.40 V IIH Input High Current ISC Output Short Circuit Current (3) ICC Power Supply Current VCL Input Clamp Voltage ICEX Output Leakage Current Min. Max. Unit V 2.4 0.45 2.1 V V 0.8 V –300 µA VCC = Max, VIN = 4.5V 40 µA VCC = Max., VOUT = 0.0V –70 mA All Inputs = GND VCC = Max. TA = 125°C TA = 75°C 70 TA = 0°C 80 TA = –55°C 90 70 IIN = –10mA VOUT = 2.4V, VCC = Max. VOUT = 0.5V, VCC = Max. Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability Document # SRAM102 REV A P93U422 –1.5 50 –50 mA V µA 2. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds. 4. This parameter is sampled and not 100% tested. Page 2 of 10 P93U422 FUNCTIONAL DESCRIPTION An active LOW write enable (WE) controls the writing/ reading operation of the memory. When chip select one (CS 1) and write enable (WE) are LOW and chip select two (CS 2) is HIGH, the information on data inputs (D0 through D3) is written into the addressed memory word and preconditions the output circuitry so that true data is present at the outputs when the write cycle is complete. This preconditioning operation insures minimum write recovery times by eliminating the “write recovery glitch.” Reading is performed with chip selct one (CS 1) LOW, chip select two (CS 2) HIGH, write enable (WE) HIGH and output enable (OE) LOW. The information stored in the addressed word is read out on the noninverting outputs (O0 through O3). The outputs of the memory go to an inactive high impedance state whenever chip select one (CS 1) is HIGH, or during the write operation when write enable (WE) is LOW. TRUTH TABLE CS2 CS 1 WE OE Output Standby L X X X High Z Standby X H X X High Z DOUT Disabled H L X H High Z Read H L H L DOUT Write H L L X High Z Mode Notes: H = HIGH L = Low X = Don't Care HIGH Z = Implies outputs are disabled or off. This condition is defined as high impedance state for the P93U422. SWITCHING CHARACTERISTICS (5,6) Over Operating Range (Commercial and Military) Description Parameters P93U422 Min. Max. Unit tPLH(A)(7) tPLH(A)(7) Delay from Address to Output (Address Access Time) (See Fig. 2) 35 ns tPZH (CS1, CS2)(8) tPZL (CS1, CS2)(8) Delay from Chip Select to Active Output and Correct Data (See Fig. 2) 25 ns tPZH (WE)(8) tPZL (WE)(8) Delay from Write Enable to Active Output and Correct Data (Write Recovery) (See Fig. 1) 25 ns tPZH (OE)(8) tPZL (OE)(8) Delay from Output Enable to Active Output and Correct Data (See Fig. 2) 25 ns tS(A) th(A) tS(DI) th(DI) Setup Time Address (Prior to Initiation of Write) (See Fig. 1) Hold Time Address (After Termination of Write) (See Fig. 1) 5 5 ns 5 ns ns tS (CS1, CS2) Setup Time Data Input (Prior to Initiation of Write) (See Fig. 1) Hold Time Data Input (After Termination of Write) (See Fig. 1) Setup Time Chip Select (Prior to Initiation of Write) (See Fig. 1) th (CS1, CS2) Hold Time Chip Select (After Termination of Write) (See Fig. 1) 5 ns Minimum Write Enable Pulse Width (to Insure Write) (See Fig. 1) 20 ns tpw(WE) ns 5 5 ns tPHZ (CS1, CS2) tPLZ (CS1, CS2)(8) Delay from Chip Select to Inactive Output (HIGH Z) (See Fig. 2) 30 ns tPHZ (WE)(8) tPLZ (WE)(8) Delay from Write Enable to Inactive Output (HIGH Z) (See Fig. 1) 30 ns tPHZ (OE)(8) tPLZ (OE)(8) Delay from Output Enable to Inactive Output (HIGH Z) (See Fig. 2) 30 ns (8) Document # SRAM102 REV A Page 3 of 10 P93U422 Notes: 5) Test conditions assume signal transition times of 10 ns or less. 6) Extended temperature operation guaranteed with 400 linear feet per minute of air flow. 7) tPLH(A) and tPHL(A) are tested with S1 closed and CL = 15 pF with both input and output timing referenced to 1.5V 8) tPZH(WE), tPZH(CS1, CS2) and tPZH(OE) are measured with S1 open, CL = 15 pF and with both the input and output timing referenced to 1.5V. tPZL(WE), tPZL(CS1, CS2) and tPZL(OE) are measured with S1 closed, CL = 15pF and with both the input and output timing referenced to 1.5V. tPHZ(WE), tPHZ(CS1, CS2) and tPHZ(OE) are measured with S1 open, CL < 5pF and are measured between the 1.5V level input to the VOH -500mV level on the output. on the tPLZ(WE), tPLZ(CS1, CS2) and tPLZ(OE) are measured with S1 closed, CL < 5pF and are measured between the 1.5V level input to the VOL +500mV level on the output. on the SWITCHING TEST Test Circuits (7, 8) Document # SRAM102 REV A Page 4 of 10 P93U422 KEY TO DIAGRAM SWITCHING WAVEFORMS Write Mode (with OE = LOW) Figure 1. Read Mode Figure 2. Document # SRAM102 REV A Page 5 of 10 P93U422 ORDERING INFORMATION SELECTION GUIDE The P93U422 is available in the following temperature range, speed, and package options. Temperature Range Commercial Temperature Military Temperature Package 35 Plastic DIP -35PC Plastic SOIC -35SC Side Brazed DIP -35CM CERDIP -35DM CERPACK -35FM LCC -35LM Side Brazed DIP Military Processed* Speed (ns) -35CMB CERDIP -35DMB CERPACK -35FMB LCC -35LMB *Military temperature range with MIL-STD-883, Class B processing. Document # SRAM102 REV A Page 6 of 10 P93U422 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2 Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 α C3-1 SIDE BRAZED DUAL IN-LINE PACKAGE 22 (400 Mil) Min Max 0.200 0.014 0.026 0.035 0.060 0.008 0.015 1.100 0.360 0.410 0.400 BSC 0.100 BSC 0.125 0.200 0.015 0.060 0.005 0.005 - D3-1 CERDIP DUAL IN-LINE PACKAGE 22 (400 Mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.111 0.350 0.410 0.400 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0° 15° Document # SRAM102 REV A Page 7 of 10 P93U422 Pkg # # Pins Symbol A b c D E e k L Q S S1 Pkg # # Pins Symbol A A1 B1 D/E D1/E1 D2/E2 D3/E3 e h j L L1 L2 ND NE F3 CERPACK CERAMIC FLAT PACKAGE 24 Min Max 0.060 0.090 0.015 0.022 0.004 0.009 0.630 0.330 0.380 0.050 BSC 0.008 0.015 0.250 0.370 0.026 0.045 0.085 0.005 - L4 SQUARE LEADLESS CHIP CARRIER 24 Min Max 0.060 0.075 0.050 0.065 0.022 0.028 0.395 0.410 0.250 BSC 0.125 BSC 0.410 0.050 BSC 0.040 REF 0.020 REF 0.045 0.055 0.045 0.055 0.075 0.095 6 6 Document # SRAM102 REV A Page 8 of 10 P93U422 Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L α Pkg # # Pins Symbol A A1 b2 C D e E H h L α P3-1 PLASTIC DUAL IN-LINE PACKAGE 22 (400 Mil) Min Max 0.210 0.015 0.014 0.022 0.045 0.065 0.009 0.015 1.065 1.120 0.330 0.390 0.390 0.425 0.100 BSC 0.500 0.115 0.160 0° 15° S4 SMALL OUTLINE IC PLASTIC PACKAGE 24 (300 Mil) Min Max 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.012 0.598 0.614 0.050 BSC 0.291 0.299 0.394 0.419 0.010 0.029 0.016 0.050 0° 8° Document # SRAM102 REV A Page 9 of 10 P93U422 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM102 P93U422 HIGH SPEED 256 x 4 STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE ORIG 1997 DAB New Data Sheet A Oct-05 JDB Change logo to Pyramid Document # SRAM102 REV A DESCRIPTION OF CHANGE Page 10 of 10