PYRAMID P4C422-10SC

P4C422
HIGH SPEED 256 x 4
STATIC CMOS RAM
FEATURES
Separate I/O
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35 ns (Commercial)
– 15/20/25/35 ns (Military)
Fully TTL Compatible Inputs and Outputs
Resistant to single event upset and latchup
resulting from advanced process and design
improvements
CMOS for Low Power
– 495 mW Max. – 10/12/15/20/25 (Commercial)
– 495 mW Max. – 15/20/25/35 (Military)
Standard 22-pin 400 mil DIP, 24-pin 300 mil
SOIC, 24-pin square LCC package and 24-pin
CERPACK package
Single 5V±10% Power Supply
DESCRIPTION
The P4C422 is a 1,024-bit high-speed (10ns) Static
RAM with a 256 x 4 organization. The memory requires
no clocks or refreshing and has equal access and cycle
times. Inputs and outputs are fully TTL compatible.
Operation is from a single 5 Volt supply. Easy memory
expansion is provided by an active LOW chip select one
(CS 1) and active HIGH chip select two (CS 2) as well as
3-state outputs.
FUNCTIONAL BLOCK DIAGRAM
In addition to high performance and high density, the
device features latch-up protection, single event and
upset protection. The P4C422 is offered in several
packages: 22-pin 400 mil DIP (plastic and ceramic), 24pin 300 mil SOIC, 24-pin square LCC and 24-pin
CERPACK. Devices are offered in both commercial and
military temperature ranges.
PIN CONFIGURATIONS
SOIC (S4)
CERPACK (F3) SIMILAR
DIP (P3-1, C3-1, D3-1)
LCC (L4)
Document # SRAM101 REV. A
1
Revised October 2005
P4C422
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
VCC
Power Supply Pin with
Respect to GND
– 0.5 to +7
V
VTERM
Terminal Voltage with
Respect to GND
(up to 7.0V)
– 0.5 to
VCC +0.5
V
TA
Operating Temperature
– 55 to +125
°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
TBIAS
Temperature Under
Bias
– 55 to +125
°C
TSTG
Storage Temperature
– 65 to +150
°C
I OUT
DC Output Current
20
mA
CAPACITANCES(4)
(VCC = 5.0V, TA = 25°C, f = 1.0MHz)
Vcc
Parameter
Conditions Typ. Unit
Ambient Temp
Commercial
0°C to 70°C
0V
5.0V ±10%
CIN
Input Capacitance
VIN = 0V
5
pF
–55°C to 125°C
0V
5.0V ±10%
COUT
Output Capacitance VOUT = 0V
7
pF
Military
Gnd
Symbol
Grade (2)
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
Symbol
P4C422
Parameter
Test Conditions
VOH
Output High Voltage
IOH = –5.2 mA, VCC = Min.2.4
VOL
Output Low Voltage
IOL = +8 mA, VCC = Min.
VIH
Input High Voltage
VIL
Input Low Voltage
VCL
Input Clamp Diode Voltage
IIN = –10 mA
–1.5
I IX
Input Load Current
GND ≤ VIN ≤ VCC
–10
10
µA
I OZ
Output Current (High Z)
VOL ≤ VOUT ≤ VOH , Output Disabled
–10
10
µA
I OS
Output Short Circuit
Current(3)
VCC= Max., VOUT = GND
90
mA
Min
Max
Unit
V
0.4
2.1
V
V
0.8
V
V
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
ICC
Dynamic Operating Current
Temperature
Range
-10
-12
-15
-20
-25
-35
Commercial
Military
90
N/A
90
N/A
90
90
90
90
65
90
65
90
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4. This parameter is sampled and not 100% tested.
Document # SRAM101 REV. A
Unit
mA
mA
5. Transition time is ≤ 3ns for 10, 12, and 15 ns products and ≤ 5ns for
20, 25, and 35 ns products, see Fig 1d. Timing is referenced at input
and output levels of 1.5V. The output loading is equivalent to the
specified IOL/IOH with a load capacitance of 15 pF (10, 12) or 30 pF (15,
20, 25, 35) as in Fig. 1a and 1b respectively.
6. Transition time is ≤ 3ns for 10, 12, and 15 ns products and ≤ 5ns for
20, 25, and 35 ns products, see Fig 1d. Transition is measured at
steady state HIGH level -500mV or steady state LOW level +500mV
on the output from a level on the input with load shown in Fig. 1c.
7. tW is measured at tWSA = min.; tWSA is measured at tW = min.
Page 2 of 10
P4C422
FUNCTIONAL DESCRIPTION
An active LOW write enable (WE) controls the writing/
reading operation of the memory. When the chip select
one (CS 1) and the write enable (WE) are LOW and the chip
select two (CS 2) is HIGH, the information on data inputs
(D0 through D3) is written into the addressed memory word
and preconditions the output circuitry so that true data is
present at the outputs when the write cycle is complete.
This preconditioning operation insures minimum write
recovery times by eliminating the “write recovery glitch.”
Reading is performed with chip selct one (CS 1) LOW, chip
select two (CS 2) HIGH, write enable (WE) HIGH and
output enable (OE) LOW. The information stored in the
addressed word is read out on the noninverting outputs
(O0 through O3). The outputs of the memory go to an
inactive high impedance state whenever chip select one
(CS 1) is HIGH, or during the write operation when write
enable (WE) is LOW.
TRUTH TABLE
CS2
CS1
WE
OE
Output
Notes:
Standby
L
X
X
X
High Z
Standby
X
H
X
X
High Z
DOUT Disabled
H
L
X
H
High Z
H
L
X
HIGH Z
Read
H
L
H
L
DOUT
Write
H
L
L
X
High Z
Mode
= HIGH
= Low
= Don't Care
= Implies outputs are disabled or off. This condition
is defined as high impedance state for the
P4C422.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10% except as noted, All Temperature Ranges)(2)
Parameter
Sym.
tRC
Read Cycle Time (5)
tACS
Chip Select Time (5)
tZRCS
Chip Select to High-Z (6)
tAOS
Output Enable Time
tZROS
Output Enable to High-Z
tAA
Address Access Time (5)
-10*
-20
-15
-25
-35
Min Max Min Max Min Max Min Max Min Max Min Max
12
(6)
-12
12
20
15
25
35
Unit
ns
7.5
8
8
12
15
25
ns
8
10
12
15
20
30
ns
7.5
8
8
12
15
25
ns
8
10
12
15
20
30
ns
10
12
15
20
25
35
ns
*VCC = 5V ± 5%
TIMING WAVEFORM OF READ CYCLE
Document # SRAM101 REV. A
Page 3 of 10
P4C422
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10% except as noted, All Temperature Ranges)(2)
-10*
Parameter
Sym.
-15
-12
-20
-25
-35
Min Max Min Max Min Max Min Max Min Max Min Max
tWC
Write Cycle Time (5)
tZWS
Write Enable to High-Z
tWR
Write Recovery Time
tW
Write Pulse Width
tWSD
10
(6)
15
12
35
25
20
Unit
ns
8
10
12
15
20
30
ns
8
10
12
15
20
25
ns
8
9
11
13
15
20
ns
Data Setup Time Prior to Write (5)
0
0
0
2
5
5
ns
tWHD
Data Hold Time (5)
2
2
2
5
5
5
ns
tWSA
Address Setup Time
0
0
0
2
5
5
ns
tWHA
Address Hold Time (5)
2
2
4
5
5
5
ns
tWSCS
Chip Select Setup Time
0
0
0
2
5
5
ns
tWHCS
Chip Select Hold Time (5)
2
2
2
5
5
5
ns
(5,7)
(5,7)
(5)
*VCC = 5V ± 5%
TIMING WAVEFORM OF WRITE CYCLE
Document # SRAM101 REV. A
Page 4 of 10
P4C422
AC TEST LOADS & WAVEFORMS
Figure 1a
Figure 1b
Figure 1c
Figure 1d
Document # SRAM101 REV. A
Page 5 of 10
P4C422
ORDERING INFORMATION
SELECTION GUIDE
The P4C422 is available in the following temperature range, speed, and package options.
Temperature
Range
Commercial
Temperature
Military
Temperature
Military
Processed*
Package
Speed (ns)
10
12
15
20
25
35
Plastic DIP
-10PC
-12PC
-15PC
-20PC
-25PC
-35PC
SOIC
-10SC
-12SC
-15SC
-20SC
-25SC
-35SC
Side Brazed DIP
N/A
N/A
-15CM
-20CM
-25CM
-35CM
CERDIP
N/A
N/A
-15DM
-20DM
-25DM
-35DM
LCC
N/A
N/A
-15LM
-20LM
-25LM
-35LM
CERPACK
N/A
N/A
-15FM
-20FM
-25FM
-35FM
Side Brazed DIP
N/A
N/A
-15CMB
-20CMB
-25CMB
-35CMB
CERDIP
N/A
N/A
-15DMB
-20DMB
-25DMB
-35DMB
LCC
N/A
N/A
-15LMB
-20LMB
-25LMB
-35LMB
CERPACK
N/A
N/A
-15FMB
-20FMB
-25FMB
-35FMB
*Military temperature range with MIL-STD-883, Class B compliance.
N/A = Not Available
Document # SRAM101 REV. A
Page 6 of 10
P4C422
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
α
C3-1
SIDE BRAZED DUAL IN-LINE PACKAGE
22 (400 Mil)
Min
Max
0.200
0.014
0.026
0.035
0.060
0.008
0.015
1.100
0.360
0.410
0.400 BSC
0.100 BSC
0.125
0.200
0.015
0.060
0.005
0.005
-
D3-1
CERDIP DUAL IN-LINE PACKAGE
22 (400 Mil)
Min
Max
0.225
0.014
0.026
0.045
0.065
0.008
0.018
1.111
0.350
0.410
0.400 BSC
0.100 BSC
0.125
0.200
0.015
0.070
0.005
0°
15°
Document # SRAM101 REV. A
Page 7 of 10
P4C422
Pkg #
# Pins
Symbol
A
b
c
D
E
e
k
L
Q
S
S1
Pkg #
# Pins
Symbol
A
A1
B1
D/E
D1/E1
D2/E2
D3/E3
e
h
j
L
L1
L2
ND
NE
F3
CERPACK CERAMIC FLAT PACKAGE
24
Min
Max
0.060
0.090
0.015
0.022
0.004
0.009
0.630
0.330
0.380
0.050 BSC
0.008
0.015
0.250
0.370
0.026
0.045
0.085
0.005
-
L4
SQUARE LEADLESS CHIP CARRIER
24
Min
Max
0.060
0.075
0.050
0.065
0.022
0.028
0.395
0.410
0.250 BSC
0.125 BSC
0.410
0.050 BSC
0.040 REF
0.020 REF
0.045
0.055
0.045
0.055
0.075
0.095
6
6
Document # SRAM101 REV. A
Page 8 of 10
P4C422
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
Pkg #
# Pins
Symbol
A
A1
b2
C
D
e
E
H
h
L
α
P3-1
22 (400 Mil)
Min
Max
0.210
0.015
0.014
0.022
0.045
0.065
0.009
0.015
1.065
1.120
0.330
0.390
0.390
0.425
0.100 BSC
0.500
0.115
0.160
0°
15°
S4
PLASTIC DUAL IN-LINE PACKAGE
SMALL OUTLINE IC PLASTIC PACKAGE
24 (300 Mil)
Min
Max
0.093
0.104
0.004
0.012
0.013
0.020
0.009
0.012
0.598
0.614
0.050 BSC
0.291
0.299
0.394
0.419
0.010
0.029
0.016
0.050
0°
8°
Document # SRAM101 REV. A
Page 9 of 10
P4C422
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM101
P4C422 HIGH SPEED 256 x 4 Static CMOS RAM
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
1997
DAB
New Data Sheet
A
Oct-05
JDB
Change logo to Pyramid
Document # SRAM101 REV. A
DESCRIPTION OF CHANGE
Page 10 of 10