PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal Features Description ÎÎConverts low-swing AC coupled differential input to HDMI Pericom Semiconductor’s PI3VDP411LST provides the ability to use a Dual-mode Display Port transmitter in HDMI mode. This flexibility provides the user a choice of how to connect to their favorite display. All signal paths accept AC coupled video signals. The PI3VDP411LST converts this AC coupled signal into an HDMI rev 1.3 compliant signal with proper signal swing. This conversion is automatic and transparent to the user. rev 1.3 compliant open-drain current steering Rx terminated differential output ÎÎHDMI level shifting operation up to 2.5Gbps per lane (250MHz pixel clock) ÎÎIntegrated 50-ohm termination resistors for AC-coupled differential inputs. ÎÎEnable/Disable feature to turn off TMDS outputs to enter lowpower state. ÎÎOutput slew rate control on TMDS outputs to minimize EMI. ÎÎTransparent operation: no re-timing or configuration required. ÎÎ3.3 Power supply required. ÎÎIntegrated ESD protection up to 8kV contact on all high speed I/O pins (IN_x and OUT_x) per IEC61000-4-2 specification, level 4 ÎÎDDC level shifters from 5V down to 3.3V ÎÎInverting level shifter for HPD signal from HDMI/DVI ÎÎconnector ÎÎIntegrated pull-down on HPD_sink input guarantees "input low" when no display is plugged in ÎÎPackaging (Pb-Free & Green) àà 48 TQFN, 7mm × 7mm (ZD) àà 48 TQFN, 7mm × 7mm (ZB) The PI3VDP411LST supports up to 2.5Gbps, which provides 12bits of color depth per channel, as indicated in HDMI rev 1.3. Block Diagram OE# OUT_D4+ OUT_D4- 0V IN_D4+ IN_D4- Rx OUT_D3+ OUT_D3- 0V IN_D3+ IN_D3- Rx VDD OE# OUT_D2+ GND SCL_SINK HPD_SINK SDA_SINK DDC_EN GND VDD EQ_1 EQ_0 GND Pin Configuration 48-Pin TQFN (ZD/ZB) 26 25 24 OUT_D2- 0V IN_D2+ IN_D2- 36 35 34 33 32 31 30 29 28 27 GND 37 IN_D1- 38 23 OUT_D1- IN_D1+ 39 22 OUT_D1+ VDD 40 21 VDD GND IN_D2- 41 20 OUT_D2- IN_D2+ 42 19 OUT_D2+ GND 43 18 GND IN_D3- 44 17 OUT_D3- IN_D3+ 45 16 OUT_D3+ VDD 46 15 VDD IN_D4- 47 14 OUT_D4- IN_D4+ 48 OUT_D4+ 1 2 3 4 5 6 7 8 9 10 11 13 12 GND VDD OC_0 OC_1 GND OC_2(REXT ) HPD_SOURCE# SDA_SOURCE SCL_SOURCE OC_3 VDD GND GND 11-0083 Rx OUT_D1+ OUT_D1- 0V IN_D1+ IN_D1- HPD_SOURCE# 1 Rx HPD HPD_SINK SCL_SOURCE SCL_SINK SDA_SOURCE SDA_SINK PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal Maximum Ratings (Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................–65°C to +150°C Supply Voltage to Ground Potential .............–0.5V to +5V DC Input Voltage ..........................................–0.5V to VDD DC Output Current .......................................120mA Power Dissipation .........................................1.0W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 2: Signal Descriptions Pin Name Type Description Enable for level shifter path 5.5V tolerant low-voltage singleended input OE# OE# IN_D Termination OUT_D Outputs 1 >100KΩ High-Z 0 50Ω Active IN_D4+ Differential input Low-swing diff input from GMCH PCIE outputs. IN_D4+ makes a differential pair with IN_D4–. IN_D4– Differential input Low-swing diff input from GMCH PCIE outputs. IN_D4– makes a differential pair with IN_D4+. IN_D3+ Differential input Low-swing diff input from GMCH PCIE outputs. IN_D3+ makes a differential pair with IN_D3–. IN_D3– Differential input Low-swing diff input from GMCH PCIE outputs. IN_D3– makes a differential pair with IN_D3+. IN_D2+ Differential input Low-swing diff input from GMCH PCIE outputs. IN_D2+ makes a differential pair with IN_D2–. IN_D2– Differential input Low-swing diff input from GMCH PCIE outputs. IN_D2– makes a differential pair with IN_D2+. IN_D1+ Differential input Low-swing diff input from GMCH PCIE outputs. IN_D1+ makes a differential pair with IN_D1–. IN_D1– Differential input Low-swing diff input from GMCH PCIE outputs. IN_D1– makes a differential pair with IN_D1+. OUT_D4+ TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential output signal with OUT_D4–. OUT_D4– TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D4– makes a differential output signal with OUT_D4+. OUT_D3+ TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential output signal with OUT_D3–. OUT_D3– TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D3– makes a differential output signal with OUT_D3+. 11-0083 2 PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal Pin Name Type Description OUT_D2+ TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential output signal with OUT_D2–. OUT_D2– TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D2– makes a differential output signal with OUT_D2+. OUT_D1+ TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential output signal with OUT_D1–. OUT_D1– TMDS Differential output HDMI 1.3 compliant TMDS output. OUT_D1– makes a differential output signal with OUT_D1+. HPD_SINK 5V tolerance single-ended input Low Frequency, 0V to 5V (nominal) input signal. This signal comes from the HDMI connector. Voltage High indicates "plugged" state; voltage low indicated "unplugged". HPD_SINK is pulled down by an integrated 100K ohm pull-down resistor. HPD_SOURCE# 1V buffer Inverted buffer from 0V to 5V input signal. If input is LOGIC HIGH, then output will be LOGIC LOW, with VOL max of 0.1V max. If input is LOGIC LOW, then output will be LOGIC HIGH, with VOH of 0.8V min. SCL_SOURCE Single-ended 3.3V open-drain DDC I/O 3.3V DDC Data I/O. Pulled up by external termination to 3.3V. Connected to SCL_SINK through voltage-limiting integrated NMOS passgate. SDA_SOURCE Single-ended 3.3V open-drain DDC I/O 3.3V DDC Data I/O. Pulled up by external termination to 3.3V. Connected to SDA_SINK through voltage-limiting integrated NMOS passgate. SCL_SINK Single-ended 5V open-drain DDC I/O 5V DDC Clock I/O. Pulled up by external termination to 5V. Connected to SCL_SOURCE through voltage-limiting integrated NMOS passgate. SDA_SINK Single-ended 5V open-drain DDC I/O 5V DDC Data I/O. Pulled up by external termination to 5V. Connected to SDA_SOURCE through voltage-limiting integrated NMOS passgate. Enables bias voltage to the DDC passgate level shifter gates. (May be implemented as a bias voltage connection to the DDC pass gates themselves.) DDC_EN VDD OC_2 (1) (REXT) 5.0V tolerant Single-ended input DDC_EN Passgate 0V Disabled 3.3V Enabled 3.3V DC Supply 3.3V ± 10% 3.3V single-ended control input Acceptable connections to OC_1 (REXT) pin are: Resistor to GND; Resistor to 3.3V; NC. (Resistor should be 0-ohm). Note: 1) internal 100Kohm pull-up 11-0083 3 PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal Pin Name Type Description OC_3 Analog connection to external compo- Acceptable connections to OC_3 pin are: short to 3.3V or to nent or supply GND; NC. OC_0 OC_1 Output and Input jitter elimination control EQ_0 EQ_1 Control pins are to enable Jitter elimination features. For normal operation these pins are tied GND or to VDD. Please see the truth tables for more information. Truth Table 1 OC_3(2) OC_2(1) OC_1(1) OC_0(1) Vswing (mV) Pre/De-emphasis 0 0 0 0 500 0 0 0 0 1 600 0 0 0 1 0 750 0 0 0 1 1 1000 0 0 1 0 0 500 0 0 1 0 1 500 1.5dB 0 1 1 0 500 3.5dB 0 1 1 1 500 6dB 1 0 0 0 400 0 1 0 0 1 400 3.5dB 1 0 1 0 400 6dB 1 0 1 1 400 9dB 1 1 0 0 1000 0 1 1 0 1 1000 -3.5dB 1 1 1 0 1000 -6dB 1 1 1 1 1000 -9dB Truth Table 2 EQ_1(2) EQ_0(1) Equalization @ 1.25GHz (dB) 0 0 3 0 1 6 1 0 9 1 1 12 Notes: 1. Internal 100Kohm pull-up 2. For 42-TQFN (ZHE) package, there is an internal connection to GND. 3. For 48-TQFN (ZDE) package, external connection is allowed and there is an internal 100KW pull-up. 11-0083 4 PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal Electrical Characteristics Table 3: Power Supplies and Temperature Range Symbol Parameter Min Nom Max Units VDD 3.3V Power Supply 3.0 3.3 3.6 V ICC Max Current 100 mA Total current from VDD 3.3V supply when deemphasis/pre-emphasis is set to 0dB. ICCQ Standby Current Consumption 2 mA OE# = HIGH TCASE Case temperature range for operation with spec. 85 Celsius -40 Comments Table 4: OE# Description OE# Device State Comments Asserted (low voltage) Differential input buffers and output buffers enabled. Input impedance = 50Ω Normal functioning state for IN_D to OUT_D level shifting function. Low-power state. Unasserted (high voltage) Differential input buffers and termination are disabled. Differential inputs are in a high-impedance state. OUT_D level-shifting outputs are disabled. OUT_D level-shifting outputs are in highimpedence state. Internal bias currents are turned off. 11-0083 5 Intended for lowest power condition when: • No display is plugged in or • The level shifted data path is disabled HPD_SINK input and HPD_SOURCE# output are not affected by OE# SCL_SOURCE, SCL_SINK, SDA_SOURCE and SDA_SINK signals and functions are not affected by OE# PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal Table 5: Differential Input Characteristics for IN_D and RX_IN signals Symbol Parameter Min Tbit Unit Interval 360 VRX-DIFFp-p Differential Input Peak to Peak Voltage 0.175 TRX-EYE Minimum Eye Width at IN_D input pair 0.8 Nom Max Units Comments ps 1.200 V Tbit 100 Common Mode Input Voltage Applies to IN_D and RX_IN signals The level shifter may add a maximum of 0.02UI jitter mV VRX-CM-DC = DC(avg) of|VRX-D+ + VRXD-|/2 VCM-AC-pp includes all frequencies above 30 kHz. ZRX-DC 40 VRX-Bias 0 ZRX-HIGH-Z 100 11-0083 VRX-DIFFp-p=2'|VRX-D+ x VRX-D-| VCM-AC-pp = |VRX-D+ + VRX-D-|/2 - VRXCM-DC. AC Peak VCM-AC-pp Tbit is determined by the display mode. Nominal bit rate ranges from 250Mbps to 2.5Gbps per lane. Nominal Tbit at 2.5Gbps=400ps. 360ps=400ps-10% 50 6 60 Ω Required IN_D+ as well as IN_D- DC impedance (50Ω ± 20% tolerance). 2.0 V Intended to limit power-up stress on chipset's PCIE output buffers. kΩ Differential inputs must be in a high impedance state when OE# is HIGH. PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal TMDS Outputs The level shifter's TMDS outputs are required to meet HDMI 1.3 specifications. The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3 specification. Table 6: Differential Output Characteristics for TMDS_OUT signals Symbol Parameter VH Single-ended high level output voltage AVDD-10mV AVDD VL Single-ended low level output voltage AVDD-600mV VSWING Single-ended out450mV put swing voltage IOFF Single-ended current in high-Z state TR Rise time TF Fall time TSKEW-INTRA TSKEW-INTER Min Nom Units Comments AVDD+10mV V AVDD is the DC termination voltage in the HDMI or DVI Sink. AVDD is nominally 3.3V AVDD-500mV AVDD-400mV V The open-drain output pulls down from AVDD. 500mV 600mV V Swing down from TMDS termination voltage (3.3V ± 10%) 50 µA Measured with TMDS outputs pulled up to AVDD Max (3.6V) through 50Ω resistors. 125ps 0.4Tbit ps Max Rise/Fall time @2.7Gbps = 148ps. 125ps = 148-15% 125ps 0.4Tbit ps Max Rise/Fall time @2.7Gbps = 148ps. 125ps = 148-15% ps This differential skew budget is in addition to the skew presented between D+ and Dpaired input pins. HDMI revision 1.3 source allowable intra-pair skew is 0.15Tbit. ps This lane-to-lane skew budget is in addition to skew between differential input pairs ps Jitter budget for TMDS signals as they pass through the level shifter. 25ps = 0.056 Tbit at 2.25 Gb/s Intra-pair 30 differential skew Inter-pair laneto-lane output skew 100 Jitter added to TMDS signals TJIT 11-0083 Max 25 7 PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal TMDS output oscillation elimination The inputs do not incorporate a squelch circuit. Therefore, we reccomend the input to be externally biased to prevent output oscillation. Pericom reccomends to add a 1.5Kohm pull-up to the CLK- input for each oif the video input ports. VBIAS 3.3V 1.5Kohm RINT RINT DMDP Receiver TMDS Driver SS RT AVDD SS RT TMDS Input Fail-Safe Recommendation 11-0083 8 PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal Table 8: HPD Characteristics Symbol Parameter Input High Level VIH-HPD Min Nom Max Units Comments 2.0 5.0 5.3 V Low-speed input changes state on cable plug/ unplug 0.8 V VIL-HPD HPD_sink Input Low Level IIN-HPD HPD_sink Input Leakage Current 70 μA Measured with HPD_sink at VIH-HPD max and VIL-HPD min VOH-HPDB HPD_Source# Output High-Level, IOH = 0.8 -200μA 1.1 V VDD = 3.3V ± 10% VOL-HPDB HPD_Source# Output Low-Level, IOL = 0 200μA 0.1 V THPD HPD_Source# to HPD_source propagation delay 200 ns Time from HPD_sink changing state to HPD_source# changing state. Includes HPD_source rise/fall time TRF-HPDB HPD_Source# rise/ fall time 20 ns Time required to transition from VOH-HPD to VOL-HPD or from VOL-HPD to VOH-HPD 0 1 Table 9: OE# Input and DDC_EN Symbol Parameter Min VIH Input High Level 2.0 VIL Input Low Level 0 IIN Input Leakage Current Nom Max Units Comments VDD V TMDS enable input changes state on cable plug/unplug 0.8 V 10 μA Measured with input at VIH-EN max and VIL-EN min DDC I/O Pins (SCL, SCL_SINK, SDA, SDA_SINK) |Ilkg| Input leakage current VI = 0.1VDD to 0.9VDD to isolated DDC ports 0.1 CIO Input/output capacitance VI = 0V 7.5 RON Switch resistance IO = 3mA, VO = 0.4V VPASS Switch output voltage VI = 3.3V, II = 100µA 1.5(2) 2 µA pF 25 50 ohm 2.0 2.5(3) V Table 10: Termination Resistors Symbol Parameter Min Nom Max Units Comments R HPD HPD_sink input pulldown resistor. 80K 100k 120K Ω Guarantees HPD_sink is LOW when no display is plugged in. 11-0083 9 PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal Recommended Power Supply Decoupling Circuit Figure 1 is the recommended power supply decoupling circuit configuration. It is recommended to put 0.1µF decoupling capacitors on each VDD pins of our part, there are four 0.1µF decoupling capacitors are put in Figure 1 with an assumption of only four VDD pins on our part, if there is more or less VDD pins on our Pericom parts, the number of 0.1µF decoupling capacitors should be adjusted according to the actual number of VDD pins. On top of 0.1µF decoupling capacitors on each VDD pins, it is recommended to put a 10µF decoupling capacitor near our part’s VDD, it is for stabilizing the power supply for our part. Ferrite bead is also recommended for isolating the power supply for our part and other power supplies in other parts of the circuit. But, it is optional and depends on the power supply conditions of other circuits. 10µF Ferrite Bead From main power supply 0.1µF V DD 0.1µF V DD P e r ic o m P a r t 0.1µF V DD 0.1µF V DD Figure 1 Recommended Power Supply Decoupling Circuit Diagram 11-0083 10 PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal Requirements on the Decoupling Capacitors There is no special requirement on the material of the capacitors. Ceramic capacitors are generally being used with typically materials of X5R or X7R. Layout and Decoupling Capacitor Placement Consideration i. Each 0.1µF decoupling capacitor should be placed as close as possible to each VDD pin. ii. VDD and GND planes should be used to provide a low impedance path for power and ground. iii. Via holes should be placed to connect to VDD and GND planes directly. iv. Trace should be as wide as possible v. Trace should be as short as possible. vi. The placement of decoupling capacitor and the way of routing trace should consider the power flowing criteria. vii. 10µF capacitor should also be placed closed to our part and should be placed in the middle location of 0.1µF capacitors. viii.Avoid the large current circuit placed close to our part; especially when it is shared the same VDD and GND planes. Since large current flowing on our VDD or GND planes will generate a potential variation on the VDD or GND of our part. V DD P la ne Bypass noise Power Flow G N D P la ne 0 .1 uF P e r ic o m P a r t Figure 2 Layout and Decoupling Capacitor Placement Diagram 11-0083 11 PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal 1 DATE: 02/12/09 Notes: 1. All dimensions are in millimeters, angles are in degrees. 2. Refer JEDEC MO-220/VKKD 3. Thermal Pad Soldering Area 4. Depending on the method of lead termination at the edge of the package, pull back maybe present. 5. Recommended Land Pattern is for reference only. DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZD (ZD48) DOCUMENT CONTROL #: PD-2045 REVISION: D 09-0117 11-0083 12 PS8906G 07/12/11 PI3VDP411LST Digital Video Level Shifter for dual mode DP signals w/ inverting buffer for HPD signal UNIT: mm 1 DATE: 02/11/09 Notes: 1. All dimensions are in millimeters, angles are in degrees. 2. Coplanarity applies to the exposed thermal pad as well as the terminals. 3. Refer JEDEC MO-220 4. Recommended land pattern is for reference only. 5. Thermal pad soldering area DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN) PACKAGE CODE: ZB48 DOCUMENT CONTROL #: PD-2080 REVISION: A 09-0091 Note: • For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php Ordering Information Ordering Code Package Code Package Description PI3VDP411LSTZDE ZD 48-pin Pb-free & Green, TQFN PI3VDP411LSTZBE ZB 48-pin Pb-free & Green, TQFN Notes: • Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ • E = Pb-free and Green • Adding an X Suffix = Tape/Reel Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com 11-0083 13 PS8906G 07/12/11