PI3VDP411LSA

PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Features
Description
ÎÎConverts low-swing AC coupled differential input to
Pericom Semiconductor’s PI3VDP411LSA provides the ability
to use a Dual-mode DisplayPort™ transmitter in HDMI™ mode.
This flexibility provides the user a choice of how to connect to
their favorite display. All signal paths accept AC coupled video
signals. The PI3VDP411LSA converts this AC coupled signal into
an HDMI rev 1.3 compliant signal with proper signal swing. This
conversion is automatic and transparent to the user.
HDMI™ rev 1.3 compliant open-drain current steering Rx
terminated differential output
ÎÎHDMI Level shifting operation up to 2.5Gbps per lane
(250MHz pixel clock)
ÎÎIntegrated 50-ohm termination resistors for AC-coupled
differential inputs.
ÎÎEnable/Disable feature to turn off TMDS outputs to enter
Output squelch function is provided for each channel. When output channel is enable (OE#=0) and operating, that TMDS pixel
clock input signal determines whether the output is enabled.
When no TMDS pixel clock is present, TMDS output channel
will be disabled.
ÎÎOutput slew rate control on TMDS outputs to minimize
The PI3VDP411LSA supports up to 2.5Gbps, which provides 12bits of color depth per channel, as indicated in HDMI rev 1.3.
ÎÎProvide Output Squelch function to turn off TMDS
common mode output buffer when TMDS clock is not
present
low-power state.
EMI
ÎÎIntegrated Active / Passive DDC level shifters
to 5V sink)
(3.3V source
ÎÎTransparent operation: no re-timing or configuration
required
Pin Configuration (48-Pin TQFN)
ÎÎLevel shifter for HPD signal from HDMI/DVI connector
NC
SQSEL
VDD
DDC_EN
GND
HPD_SINK
SDA_SINK
SCL_SINK
GND
VDD
OE#
"input low" when no display is plugged in
GND
ÎÎIntegrated pull-down on HPD_SINK input guarantees
36
35
34
33
32
31
30
29
28
27
26
25
24
ÎÎ3.3V Power supply required
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1
38
23
OUT_D1-
IN_D1+
39
22
OUT_D1+
VDD
40
21
VDD
IN_D2-
41
20
OUT_D2-
IN_D2+
42
19
OUT_D2+
GND
43
18
GND
IN_D3-
44
17
OUT_D3-
IN_D3+
45
16
OUT_D3+
VDD
46
15
VDD
IN_D4-
47
14
OUT_D4-
IN_D4+
48
OUT_D4+
6
7
8
9
10
11
DDCBSEL
VDD
GND
5
SCL_SOURCE
4
SDA_SOURCE
3
HPD_SOURCE
2
13
12
NC
1
GND
GND
SR1
àà 48 TQFN, 7mm × 7mm (ZBE)
IN_D1-
SR0
àà 4kV HBM
àà ±8kV contact ESD protection on the following pins
→→ OUT_Dx±
→→ SDA_SINK, SCL_SINK
→→ HPD_SINK
ÎÎPackaging (Pb-free & Green available):
37
VDD
ÎÎESD protection on all I/O pins
GND
GND
ÎÎTMDS output enable control
GND
www.pericom.com PS9059A07/28/12
PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Block Diagram
OE#
0V
OUT_D4/3/2/1+
OUT_D4/3/2/1-
50Ω
50Ω
IN_D4/3/2/1+
Rx
IN_D4/3/2/1-
SR1/0
SQSEL
Control
Logic
DDC_EN (0V to 3.3V)
DDCBSEL
SDA_SOURCE
SDA_SINK
SCL_SOURCE
SCL_SINK
HPD_SOURCE
HPD_SINK
HPD
100KΩ
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Pin Description
Pin
Name
I/O Type
Descriptions
1, 5, 12, 18, 24,
GND
27, 31, 36, 37, 43
POWER
GROUND
2, 11, 15, 21, 26,
VDD
33, 40, 46
POWER
POWER, 3.3V ±10%
3, 4
SR0, SR1
I
Slew Rate Control. Acceptable connections to SRx pin are: resistor to 3.3V or
short to GND. (internal 200KΩ pull-LOW)
6, 35
NC
O
No Connect
7
HPD_SOURCE
O
HPD_SOURCE: 0V to 3.3V (nominal) output signal. HPD_Sink input can be as
high as 5V and then HPD_Source will output no higher than 3.3V.
3.3V DDC Data I/O. Pulled up by external termination to 3.3V.
8
SDA_SOURCE
I/O
DDC_EN
DDCBSEL
DDC level shifter type
Low
X
DISABLE DDC level shifter
High
Low
Passive level shifter ENABLE
Connected to SDA_SINK through voltagelimiting integrated NMOS passgate
Active level shifter ENABLE
High
High
Connected to SDA_SINK through bi-direction buffer
3.3V DDC Data I/O. Pulled up by external termination to 3.3V.
9
SCL_SOURCE
I/O
DDC_EN
DDCBSEL
DDC level shifter type
Low
X
DISABLE DDC level shifter
High
Low
Passive level shifter ENABLE
Connected to SCL_SINK through voltagelimiting integrated NMOS passgate
High
High
Active level shifter ENABLE
Connected to SCL_SINK through bi-direction
buffer
Active DDC level shifter enable pin. (internal 200KΩ pull-LOW)
10
DDCBSEL
I
DDCBSEL
DDC path
Low (0V)
Passive DDC level shifter
High (3.3V)
Active DDC level shifter
13
OUT_D4+
O
HDMI 1.3 compliant TMDS output. OUT_D4+ makes a differential output
signal with OUT_D4-.
14
OUT_D4-
O
HDMI 1.3 compliant TMDS output. OUT_D4- makes a differential output
signal with OUT_D4+
16
OUT_D3+
O
HDMI 1.3 compliant TMDS output. OUT_D3+ makes a differential output
signal with OUT_D3-.
17
OUT_D3-
O
HDMI 1.3 compliant TMDS output. OUT_D3- makes a differential output
signal with OUT_D3+
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Pin
Name
I/O Type
Descriptions
19
OUT_D2+
O
HDMI 1.3 compliant TMDS output. OUT_D2+ makes a differential output
signal with OUT_D2-.
20
OUT_D2-
O
HDMI 1.3 compliant TMDS output. OUT_D2- makes a differential output
signal with OUT_D2+
22
OUT_D1+
O
HDMI 1.3 compliant TMDS output. OUT_D1+ makes a differential output
signal with OUT_D1-.
23
OUT_D1-
O
HDMI 1.3 compliant TMDS output. OUT_D1- makes a differential output
signal with OUT_D1+
Enable for level shifter path.
25
OE#
I
OE#
IN_D Termination
OUT_D Outputs
1
> 100KΩ
High-Z
0
50Ω
Active
5V DDC Clock I/O. Pulled up by external termination to 5V.
28
SCL_SINK
I/O
DDC_EN
DDCBSEL
DDC level shifter type
Low
X
DISABLE DDC level shifter
High
Low
Passive level shifter ENABLE
Connected to SCL_SOURCE through voltagelimiting integrated NMOS passgate
High
High
Active level shifter ENABLE
Connected to SCL_SOURCE through bidirection buffer
5V DDC Data I/O. Pulled up by external termination to 5V.
29
SDA_SINK
30
HPD_SINK
I/O
I
DDC_EN
DDCBSEL
DDC level shifter type
Low
X
DISABLE DDC level shifter
High
Low
Passive level shifter ENABLE
Connected to SDA_SOURCE through voltagelimiting integrated NMOS passgate
High
High
Active level shifter ENABLE
Connected to SDA_SOURCE through bidirection buffer
Low Frequency, 0V to 5V (nominal) input signal. This signal comes from the
TMDS connector. Voltage High indicates “plugged” state; voltage low indicated
“unplugged”. HPD_SINK is pulled down by an integrated 100K ohm pull-down
resistor.
Enables DDC level shifter path
32
DDC_EN
12-0236
I
DDC_EN
Passgate
Low (0V)
Disable
High (3.3V)
Enable
4
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Pin
Name
I/O Type
Descriptions
TMDS clock detection setting
Pulled up by external termination to 3.3V or short to GND.
SQSEL Clock Monitor Pin
34
SQSEL
I
0
1
Device monitor HDMI pixel clock on Pin38/39
(Channel IN_D1±)
Device monitor DVI pixel clock on Pin 47/48
(Channel IN_D4±)
38
IN_D1-
I
Low-swing diff input from DP Tx outputs. IN_D1- makes a differential pair
with IN_D1+.
39
IN_D1+
I
Low-swing diff input from DP Tx outputs. IN_D1+ makes a differential pair
with IN_D1-.
41
IN_D2-
I
Low-swing diff input from DP Tx outputs. IN_D2- makes a differential pair
with IN_D2+.
42
IN_D2+
I
Low-swing diff input from DP Tx outputs. IN_D2+ makes a differential pair
with IN_D2-.
44
IN_D3-
I
Low-swing diff input from DP Tx outputs. IN_D3- makes a differential pair
with IN_D3+.
45
IN_D3+
I
Low-swing diff input from DP Tx outputs. IN_D3+ makes a differential pair
with IN_D3-.
47
IN_D4-
I
Low-swing diff input from DP Tx outputs. IN_D4- makes a differential pair
with IN_D4+.
48
IN_D4+
I
Low-swing diff input from DP Tx outputs. IN_D4+ makes a differential pair
with IN_D4-.
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Truth Table (Slew Rate control function)
SR1
SR0
Rise/Fall Time (Typ)
1
1
140ps
1
0
130ps
0
1
120ps
0
0
110ps
Test Setup Condition
VDD = 3.3V, Ambient temperature 25°C
Rise/Fall time is from 20% to 80% on Rising/Falling edge
Date rate: 620 Mbps
Input: 1V differential peak-to-peak clock pattern
Equalization : 3dB
Table 1: OE Pin Description
OE#
Device State
Comments
Asserted (low voltage)
Differential input buffers and output buffers
enabled. Input impedance = 50Ω
Normal functioning state for IN_D to OUT_D
level shifting function.
Low-power state.
Unasserted (high voltage)
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àà Differential input buffers and termination Intended for lowest power condition when:
àà No display is plugged in or
are disabled.
àà The level shifted data path is disabled
àà Differential inputs are in a high
HPD_SINK input and HPD_SOURCE
impedance state.
output are not affected by OE# SCL_
àà OUT_D level-shifting outputs are
SOURCE, SCL_SINK, SDA_SOURCE
disabled.
and SDA_SINK signals and functions
àà OUT_D level-shifting outputs are in high
are not affected by OE#
impedance state.
àà Internal bias currents are turned off.
6
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Absolute Maximum Ratings (Over operating free-air temperature range)
Item
Rating
Supply Voltage to Ground Potential
5.5V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
-40 to +85°C
Storage Temperature
-65 to +150°C
Junction Temperature
150°C
Soldering Temperature
260°C
Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Electrical Characteristics
Table: Power Supplies and Temperature Range
Symbol
Parameter
Min
Typ
Max
Units
VDD
3.3V Power supply
3.0
3.3
3.6
V
ICC
Max Current
100
mA
ICC_squelch
Supply Current when no
TMDS clock present
ICCQ
Standby Current
TCASE
Case temperature range
for operation with spec.
12-0236
8
-40
Comments
mA
2
mA
85
Celsius (°)
7
OE# = HIGH
www.pericom.com PS9059A07/28/12
PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Table: Differential Input Characteristics forIN_Dx signals
Symbol
Parameter
Min
Tbit
UI, Unit Interval
360
VRX_DIFF
Input Differential Voltage Level
0.175
TRX_EYE
Minimum Eye Width at
IN_D input pair
0.8
VCM-ACp-p
AC Peak Common
Mode Input Voltage
ZRX_DC
40
ZRX-Bias
0
ZRX_HIGH-Z
100
Typ
Max
Units
Comments
ps
Tbit is determined by the display mode. Nominal
bit rate ranges from 250Mbps to 2.5Gbps per lane.
Nominal Tbit at 2.5 Gbps = 400 ps. 360ps = 400ps10%
1.200 V
See note 1 below
Tbit
50
100
mV
See note 2 below
60
Ω
Required IN_D+ as well as IN_D- DC impedance
(50 ±20% tolerance).
2.0
V
Intended to limit power-up stress on chipset's PCIE
output buffers.
kΩ
Differential inputs must be in a high impedance
state when OE# is HIGH.
1. VRX-DIFF = 2x|VRX-D- -VRX-D-| Applies to IN_Dx signals
2. VCM-AC-p-p = |VRX-D - - VRX-D -|/2 - VRX-CM-DC
VRX-CM-DC = DC(avg) of |VRX-D+ + VRX-D -|/2
VCM-AC-p-p includes all frequencies above 30 kHz.
TMDS Outputs
The level shifter's TMDS outputs are required to meet HDMI 1.3 specifications.
The HDMI 1.3 Specification is assumed to be the correct reference in instances where this document conflicts with the HDMI 1.3
specification.
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Table 2: Differential Output Characteristics for TMDS_OUT signals
Symbol
Parameter
Min
Typ
Max
Units
Comments
VH
Single-ended high
level output voltage
VDD -10mV
VDD
VDD+10mV
V
VDD is the DC termination voltage
in the HDMI or DVI Sink. VDD is
nominally 3.3V
VL
Single-ended low level
VDD -600mV VDD -500mV VDD -400mV V
output voltage
The open-drain output pulls down
from VDD.
VSWING
Single ended output
swing voltage
IOFF
Single-ended current
in high-Z state
425
500
600
mV
Swing down from TMDS termination voltage (3.3V ±10%)
50
µA
Measured with TMDS outputs
pulled up to VDD Max _(3.6V)
through 50Ω resistors.
TSKEW-INTRA
Intra-pair differential
skew
30
ps
This differential skew budget is in
addition to the skew presented between D+ and D- paired input pins.
HDMI revision 1.3 source allowable
intrapair skew is 0.15 Tbit.
TSKEW-INTER
Inter-pair lane-to-lane
output skew
100
ps
This lane-to-lane skew budget is in
addition to skew between differential input pairs
TJIT
Jitter added to TMDS
signals
25
ps
Jitter budget for TMDS signals as
they pass through the level shifter.
25ps = 0.056 at 2.25 Gbps
TMDS output oscillation elimination
The inputs already incorporate a squelch circuit. Therefore, nothing is needed from application standpoint to eliminate TMDS output
oscillation when there is no TMDS input present. The IC will do this automatically.
Table 3: HPD Characteristics
Symbol
Parameter
Min
Typ
Max
Units
Comments
VIH-HPD
Input High Level
2.0
5.0
5.3
V
Low-speed input changes state on cable plug/
unplug
VIL-HPD
HPD_SINK Input Low
Level
0
0.8
V
IIN-HPD
HPD_SINK Input Leakage
Current
70
µA
VOH-HPD
HPD_source Output
High-Level
VDD
V
VOL-HPD
HPD_source Output Low0
Level
0.4
V
IOL = 4mA(MIN) / 8mA(MAX)
THPD
HPD_SINK to HPD_
source propagation delay
200
ns
Time from HPD_SINK changing state to
HPD_source changing state. Includes HPD_
source rise/fall time
TRF-HPDB
HPD_source rise/ fall time 1
20
ns
Time required to transition from VOH- HPDB
to VOL-HPDB or from VOL-HPDB to VOH-HPDB
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2.5
9
Measured with HPD_SINK at VIH-HPD max
and VIL-HPD min
VDD = 3.3V ±10%
IOH = -4mA(MIN) / -8mA(MAX)
www.pericom.com PS9059A07/28/12
PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Table 4: OE# Input, SQSEL and DDC_EN
Symbol
Parameter
Min
VIH
Input High Level
VIL
Input Low Level
IIN
Input Leakage Current
Typ
Max
Units
Comments
2.0
VDD
V
TMDS enable input changes state on cable
plug/unplug
0
0.8
V
10
µA
Measured with input at VIH-EN max and
VIL-EN min
Max
Units
Comments
Ω
Guarantees HPD_SINK is LOW when no
display is plugged in.
Table 5: Termination Resistor
Symbol
Parameter
Min
R HPD
HPD_SINK input pulldown resistor.
100K
12-0236
Typ
10
www.pericom.com PS9059A07/28/12
PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Packaging Mechanical: 48-Pin TQFN (ZB)
UNIT: mm
1
DATE: 02/11/09
Notes:
1. All dimensions are in millimeters, angles are in degrees.
2. Coplanarity applies to the exposed thermal pad as well as the terminals.
3. Refer JEDEC MO-220
4. Recommended land pattern is for reference only.
5. Thermal pad soldering area
DESCRIPTION: 48-Pin, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZB48
REVISION: A
DOCUMENT CONTROL #: PD-2080
09-0091
Note:
1.For latest package info, please check: http://www.pericom.com/support/packaging/packaging-mechanicals-and-thermal-characteristics
2.The exposed die paddle size is 3.6x3.6mm for PI3VDP411LSAZBE
3. Pad size (D2 * E2) is 157 x 157 mm
Pericom Semiconductor Corporation • 1-800-435-2336
12-0236
All trademarks are property of their respective owners.
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
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Reference Information
Document
Description
VESA DisplayPort Standard Version 1 Revision 2, Video Electronics Standards Association, January 5, 2010
VESA DisplayPort Dual-Mode Standard Version 1, Video Electronics Standards Association, February 10,
2012
VESA
VESA DisplayPort Interoperability Guideline Version 1.1a, Video Electronics Standards Association, February 5, 2009
HDMI
High-Definition Multimedia Interface Specification Version 1.4, HDMI Licensing, LLC, June 5, 2009
Ordering Information
Ordering Code
Package Code
Package Type
PI3VDP411LSAZBE
ZB
Pb-free & Green, 48-pin TQFN
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
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PI3VDP411LSA
Dual Mode DisplayPort™ to DVI/HDMI™ Electrical bridge (Level Shifter)
Revision History
Date
Changes
7/28/2012
Actual pad size 157 x 157 mil in package drawing
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