PI6C49S1510

PI6C49S1510
High Performance Differential Fanout Buffer
Features
Description
ÎÎ10 differential outputs with 2 banks
The PI6C49S1510 is a high performance fanout buffer devicewhich supports up to 1.5GHz frequency. It also integrates a
unique feature with user configurable output signaling standards on per bank basis which provide great flexibilities to
users. The device also uses Pericom's proprietary input detection
technique to make sure illegal input conditions will be detected
and reflected by output states. This device is ideal for systems
that need to distribute low jitter clock signals to multiple destinations.
ÎÎUser configurable output signaling standard for each bank:
LVDS or LVPECL or HCSL
ÎÎLVCMOS reference output up to 200MHz
ÎÎUp to 1.5GHz output frequency for differential outputs
ÎÎUltra low additive phase jitter: < 0.03 ps
(typ) (differential
156.25MHz, 12KHz to 20MHz integration range); < 0.02 ps
(typ) (differential 156.25MHz, 10kHz to 1MHz integration
range)
ÎÎSelectable reference inputs support either single-ended
Applications
or differential or Xtal
ÎÎNetworking systems including switches and Routers
ÎÎLow skew between outputs within banks (<40ps)
ÎÎHigh frequency backplane based computing and telecom
ÎÎLow delay from input to output (Tpd typ. < 1.7ns)
platforms
ÎÎSeparate Input output supply voltage for level shifting
ÎÎ2.5V / 3.3V power supply
ÎÎIndustrial temperature support
ÎÎTQFN-48 package
Block Diagram
OPMODEA[1:0]
Ref_Out
IN_SEL[1:0]
Sync_OE
Sync
Iref
GND
Iref
OPMODEB_1
IN1-
34
QB1+
QA1-
4
33
QB1-
VDDO
5
32
VDDO
QA2+
6
31
QB2+
QA2-
7
30
QB2-
VDDO
8
29
VDDO
QA3+
9
28
QB3+
QA3-
10
27
QB3-
QA4+
11
26
QB4+
QA4-
12
25
QB4-
GND
X2
X1
VDD
OPMODEA_0
GND
1
IN1+
3
13 14 15 16 17 18
14-0137
VDD
GND
Ref_Out
VDDO
QBO-
QA1+
19 20 21 22 23 24
PI6C49S1510
GND
IN1+
IN1-
35
OPMODEB_0
5
QBO+
2
IN_SEL_1
QB[0:4]
36
QAO-
IN0-
IN0+
IN0-
1
IN0+
OPMODEB[1:0]
42 41 40 39 38 37
QAO+
IN_SEL_0
5
OSC
Sync_OE
48 47 46 45 44 43
QA[0:4]
X1
X2
OPMODEA_1
GND
Pin Configuration (48-Pin TQFN)
Rev G
09/18/2014
PI6C49S1510
High Performance Differential Fanout Buffer
Pinout Table
Pin #
Pin Name
QA0+
1,2
QA0QA1+
3,4
QA1-
5,8,29,32,45
VDDO
QA2+
6,7
QA2QA3+
9,10
QA3QA4+
11,12
QA4-
Type
Description
Output
Bank A differential output pair 0. Pin selectable
LVPECL/LVDS/HCSL interface levels.
Output
Bank A differential output pair 1. Pin selectable
LVPECL/LVDS/HCSL interface levels.
Power
Power supply pins for IO
Output
Bank A differential output pair 2. Pin selectable
LVPECL/LVDS/HCSL interface levels.
Output
Bank A differential output pair 3. Pin selectable
LVPECL/LVDS/HCSL interface levels.
Output
Bank A differential output pair 4. Pin selectable
LVPECL/LVDS/HCSL interface levels.
Power supply ground
13,18,24,37,43,48
GND
Power
14,47
OPMODEA
Input
15,42
VDD
Power
Power supply pins
16
X1
Input
XTAL input, can also be used as single ended input
pin
17
X2
Output
XTAL output. If X1 is used as a single ended input
pin, X2 is to be left open
19,22
IN_SEL
Input
Pulldown
Input clock sele ct. See Table 1 for function. LVCMOS/LVTTL interface levels.
20
IN0+
Input
Pulldown
Reference input 0
21
IN0-
Input
Pull-up/
Pulldown
Inverted reference input 0, internal bias to VDD/2
23,39
OPMODEB
Input
Pulldown
Output mode select for Bank B. See Table 2for functions, LVCMOS/LVTTL interface levels
QB4+
26,25
QB4QB3+
28,27
QB3QB2+
31,30
QB2QB1+
34,33
QB1-
14-0137
Pulldown
Output mode select for Bank A. See Table 2 for functions, LVCMOS/LVTTL interface levels
Output
Bank B differential output pair 4. Pin selectable
LVPECL/LVDS/HCSL interface levels.
Output
Bank B differential output pair 3. Pin selectable
LVPECL/LVDS/HCSL interface levels.
Output
Bank B differential output pair 2. Pin selectable
LVPECL/LVDS/HCSL interface levels.
Output
Bank B differential output pair 1. Pin selectable
LVPECL/LVDS/HCSL interface levels.
2
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High Performance Differential Fanout Buffer
Pinout Table (Continued..)
Pin #
Pin Name
QB0+
36,35
QB0-
Type
Description
Output
Bank B differential output pair 0. Pin selectable
LVPECL/LVDS/HCSL interface levels.
A fixed precision resistor (475ohm) from this pin to
ground provides a reference current for HCSL mode.
If LVPECL or LVDS mode chosen, pin can be left
open
38
Iref
Output
40
IN1-
Input
Pull-up/
Pulldown
Inverted reference input, internal bias to VDD/2
41
IN1+
Input
Pulldown
Reference input 1
44
Ref_Out
Output
46
Sync_OE
Input
Reference output, CMOS
Pulldown
Synchronous output enable for Ref_Out, see Table 3
for functions
Function Table
Table 1: Input select function
IN_SEL [1]
IN_SEL [0]
Function
0
0
IN0 is the selected reference input
0
1
IN1 is the selected reference input
1
X
XTAL is the selected input
Table 2: Output Mode select function
OPMODEA/B [1]
OPMODEA/B [0]
Output Bank A / Bank B Mode
0
0
LVPECL
0
1
LVDS
1
0
HCSL
1
1
Hi-Z
Table 3: Reference output enable function
Sync_OE
Ref_Out
0
Hi-Z
1
Output enabled
Table 4: Illegal input level function
Input illegal status
Output status
Input open
Logic Low
Input both high
Logic Low
Input both low
Logic Low
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PI6C49S1510
High Performance Differential Fanout Buffer
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested)
Storage temperature....................................................-55 to +150ºC
Supply Voltage to Ground Potential (VDD).............. -0.5 to +4.6V
Inputs (Referenced to GND).............................. -0.5 to VDD+0.5V
Clock Output (Referenced to GND)................. -0.5 to VDD+0.5V
Soldering Temperature (Max of 10 seconds).....................+260ºC
Latch up...................................................................................200mA
ESD Protection (Input)................................... 2000 V min (HBM)
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Power Supply Characteristics and Operating Conditions
Symbol
Parameter
VDD
Core Supply Voltage
VDDO
Output Supply Voltage
IDD
Core Power Supply Current
Output Power Supply Current
IDDO
Test Condition
Typ.
Max.
Units
2.375
3.465
V
2.375
3.465
V
90
120
All LVPECL outputs unloaded
110
145
All LVDS outputs loaded
110
125
All HCSL outputs unloaded
70
120
Ambient Operating Temperature
TA
Min.
-40
mA
85
°C
Max.
Units
150
uA
DC Electrical Specifications - Differential Inputs
Symbol
Parameter
IIH
Input High current
Input = VDD
IIL
Input Low current
Input = GND
CIN
Input capacitance
VIH
Input high voltage
VIL
Input low voltage
-0.3
VID
Input Differential Amplitude
PK-PK
0.15
VDD -0.85
V
Common model input voltage
GND + 0.5
VDD -0.85
V
VCM
ISOMUX
Min.
-150
uA
3
PF
VDD+0.3
MUX isolation
14-0137
Typ.
V
-89
4
V
PI6C49S1510
dBc
Rev G
09/18/2014
PI6C49S1510
High Performance Differential Fanout Buffer
DC Electrical Specifications - LVCMOS Inputs
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
IIH
Input High current
Input = VDD
150
uA
IIL
Input Low current
Input = GND
-150
VIH
Input high voltage
VDD =3.3V
2.0
VDD+0.3
V
VIL
Input low voltage
VDD =3.3V
-0.3
0.8
V
VIH
Input high voltage
VDD =2.5V
1.7
VDD+0.3
V
VIL
Input low voltage
VDD =2.5V
-0.3
0.7
V
uA
DC Electrical Specifications- LVPECL Outputs
Parameter
Description
Conditions
Min.
Typ.
Max.
Units
VOH
Output High voltage
VDDO -1.4
VDDO -0.9 V
VOL
Output Low voltage
VDDO -2.1
VDDO -1.7
V
Max.
Units
DC Electrical Specifications- LVDS Outputs
Parameter
Description
Conditions
Min.
Typ.
VOH
Output High voltage
1.433
V
VOL
Output Low voltage
1.064
V
Vocm
Output commode voltage
1.25
V
DVocm
Change in Vocm between completely output states
Ro
Output impedance
85
50
mV
140
W
DC Electrical Specifications – HCSL Outputs
Parameter
Description
VOH
Output High voltage
VOL
Output Low voltage
14-0137
Conditions
5
Min.
Typ.
Max.
Units
520
900
mV
-150
150
mV
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Rev G
09/18/2014
PI6C49S1510
High Performance Differential Fanout Buffer
DC Electrical Specifications – LVCMOS Output
Parameter
Description
VOH
Output High voltage
VOL
Output Low voltage
VOH
Output High voltage
VOL
Output Low voltage
R IUT
Output Impedance
Conditions
Min.
Typ.
Max.
Units
VDDO =3.3V +/-5%, IOH = 8mA
2.3
V
VDDO =2.5V +/- 5%, IOH = 8mA
1.5
V
VDDO =3.3V +/-5%, IOL = -8mA
0.5
V
VDDO =2.5V +/- 5%, IOL = -8mA
0.4
V
VDDO =3.3V +/-5%, IOH = 24mA
2.1
V
VDDO =2.5V +/- 5%, IOH = 16mA
1.5
V
VDDO =3.3V +/-5%, IOL = -24mA
VDDO =2.5V +/- 5%, IOL = -16mA
VDDO = 3.3V ± 5%
17
VDDO = 2.5V ± 5%
22
1
V
0.8
V
Ω
Ω
AC Electrical Specifications – Differential Outputs
Parameter
Description
FOUT
Clock output frequency
Output rise time
Tr
Output fall time
Tf
Output duty cycle
TODC
Output swing Single-ended
VPP
Conditions
Min.
Typ.
Max.
LVPECL, LVDS
1500
HCSL
250
LVPECL
120
150
300
LVDS
120
150
300
HCSL
350
LVPECL
120
150
300
LVDS
120
150
300
HCSL
350
550
LVPECL,
HCSL
48
52
LVDS
47
53
LVPECL outputs @ <1GHz
500
1000
LVPECL outputs @ >1GHz
400
LVDS outputs
250
From 20% to 80%
From 80% to 20%
Frequency<650MHz
Units
MHz
ps
550
ps
%
mV
500
156.25MHz, 12kHz to 20MHz
0.03
ps
156.25MHz, 10kHz to 1MHz
0.02
ps
Absolute crossing voltage
HCSL
460
mV
Total variation of crossing voltage
HCSL
TSK
Output Skew
10 outputs devices,
outputs in same
tank, with same load,
at DUT.
40
TPD
Propagation Delay
LVPECL, LVDS @ 3.3V, 100MHz
1650
ps
HCSL @ 3.3V, 100MHz
2000
ps
Tj
Buffer additive jitter RMS
VCROSS
DVCROSS
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PI6C49S1510
140
mV
70
ps
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PI6C49S1510
High Performance Differential Fanout Buffer
TOD
Valid to HiZ
TOE
HiZ to valid
TP2P Skew
Part to Part Skew
200
ns
200
ns
200
1
ps
Notes:
1. This parameter is guaranteed by design
AC
Electrical Specifications – CMOS
Parameter
Description
FOUT
Ref_Out frequency
Tj
Buffer additive jitter RMS
tr/ tf
Conditions
Min.
XTAL input
10
Typ.
Reference input
Max.
Units
50
MHz
200
MHz
XTAL input
0.3
ps
Reference input
0.03
ps
Rise time, Fall time
CL = 10pF
1.5
ns
TODC
Output duty cycle
CL = 10pF
tPD
Propagation delay
3.3V, 25MHz
tS
Setup time
tSOD
Clock edge to output disable
Ref_Out
2
4
cycles
tSOE
Clock edge to output enable
Ref_Out
2
4
cycles
45
55
%
2700
ps
300
ps
Crystal Characteristics
Parameter
Min.
Max.
Units
50
MHz
Equivalent Series Resistance (ESR)
70
Ω
Shunt Capacitance
7
pF
18
pF
500
µW
Mode of Oscillation
Frequency Range
Load Capacitance
Typ.
Fundamental
10
10
Drive Level
Recommended Crystals
Pericom recommends:
a) GC2500003 XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/GC_GF.pdf
b) FY2500091, SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm
http://www.pericom.com/pdf/datasheets/se/FY_F9.pdf
c) FL2500047, SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm
http://www.pericom.com/pdf/datasheets/se/FL.pdf
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High Performance Differential Fanout Buffer
Propagation Delay
Output Skew
Output Skew TSK
Propagation Delay TPD
VOH
IN+/IN-
IN+/IN-
tPD
tPD
TPLHx
TPHLx
CLKn
VOH
VOL
TSK
TSK
QA/QB
VOL
tR
CLKn+1
tF
VOL
VOH
VOH
VOL
TPLHy
TPHLy
TSK = TPLHy - TPLHx or TSK = TPHLy - TPHLx
TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1
Part to Part Skew
Part-to-Part Skew
VOH
IN+/IN-
TPLH1
TPHL1
Part1 CLK
VOL
VOH
VOL
TSK
TSK
Part2 CLK
VOH
VOL
TPLH2
TPHL2
TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1
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PI6C49S1510
High Performance Differential Fanout Buffer
LVPECL/ LVDS Output Swing vs. Frequency
Propagation Delay vs. Temperature
1.5GHz LVEPCL/ LVDS Waveform
14-0137
2.5V LVPECL Waveform
3.3V LVPECL Waveform
2.5V LVDS Waveform
3.3V LVDS Waveform
9
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High Performance Differential Fanout Buffer
Phase Noise and Additive Jitter
Output phase noise (Dark Blue) vs Input Phase noise (light blue)
Additive jitter is calculated at 156.25MHz~27fs RMS (12kHz to 20MHz). Additive jitter = √(Output jitter2 - Input jitter2)
Total phase jitter with 25MHz XTAL ~ 264fs RMS (12kHz ~20MHz)
Configuration Test Load Board Termination for LVPECL/ LVDS Outputs
LVPECL/ LVDS Buffer
VDDQx
Z o = 50Ω
L = 0 ~ 10 in.
100Ω
Z o = 50Ω
150Ω*
150Ω*
*Remove for LVDS
14-0137
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PI6C49S1510
High Performance Differential Fanout Buffer
Configuration Test Load Board Termination for HCSL Outputs
Rs
33Ω
5%
DUT
Clock
TLA
Rs
33Ω
5%
Clock#
TLB
475Ω
1%
Rp
49.9Ω
1%
Rp
49.9Ω
1%
2pF
5%
2pF
5%
Configuration Test Load Board Termination for LVCMOS Outputs
3.3V ±5%
VDD
VDDO
10pF
GND
14-0137
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PI6C49S1510
High Performance Differential Fanout Buffer
Application Information
Wiring the differential input to accept single ended levels
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and
R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is
only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R1/R2 = 0.609.
VDD
R1
Single Ended
Clock Input
1K
CLK
/CLK
C1
0.1µ
R2
1K
Figure 1. Single-ended input to Differential input device
Power Supply Filtering Techniques
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. All power pins should be individually connected to the power supply plane through vias,
and 0.1μF an 1μF bypass capacitors should be used for each pin.
VDD
VDD
0.1µF
1µF
VDDO
VDDO
0.1µF
14-0137
12
1µF
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Rev G
09/18/2014
PI6C49S1510
High Performance Differential Fanout Buffer
Driving X1 with a Single Ended Input
Rs
CMOS
Clock
0.1µF
Single Ended Input, AC couple
Osc
Input
50Ω
Rs
CMOS
Clock
X1
50Ω
0.1µF
0.1µF
50Ω
X2
0.1µF
Single Ended Input, DC couple
Clock IC crystal input guide
Clock IC
Rs
CMOS
Clock
Differential
Clock
Input
50Ω
Rf
0.1µF
50Ω
VDD
Differential
Clock
Input
50Ω
C_in
C_out
XTL_IN
XTL_OUT
Cb
0.1µF
Crystal (CL)
C1
Cb
C2
LVPECL, DC Couple, Thevenin Equivalent
LVPECL, AC Couple, Thevenin Equivalent
VDDO
VDDO
QAn+/ QBn+
LVPECL
Driver
QAn-/ QBn-
RPU
0.1µF
RT
100Ω Differential
VDDO
RPD
0.1µF
LVPECL
Driver
LVPECL
Receiver
100Ω Differential
VDDO
RPD
LVPECL
Receiver
RPU
RPU
QAn-/ QBn-
RT
RPD
VDDO
RT
VDDO RPU RPD
RPU RPD
2.5V
91Ω
RPD
3.3V 120Ω 82Ω
3.3V 160Ω 120Ω 82Ω
14-0137
RPU
QAn+/ QBn+
2.5V 250Ω 62.5Ω
250Ω 62.5Ω
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High Performance Differential Fanout Buffer
LVDS DC Couple
LVDS AC Couple at Load
0.1µF
QAn+/ QBn+
QAn+/ QBn+
LVDS
Driver
100Ω Differential 100Ω
LVDS
Receiver
kΩ
LVDS
Driver
QAn-/ QBn-
100Ω Differential
kΩ
QAn-/ QBn-
LVDS AC Couple with Internal Termination
Vbias
100Ω
0.1µF
Single Ended LVPECL, DC Couple
VDDO - 2V
QAn+/ QBn+
0.1µF
50Ω
QAn+/ QBn+
50Ω
LVDS
Driver
100Ω
100Ω Differential
LVPECL
Driver
Vbias
50Ω
QAn-/ QBn-
50Ω
0.1µF
QAn-/ QBn-
Single Ended LVPECL, DC Couple, Thevenin
Equivalent
VDDO - 2V
50Ω
Single Ended LVPECL, AC Couple, Thevenin
Equivalent
VDDO - 2V
RPU
QAn+/ QBn+
LVPECL
Driver
QAn+/ QBn+
VDDO
LVPECL
Driver
RPD
VDDO RPU RPD
RPU
3.3V 120Ω 82Ω
14-0137
QAn-/ QBn-
RPD
14
Load
50Ω
50Ω
2.5V 250Ω 62.5Ω
QAn-/ QBn-
0.1µF
RT
50Ω
0.1µF
VDDO RT
3.3V 160Ω
RT
50Ω
2.5V
PI6C49S1510
91Ω
Rev G
09/18/2014
PI6C49S1510
High Performance Differential Fanout Buffer
Clock IC Crystal loading cap. design guide
Clock IC
Rf
CL =crystal spec. loading cap.
C_in
C_in/out = (3~5pF) of IC pin cap.
C_out
XTL_IN
XTL_OUT
Cb
Cb = PCB trace (2~4pF)
C1,C2 = load cap. of design
Crystal (CL)
C1
Cb
Rd = 50 to 100ohm drive level limit
C2
Design guide: C1=C2=2 *CL - (Cb +C_in/out) to meet target +/-ppm < 20 ppm
Example1: Select CL=18 pF crystal, C1=C2=2*(18pF) – (4pF+5pF)=27pF, check datasheet too
Example2: For higher frequency crystal (=>20MHz), can use formula C1=C2=2*(CL-6), can do fine tune of C1, C2 for more accurate
ppm if necessary
Thermal Information
Symbol
Description
ΘJA
Junction-to-ambient thermal resistance
ΘJC
Junction-to-case thermal resistance
14-0137
Condition
23.65 °C/W
Still air
9.10 °C/W
15
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High Performance Differential Fanout Buffer
Packaging Mechanical: 48-Pin TQFN (ZD)
1
DATE: 05
3/09/12
4
Notes:
1. All dimensions are in millimeters, angles are in degrees.
2. Refer JEDEC MO-220/VKKD
3. Thermal Pad Soldering Area
4. Depending on the method of lead termination at the edge of the package,
pull back maybe present.
DESCRIPTION: 48-Contact, Thin Fine Pitch Quad Flat No-Lead (TQFN)
PACKAGE CODE: ZD (ZD48)
REVISION: E
DOCUMENT CONTROL #: PD-2045
12-0458
Ordering Information
Ordering Code
Package Code
Package Type
Operating Temperature
PI6C49S1510ZDIE
ZD
Pb-free & Green, 48-pin TQFN
-40 °C to 85 °C
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. “E” denotes Pb-free and Green
3. Adding an “X” at the end of the ordering code denotes tape and Reel packaging
Pericom Semiconductor Corporation • 1-800-435-2336
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