TABLE 1: ELECTRICAL SPECIFICATIONS AT 25 OC PARAMETER MIN. PRIMARY INDUCTANCE (2-1) VOLTAGE = 0.250Vrms FREQUENCY = 100 KHZ 1105 SPEC LIMITS TYP. MAX. 1228 1350 FIGURE 1: SCHEMATIC DIAGRAM WHITE DOT DENOTES PIN #1 UNITS 1 µHY PRIMARY 8 (12V@160mA) SECONDARY #3 7 (3.3V@600mA) TURN RATIO'S: SECONDARY (8-5) : PRIMARY (2-1) SECONDARY (8-7) : PRIMARY (2-1) BIAS (4-3) : PRIMARY (2-1) ---------------------- 1 : 4.88 1 : 6.917 1 : 3.77 ---------------------- 2 + 3% + 3% + 3% 3 BIAS PRI LEAKAGE IND. (8-5 SHORTED) VOLTAGE = 0.250Vrms FREQUENCY = 100 KHZ -------- -------- 50.0 µHY 4 SECONDARY #2 6 (2.5V@500mA) SECONDARY #1 5 (RTN) NOTE1: HIPOT: PRIMARY TO SECONDARY BIAS TO SECONDARY 3000 3000 --------------- --------------- A) ALL MATERIALS MEET "UL", "CSA" & "IEC" REQUIREMENTS B) TRIPLE BASIC INSULATED SECONDARY. C) VARNISH FINISHED ASSEMBLY. Vrms Vrms FIGURE 2: PHYSICAL DIMENSIONS mm (INCHES) WHITE DOT DENOES PIN#1 8 7 6 5 1 2 3 4 16.8 (.661) MAX CORE TAPED 3.5 (.137) MIN 15.5 (.610) MAX P TSD-1684 M YYWW 15.0 (.590) MAX 1.3 (.051) 1 3.0 (.118) 3 2 3.8 (.150) ∅ 0.6 (.024) 4 11.0 (.433) 8 7 6 REV. 08/13/01 09/05/01 10/25/01 11/01/01 01/21/03 5 UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MM DIMENSIONAL TOLERANCES ARE: DECIMALS ANGLES .X + .25 +0 O 30' .XX + .15 DO NOT SCALE DRAWING DESCRIPTION OF CHANGES ORIGINAL RELEASE UPDATED RELEASE ADDED ASSEMBLY DETAIL PG 3, REMOVED "BIFILAR" FROM BIAS CHANGED PRIMARY TO 3 LAYERS, ADDED MARGIN TAPE TO SEC. SIDE ADD MORE INFO. TO SCHEMATIC TRANSFORMER CONTROL DRAWING PREMIER P/N: TSD-1684 REVISION: 01/21/02 DRAWN BY: PETER PHAM REF: PWR-TOP232 SCALE: NONE SHEET: 1 OF 3 BY PP LL MD MD PP