HD74HCT237 3-to-8-line Decoder/Demultiplexer with Address Latch REJ03D0660–0200 (Previous ADE-205-548) Rev.2.00 Mar 30, 2006 Description The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are high unless G1 is high and G2 is low. The HD74HCT137 is ideally suited for the implementation of glitch free decoders in stored-address applications in bus oriented systems. Features • • • • • • High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 V to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Code (Previous Code) Package Type HD74HCT237RPEL SOP-16 pin (JEDEC) PRSP0016DG-A (FP-16DNV) Package Abbreviation RP Taping Abbreviation (Quantity) EL (2,500 pcs/reel) Function Table Inputs GL X X L L L L L L L L H H: L: X: Enable G1 G2 X H L X H L H L H L H L H L H L H L H L H L High level Low level Irrelevant C X X L L L L H H H H X Select B X X L L H H L L H H X Rev.2.00 Mar 30, 2006 page 1 of 7 Outputs A X X L H L H L H L H X Y0 L L H L L L L L L L Y1 Y2 Y3 Y4 Y5 Y6 Y7 L L L L L L L L L L L L L L L L L L L L L H L L L L L L L H L L L L L L L H L L L L L L L H L L L L L L L H L L L L L L L H L L L L L L L H Output Corresponding to stored address L; all others H HD74HCT237 Pin Arrangement 16 VCC A 1 B 2 B C 3 GL A Y0 15 Y0 C Y1 14 Y1 4 GL Y2 13 Y2 G2 5 G2 Y3 12 Y3 G1 6 G1 Y4 11 Y4 Y7 7 Y7 Y5 10 Y5 GND 8 Y6 9 Y6 (Top view) Logic Diagram A Y0 Y1 B Y2 Y3 Y4 C Y5 Y6 GL G2 G1 Rev.2.00 Mar 30, 2006 page 2 of 7 Y7 HD74HCT237 Absolute Maximum Ratings Item Supply voltage range Input voltage Output voltage Output current DC current drain per VCC, GND DC input diode current DC output diode current Power dissipation per package Storage temperature Symbol VCC VIN VOUT IOUT ICC, IGND IIK IOK PT Tstg Rating –0.5 to +7.0 –0.5 to VCC + 0.5 –0.5 to VCC + 0.5 ±25 ±50 ±20 ±20 500 –65 to +150 Unit V V V mA mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Symbol VCC VIN, VOUT Ratings 4.5 to 5.5 0 to VCC Unit V V Operating temperature Input rise / fall time*1 Ta tr, tf –40 to 85 0 to 500 °C ns Conditions VCC = 4.5 V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Output voltage Symbol VCC (V) VIH VIL VOH 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 5.5 5.5 VOL Input current Iin Quiescent supply current ICC Rev.2.00 Mar 30, 2006 page 3 of 7 Min 2.0 — 4.4 4.18 — — — — Ta = 25°C Typ Max — — — 0.8 — — — — — 0.1 — 0.26 — ±0.1 — 4.0 Ta = –40 to+85°C Min Max 2.0 — — 0.8 4.4 — 4.13 — — 0.1 — 0.33 — ±1.0 — 40 Unit V V V V µA µA Test Conditions Vin = VIH or VIL IOH = –20 µA IOH = –4 mA Vin = VIH or VIL IOL = 20 µA IOL = 4 mA Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA HD74HCT237 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Symbol VCC (V) Propagation delay time tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Pulse width Setup time Hold time Output rise/fall time Input capacitance tw tsu th tTLH tTHL Cin Ta = 25°C Ta = –40 to +85°C Typ Max Min Max 21 37 — 46 25 37 — 46 18 29 — 36 14 29 — 36 16 29 — 36 18 29 — 36 22 38 — 48 27 38 — 48 8 — 20 — 6 — 25 — –1 — 5 — Unit 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Min — — — — — — — — 16 20 5 4.5 — 5 15 — 19 ns — — 5 10 — 10 pF Test Conditions ns A, B or C to Y ns G2 to Y ns G1 to Y ns GL to Y ns ns ns Test Circuit VCC VCC Input Pulse Generator Zout = 50 Ω See Function Table Pulse Generator Zout = 50 Ω Output A Input B Y0 C CL = 50 pF GL G2 G1 Output Y7 Note : 1. CL includes probe and jig capacitance. Rev.2.00 Mar 30, 2006 page 4 of 7 CL = 50 pF HD74HCT237 Waveforms • Waveform – 1 6 ns 6 ns Input A,B,C 90% 90% 1.3 V 10% 10% VCC 90% 1.3 V 10% 90% 10% 1.3 V tW tW tPLH 0V tPHL 90% 1.3 V Output Y VOH 90% 1.3 V 10% 10% tTLH VOL tTHL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. • Waveform – 2 6 ns 6 ns G2 10% 10% 0V tPLH tPHL 90% Output Y VCC 90% 1.3 V 90% 1.3 V VOH 90% 1.3 V 10% 1.3 V 10% tTLH VOL tTHL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. • Waveform – 3 6 ns 6 ns 90% 1.3 V G1 10% 10% tPLH 1.3 V 10% tTLH 0V tPHL 90% Output Y VCC 90% 1.3 V VOH 90% 1.3 V 10% VOL tTHL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. Rev.2.00 Mar 30, 2006 page 5 of 7 HD74HCT237 • Waveform – 4 6 ns 6 ns VCC 90% 1.3 V 90% GL 1.3 V 10% 1.3 V 10% 0V tW tPHL tPLH 90% 1.3 V Output Y VOH 90% 1.3 V 10% 10% tTLH VOL tTHL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. • Waveform – 5 tW Input A,B,C VCC 1.3 V 1.3 V 0V tsu th VCC GL 1.3 V 0V Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. Rev.2.00 Mar 30, 2006 page 6 of 7 HD74HCT237 Package Dimensions JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A *1 Previous Code FP-16DNV MASS[Typ.] 0.15g D F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 9 c *2 Index mark HE E bp Terminal cross section ( Ni/Pd/Au plating ) 1 Z Reference Dimension in Millimeters Symbol 8 e *3 bp x M A L1 A1 θ L y Detail F Rev.2.00 Mar 30, 2006 page 7 of 7 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 9.90 10.30 3.95 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 5.80 6.10 6.20 1.27 0.25 0.15 0.635 0.40 0.60 1.27 1.08 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 © 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .6.0