ADC-208A 8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible) FEATURES PRODUCT OVERVIEW 8-bit flash A/D converter The ADC-208A utilizes an advanced VLSI 1.2 micron CMOS in providing 20MHz sampling rates at 8-bits. The flexibility of the design architecture and process delivers latch-up free operation without external components and operation over the full military range. 20MHz sampling rate 10MHz full-power bandwidth Sample-hold not required Low power CMOS The ADC-208A is mechanically and electrically equivalent to the ADC-208 Series, with the exception of the OVERFLOW (pin 13) and ENABLE (pins 11 and 12) functions. These functions are not offered on the ADC-208A. +5Vdc operation 1.2 Micron CMOS 8-Bit latched outputs Surface-mount version No missing codes Pin 1 INPUT/OUTPUT CONNECTIONS FUNCTION Pin FUNCTION 24 BIT 8 (LSB) VDD CLOCK INPUT –REFERENCE 23 BIT 7 3 22 BIT 6 4 ANA/DIG GND (VSS) 21 BIT 5 5 ANALOG INPUT 20 REF 1/4 FS 6 REF MIDPOINT 19 VDD 7 ANALOG INPUT 18 REF 3/4 FS 8 ANA/DIG GND (VSS) 17 BIT 4 9 +REFERENCE 16 BIT 3 10 VDD 15 BIT 2 11 N.C. 14 BIT 1 (MSB) 12 N.C. 13 N.C. 2 Figure 1. ADC-208A Block Diagram DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 06 Jul 2015 ADC-208A.B05 Page 1 of 4 ADC-208A 8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible) ABSOLUTE MAXIMUM RATINGS PARAMETERS Power Supply Voltage (VDD Pin 1, 10, 19) LIMITS UNITS –0.5 to +7 Volts Digital Inputs –0.5 to +5.5 Volts Analog Input –0.5 to (+VDD +0.5) Volts Reference Inputs –0.5 to +VDD Volts Digital Outputs (short circuit protected to ground) –0.5 to +5.5 Volts Lead Temperature (10 sec. max.) Storage Temperature +300 °C –65 to +150 °C FUNCTIONAL SPECIFICATIONS (Typical at +5V power, +25°C, 20MHz clock, +REFERENCE = +5V, –REFERENCE = ground, unless noted) ANALOG INPUT MIN. Single-Ended, Non-Isolated 0 Input Range DC - 20MHz Analog Input Capacitance – (static - Pin 5 to 7) – (dynamic - Pin 5 to 7) – Reference Ladder Resistance –0.5 Reference Input (Note 5) DIGITAL INPUTS Logic Levels 3.2 Logic "1" — Logic "0" Logic Loading — Logic Loading "1" — Logic Loading "0" 15 Clock Low Pulse Width DIGITAL OUTPUTS Logic Levels 2.4 Logic "1" — Logic "0" Logic Loading 4 Logic Loading "1" 4 Logic Loading "0" Output Data Valid Delay From Rising Clock Edge 5 99% probability 100% probability 5 +25°C — –55°C to +125°C 8 Data Output Resolution Data Coding PERFORMANCE 15 Sampling Rate ➁ 10 Full Power Bandwidth Diff. Linearity @ +25°C (See tech note 7) — Code Transitions — Center of Codes TYP. MAX. UNITS – +5.0 Volts 20 64 500 – – – – VDD +0.5 pF pF Ohms Volts — — — 0.8 Volts Volts +1 +1 25 +5 +5 — μA μA nSec 4.5 — 5.0 0.4 Volts Volts — — — — mA mA 10 15 nSec 10 25 — 40 — — Straight binary nSec nSec Bits 20 — — — MSPS MHz ±0.5 ±0.25 ±1.0 — LSB LSB ±1.0 — LSB LSB ±1/2 LSB Diff. Linearity Over Temp. — ±0.5 Code Transitions — ±0.25 Center of Codes Int. Linearity @ +25°C (See tech note 4)(ref. adjusted) — — End-point DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA — Best-fit Line Int. Linearity Over Temp. (ref. adjusted) — Best-fit Line PERFORMANCE MIN. Int. Linearity @ +25°C (ref. unadjusted) — End-point — Best-fit Line Int. Linearity Over Temp. (ref. unadjusted) — End-point — Best-fit Line — Zero-Scale Offset — ±1/2 LSB ±1/2 ±1 LSB TYP. MAX. UNITS ±2 ±1.6 ±2.6 ±1.9 LSB LSB ±2.3 ±1.8 ±1 ±2.6 ±2.0 ±2 LSB LSB LSB ±3 — — — — LSB % degrees ns ps (Code "0" to "1" transition) — ±1.5 Gain Error — 2 Differential Gain ➂ — 1.1 Differential Phase ➂ — 8 Aperture Delay — 50 Aperture Jitter Harmonic Distortion (8MHz second order harm.) –40 –46 — dB Ref. bandwidth (See tech note 5) — 10 — MHz Power Supply Rejection — ±0.02 ±0.05 %FSR/%Vs No Missing Codes POWER REQUIREMENTS Power Supply Range (+VDD) Power Supply Current +25°C +85°C –40°C +125°C –55°C Power Dissipation +25°C +85°C –40°C +125°C –55°C PHYSICAL/ENVIRONMENTAL Operating Temp. Range, Case: MC/LC Versions MC-C/LC-C Versions ME/LE Versions ME-C/LE-C Versions MM/LM/QL Versions MM-C/LM-C/QL-C Versions Storage Temp. Range Package Type DIP 24-pin ceramic DIP LCC 24-pin ceramic LCC Over the operating temperature range +3.0 +5.0 +5.5 Volts — — — — — +45 +40 +50 +40 +50 +65 +60 +70 +60 +70 mA mA mA mA mA — — — — — 225 200 250 200 250 325 300 350 300 350 mW mW mW mW mW 0 0 –40 –40 –55 –55 –65 — — — — — — — +70 +70 +100 +100 +125 +125 +150 °C °C °C °C °C °C °C Footnotes: ➀ Maximum input impedance is a function of clock frequency. ➁ At full-power input. ➂ For 10-step, 40 IRE NTSC ramp test. • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 06 Jul 2015 ADC-208A.B05 Page 2 of 4 ADC-208A 8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible) TECHNICAL NOTES Table 1. ADC-208A Output Code 1. The Reference ladder is floating with respect to VDD and may be referenced anywhere within the specified limits. AC modulation of the reference voltage may also be utilized; contact DATEL for further information. 2. Clock Pulse Width – To improve performance when input signals may exceed Nyquist bandwidths, the clock duty cycle can be adjusted so that the low portion (sample mode) of the clock pulse is 15nSec wide. Reducing the sampling time period minimizes the amount the input voltage slews and prevents the comparators from saturating. 3. A full-scale input produces all "1" on the data outputs. 4. DATEL uses the conservative definitions when specifying Intergal Linearity (end-point) and Differential Linearity (code transition). The specifications using the less conservative definition have also been provided as a comparative specification for products specified this way. 5. The process that is used to fabricate the ADC-208A eliminates the latchup phenomena that has plagued CMOS devices in the past. These converters do not require external protection diodes. 6. For clock rates less than 100kHz, there may be some degradation in offset and differential nonlinearity. Performance may be improved by increasing the clock duty cycle (decreasing the time spent in the sample mode). 7. Connect the converter appropriately; a typical connection circuit is shown in Figure 2. Then apply an appropriate clock input.The reference input should be held to ±0.1% accuracy or better. Do not use the +5V power supply as a reference without precision regulation and high-frequency decoupling capacitors. 8. Zero Adjustment - Adjusting the voltage at –REFERENCE (pin 3) adjusts the offset or zero of the device. Pin 3 can be tied to GROUND for operation without adjustments 9. Full Scale Adjustment - Adjusting the voltage at +REFERENCE (pin 9) adjusts the gain of the device. Pin 9 can be tied directly to a +5V reference for operation without adjustment. 10. Integral Nonlinearity Adjustments - Provision is made for optional adjustment of Integral Nonlinearity through access of the reference's ¼, ½, and ¾ full scale points. For example, the REF. MIDPOINT (pin 6) can be tied to a precision voltage halfway between +REFERENCE and –REFERENCE. Pins 6, 18 and 20 should be bypassed to GROUND through 0.1μF capacitors for operation without INL adjustments ANALOG INPUT CODE DATA 1234 DATA 5678 DECIMAL HEX 0.00V Zero 0000 0000 0000 0 00 +0.02V +1 LSB 0000 0001 1 01 +1.28V +¼ FS 0100 0000 64 40 +2.54V +½ FS-ILSB 0111 1111 127 7F +2.56V +½ FS 1000 0000 128 80 +2.58V +½ FS+ILSB 1000 0001 129 81 +3.84V +¾ FS 1100 0000 192 C0 +5.10V +FS 1111 1111 255 FF Note: Values shown here are for a +5.12Vdc reference. Scale other refereces proportionally. (+REF=+5.12V, –REF=GND, ¼, ½, and ¾ References FS=No Connection) Figure 2. ADC-208A Typical Connection Diagram DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: [email protected] 06 Jul 2015 ADC-208A.B05 Page 3 of 4 ADC-208A 8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible) MECHNICAL DIMENSIONS ADC-208A DIP ADC-208A LCC 1.250 (31.7) DATEL 0.500 (12.7) ADC-208A 0.610 (15.5) PIN 1 IDENTIFIER 0.190 (4.9) 0.190 (4.9) 0.050 (1.3) 0.020 (0.5) AUTO ZERO 01 0.38 (9.7) 0.100 (2.5) SAMPLE N AUTO ZERO 02 01 SAMPLE N+1 AUTO ZERO SAMPLE N+2 01 02 02 N+1 DATA N DATA 40nSec max. 40nSec max. Figure 3. Timing Diagram DATEL is a registered trademark of DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA ORDERING INFORMATION MODEL ADC-208AMC ADC-208AMC-C ADC-208AME ADC-208AME-C ADC-208AMM ADC-208AMM-C ADC-208AMM-QL ADC-208AMM-QL-C ADC-208ALC ADC-208ALC-C ADC-208ALE ADC-208ALE-C ADC-208ALM ADC-208ALM-C ADC-208ALM-QL ADC-208ALM-QL-C TEMP. RANGE 0°C to +70°C 0°C to +70°C –40°C to +100°C –40°C to +100°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C 0°C to +70°C 0°C to +70°C –40°C to +100°C –40°C to +100°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C PACKAGE 24-pin DIP 24-pin DIP 24-pin DIP 24-pin DIP 24-pin DIP 24-pin DIP 24-pin DIP 24-pin DIP 24-pin LCC 24-pin LCC 24-pin LCC 24-pin LCC 24-pin LCC 24-pin LCC 24-pin LCC 24-pin LCC ROHS No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes DATEL, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. ITAR and ISO 9001/14001 REGISTERED © 2015 DATEL, Inc. www.datel.com • e-mail: [email protected] 06 Jul 2015 ADC-208A.B05 Page 4 of 4